/*****************************************************************************
 *
 *   SPDX-License-Identifier: BSD-3-Clause
 *   Copyright(c) 2007-2026 Intel Corporation
 * 
 *   These contents may have been developed with support from one or more
 *   Intel-operated generative artificial intelligence solutions.
 *
 *****************************************************************************/
/*****************************************************************************
 * @file icp_accel_devices.h
 *
 * @defgroup Acceleration Driver Framework
 *
 * @ingroup icp_Adf
 *
 * @description
 *      This is the top level header file that contains the layout of the ADF
 *      icp_accel_dev_t structure and related macros/definitions.
 *      It can be used to dereference the icp_accel_dev_t *passed into upper
 *      layers.
 *
 *****************************************************************************/

#ifndef ICP_ACCEL_DEVICES_H_
#define ICP_ACCEL_DEVICES_H_

#include "cpa.h"
#include "Osal.h"

#define MAX_DEVICE_NAME_SIZE 32
#define ADF_DEVICE_NAME_LENGTH 32
#define ADF_CFG_MAX_STR_LEN 128
#define ADF_CFG_MAX_KEY_LEN_IN_BYTES ADF_CFG_MAX_STR_LEN
#define ADF_CFG_MAX_VAL_LEN_IN_BYTES ADF_CFG_MAX_STR_LEN
#define ADF_CFG_MAX_SECTION_LEN_IN_BYTES ADF_CFG_MAX_STR_LEN
/* Max PFs = num sockets x num PFs per socket */
#define ADF_MAX_PF_DEVICES 256
/* Max devices is max PFs * num VFs per PF */
#define ADF_MAX_DEVICES (ADF_MAX_PF_DEVICES * 16)

enum dev_sku_info
{
    DEV_SKU_1 = 0,
    DEV_SKU_2,
    DEV_SKU_3,
    DEV_SKU_4,
    DEV_SKU_VF,
    DEV_SKU_UNKNOWN,
};

enum adf_event
{
    ADF_EVENT_INIT = 0,
    ADF_EVENT_START,
    ADF_EVENT_STOP,
    ADF_EVENT_SHUTDOWN,
    ADF_EVENT_RESTARTING,
    ADF_EVENT_RESTARTED,
    ADF_EVENT_ERROR,
};

#define ADF_CFG_NO_INSTANCE 0xFFFFFFFF
#define ADF_CTL_DEVICE_NAME "/dev/qat_adf_ctl"

#define ADF_DEVICE_TYPE_LENGTH 16
#define BIT(n) (1 << n)

/**
 *****************************************************************************
 * @ingroup icp_AdfAccelHandle
 *
 * @description
 *      Accelerator capabilities
 *
 *****************************************************************************/
typedef enum
{
    ICP_ACCEL_CAPABILITIES_NULL = 0,
    ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = 0x01,
    ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = 0x02,
    ICP_ACCEL_CAPABILITIES_CIPHER = 0x04,
    ICP_ACCEL_CAPABILITIES_AUTHENTICATION = 0x08,
    ICP_ACCEL_CAPABILITIES_COMPRESSION = 0x20,
    ICP_ACCEL_CAPABILITIES_DEPRECATED = 0x40,
    ICP_ACCEL_CAPABILITIES_5G = 0x80,
    ICP_ACCEL_CAPABILITIES_CRYPTO_ZUC = 0x100,
    ICP_ACCEL_CAPABILITIES_CRYPTO_SHA3 = 0x200,
    ICP_ACCEL_CAPABILITIES_RESERVED = 0x400,
    ICP_ACCEL_CAPABILITIES_RL = 0x800,
    ICP_ACCEL_CAPABILITIES_HKDF = 0x1000,
    ICP_ACCEL_CAPABILITIES_ECEDMONT = 0x2000,
    ICP_ACCEL_CAPABILITIES_EXT_ALGCHAIN = 0x4000,
    ICP_ACCEL_CAPABILITIES_SHA3_EXT = 0x8000,
    ICP_ACCEL_CAPABILITIES_AESGCM_SPC = 0x10000,
    ICP_ACCEL_CAPABILITIES_CHACHA_POLY = 0x20000,
    ICP_ACCEL_CAPABILITIES_SM2 = 0x40000,
    ICP_ACCEL_CAPABILITIES_SM3 = 0x80000,
    ICP_ACCEL_CAPABILITIES_SM4 = 0x100000,
    ICP_ACCEL_CAPABILITIES_INLINE = 0x200000,
    ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY = 0x400000,
    ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64 = 0x800000,
    ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION = 0x1000000,
    ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION = 0x2000000,
    ICP_ACCEL_CAPABILITIES_AES_V2 = 0x4000000,
    ICP_ACCEL_CAPABILITIES_KPT = 0x8000000,
    /* Reserved capability for CIPHER_CRC */
    ICP_ACCEL_CAPABILITIES_ZUC_256 = 0x20000000,
    ICP_ACCEL_CAPABILITIES_WIRELESS_CRYPTO_EXT = 0x40000000,
} icp_accel_capabilities_t;

#define IS_ASYM_SUPPORTED(icp_capabilities)                                    \
    (icp_capabilities & ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC)
#define IS_SYM_SUPPORTED(icp_capabilities)                                     \
    (icp_capabilities & ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC)
#define IS_DC_SUPPORTED(icp_capabilities)                                      \
    (icp_capabilities & ICP_ACCEL_CAPABILITIES_COMPRESSION)
#define IS_DC_ONLY(icp_capabilities)                                           \
    (!IS_ASYM_SUPPORTED(icp_capabilities) &&                                   \
     !IS_SYM_SUPPORTED(icp_capabilities) && IS_DC_SUPPORTED(icp_capabilities))

enum serv_type
{
    SERV_TYPE_DC = BIT(0),
    SERV_TYPE_SYM = BIT(1),
    SERV_TYPE_ASYM = BIT(2),
    SERV_TYPE_DECOMP = BIT(4),
    SERV_TYPE_CY = (SERV_TYPE_SYM + SERV_TYPE_ASYM),
    SERV_TYPE_SYM_DC = (SERV_TYPE_SYM + SERV_TYPE_DC),
    SERV_TYPE_ASYM_DC = (SERV_TYPE_ASYM + SERV_TYPE_DC),
    SERV_TYPE_DC_DECOMP = (SERV_TYPE_DC + SERV_TYPE_DECOMP),
    SERV_TYPE_SYM_DECOMP = (SERV_TYPE_SYM + SERV_TYPE_DECOMP),
    SERV_TYPE_ASYM_DECOMP = (SERV_TYPE_ASYM + SERV_TYPE_DECOMP),
    SERV_TYPE_CY_DC = (SERV_TYPE_SYM + SERV_TYPE_ASYM + SERV_TYPE_DC),
    SERV_TYPE_CY_DECOMP = (SERV_TYPE_SYM + SERV_TYPE_ASYM + SERV_TYPE_DECOMP),
    SERV_TYPE_SYM_DC_DECOMP = (SERV_TYPE_SYM + SERV_TYPE_DC + SERV_TYPE_DECOMP),
    SERV_TYPE_ASYM_DC_DECOMP =
        (SERV_TYPE_ASYM + SERV_TYPE_DC + SERV_TYPE_DECOMP),
};

/**
 *****************************************************************************
 * @ingroup icp_AdfAccelHandle
 *
 * @description
 *      Device Configuration Data Structure
 *
 *****************************************************************************/
typedef enum device_type_e
{
    DEVICE_UNKNOWN = 0,
    DEVICE_DH895XCC,
    DEVICE_DH895XCCVF,
    DEVICE_C62X,
    DEVICE_C62XVF,
    DEVICE_C3XXX,
    DEVICE_C3XXXVF,
    DEVICE_D15XX,
    DEVICE_D15XXVF,
    DEVICE_200XX,
    DEVICE_200XXVF,
    DEVICE_C4XXX,
    DEVICE_C4XXXVF,
    DEVICE_4XXX,
    DEVICE_4XXXVF,
    DEVICE_420XX,
    DEVICE_420XXVF,
    DEVICE_6XXX,
    DEVICE_6XXXVF,
} device_type_t;

#define QAT_GEN4_STR "4xxx"

/*
 * Macro for checking if given device_type_t enum value
 * belongs to QAT 4 generation.
 */
#ifdef IS_QAT_GEN4
#undef IS_QAT_GEN4
#endif
#define IS_QAT_GEN4(dev_type)                                                  \
    ({                                                                         \
        int _dt = dev_type;                                                    \
        _dt == DEVICE_4XXX || _dt == DEVICE_4XXXVF || _dt == DEVICE_420XX ||   \
            _dt == DEVICE_420XXVF;                                             \
    })

#ifdef IS_QAT_GEN4_2
#undef IS_QAT_GEN4_2
#endif
#define IS_QAT_GEN4_2(dev_type)                                                \
    ({                                                                         \
        int _dt = dev_type;                                                    \
        _dt == DEVICE_420XX || _dt == DEVICE_420XXVF;                          \
    })

/*
 * Macro for checking if given device_type_t enum value
 * belongs to QAT 6 generation.
 */
#ifdef IS_QAT_6XXX
#undef IS_QAT_6XXX
#endif
#define IS_QAT_6XXX(dev_type)                                                  \
    ({                                                                         \
        int _dt = dev_type;                                                    \
        _dt == DEVICE_6XXX || _dt == DEVICE_6XXXVF;                            \
    })

/*
 * Enumeration on Service Type
 */
typedef enum adf_service_type_s
{
    ADF_SERVICE_CRYPTO,
    ADF_SERVICE_COMPRESS,
    ADF_SERVICE_MAX /* this is always the last one */
} adf_service_type_t;

struct fw_caps_accel
{
    uint16_t comp_algos;
    uint16_t cksum_algos;
    uint32_t deflate_caps;
    uint16_t lz4_caps;
    uint16_t lz4s_caps;
    uint16_t zstd_caps;
    uint8_t is_fw_caps;
};

/* Enumeration on Ring Queue modes */
typedef enum adf_ring_queue_mode
{
    ADF_RING_WQ_MODE = 0,
} adf_ring_queue_mode_t;

typedef struct accel_dev_s
{
    /* Some generic information */
    Cpa32U accelId;
    device_type_t deviceType;                    /* Device Type */
    char deviceName[ADF_DEVICE_TYPE_LENGTH + 1]; /* Device name for SAL */
    Cpa16U services;
    Cpa32U accelCapabilitiesMask; /* Accelerator's capabilities mask */
    Cpa32U cipherCapabilitiesMask; /* Cipher algorithms capabilities mask */
    Cpa32U hashCapabilitiesMask;   /* Hash algorithms capabilities mask */
    Cpa32U asymCapabilitiesMask;   /* Asym algorithms capabilities mask */
    Cpa32U dcExtendedFeatures;    /* bit field of features */
    struct fw_caps_accel fw_caps;
    OsalAtomic usageCounter;      /* Prevents shutting down the dev if not 0 */
    void *pSalHandle;             /* For SAL */
    void *pQatStats;              /* For QATAL/SAL stats */
    void *ringInfoCallBack;       /* Callback for user space ring enabling */
    Cpa32U adfSubsystemStatus;    /* Status of ADF and registered subsystems */
    Cpa32S numa_node; /* Physical processor to which the dev is connected */
    enum dev_sku_info sku;
    Cpa32U arb_mask;
    void *accel;
    Cpa32U maxNumBanks;
    Cpa32U maxNumRingsPerBank;
    void *banks;    /* banks information */
    Cpa32U deviceMemAvail; /* Device memory for intermediate buffers */
    Cpa32U pciDevId;
    CpaBoolean isVf; /* Device runs on a virtual function */
    void *ioPriv;
    adf_ring_queue_mode_t ringMode;
} icp_accel_dev_t;

/*
 * This structure must be identical to CpaPfInfo which
 * defined in "icp_sal_user.h"
 */
typedef struct accel_pf_info_s
{
    Cpa32U pkg_id;
    Cpa16U domain;
    Cpa16U bdf;
    char device_gen[ADF_DEVICE_TYPE_LENGTH + 1];
} icp_accel_pf_info_t;

#endif /* ICP_ACCEL_HANDLE_H_ */
