/*
 *   SPDX-License-Identifier: BSD-3-Clause
 *   Copyright(c) 2007-2026 Intel Corporation
 * 
 *   These contents may have been developed with support from one or more
 *   Intel-operated generative artificial intelligence solutions.
 */
/*
 ****************************************************************************
 * @file icp_qat_hw_51_comp_defs.h, (autogenerated at 07-27-23 23:18)
 * @defgroup icp_qat_hw_comp_51
 * @ingroup icp_qat_hw_comp_51
 * @description
 *     This file represents the HW configuration CSR definitions
 ****************************************************************************
 */

#ifndef _ICP_QAT_HW_51_COMP_DEFS_H
#define _ICP_QAT_HW_51_COMP_DEFS_H

/*****************************************************************************/
/* Slice Operation Mode (SOM) - located in upper 32 bit */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SOM_CONTROL_BITPOS 28
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SOM_CONTROL_MASK 0x3
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible SOM_CONTROL field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_SOM_CONTROL_NORMAL_MODE = 0x0,
    /* Normal mode. */
    ICP_QAT_HW_COMP_51_SOM_CONTROL_DICTIONARY_MODE = 0x1,
    /* Dictionary mode */
    ICP_QAT_HW_COMP_51_SOM_CONTROL_INPUT_CRC = 0x2,
    /* Input CRC Mode */
    ICP_QAT_HW_COMP_51_SOM_CONTROL_RESERVED_MODE = 0x3,
    /* Reserved. */
} icp_qat_hw_comp_51_som_control_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SOM_CONTROL_DEFAULT_VAL                  \
    ICP_QAT_HW_COMP_51_SOM_CONTROL_NORMAL_MODE

/*****************************************************************************/
/* Skip Hash Read, located in upper 32 bit */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_RD_CONTROL_BITPOS 27
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible SKIP_HASH_RD_CONTROL field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_SKIP_HASH_RD_CONTROL_NO_SKIP = 0x0,
    /* When set to 0, hash reads are not skipped.  */
    ICP_QAT_HW_COMP_51_SKIP_HASH_RD_CONTROL_SKIP_HASH_READS = 0x1,
    /* Hash reads are skipped. */
} icp_qat_hw_comp_51_skip_hash_rd_control_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_RD_CONTROL_DEFAULT_VAL         \
    ICP_QAT_HW_COMP_51_SKIP_HASH_RD_CONTROL_NO_SKIP

/*****************************************************************************/
/* Bypass Compression, located in upper 32 bit */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYPASS_COMPRESSION_BITPOS 25
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYPASS_COMPRESSION_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible BYPASS_COMPRESSION field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_BYPASS_COMPRESSION_DISABLED = 0x0,
    /* 0 - CnV slice is used to process a compression job */
    ICP_QAT_HW_COMP_51_BYPASS_COMPRESSION_ENABLED = 0x1,
    /* 0 - CnV slice is used to process a decompression job */
} icp_qat_hw_comp_51_bypass_compression_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYPASS_COMPRESSION_DEFAULT_VAL           \
    ICP_QAT_HW_COMP_51_BYPASS_COMPRESSION_DISABLED

/*****************************************************************************/
/* Delayed Match Mode Algorithm, located in upper 32 bit */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_DMM_ALGORITHM_BITPOS 22
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_DMM_ALGORITHM_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible DMM_ALGORITHM field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_DMM_ALGORITHM_EDMM_ENABLED = 0x0,
    /* 0 - EXTENDED_DELAY_MATCH_MODE enabled  */
    ICP_QAT_HW_COMP_51_DMM_ALGORITHM_ZSTD_DMM_LITE = 0x1,
    /* 1 - ZSTD DMM-Lite enabled */
} icp_qat_hw_comp_51_dmm_algorithm_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_DMM_ALGORITHM_DEFAULT_VAL                \
    ICP_QAT_HW_COMP_51_DMM_ALGORITHM_EDMM_ENABLED

/*****************************************************************************/
/* CHKN_BIT: Disable Token Fusion (INTERNAL_ONLY), located in upper 32 bit */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_TOKEN_FUSION_INTERNAL_ONLY_BITPOS 21
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_TOKEN_FUSION_INTERNAL_ONLY_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible TOKEN_FUSION_INTERNAL_ONLY field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_TOKEN_FUSION_INTERNAL_ONLY_ENABLED = 0x0,
    /* 0 - Token Fusion is enabled */
    ICP_QAT_HW_COMP_51_TOKEN_FUSION_INTERNAL_ONLY_DISABLED = 0x1,
    /* 0 - Token Fusion is disabled */
} icp_qat_hw_comp_51_token_fusion_internal_only_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_TOKEN_FUSION_INTERNAL_ONLY_DEFAULT_VAL   \
    ICP_QAT_HW_COMP_51_TOKEN_FUSION_INTERNAL_ONLY_ENABLED

/*****************************************************************************/
/* Block Maximum Size (BMS), located in upper 32 bit */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BMS_BITPOS 19
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BMS_MASK 0x3
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible BMS field values
 *      Note, this enum is reflected on the QuickAssist API and the library
 *      depends on both having the same values. So the existing values must
 *      never change and if this enum is extended then CpaDcCompLZ4BlockMaxSize
 *      and icp_qat_hw_comp_20_lbms_t must also be extended.
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_BMS_BMS_64KB = 0x0,
    /* Block Max Size (BMS) == 64 KB - LZ4, ZSTD, ILZ77, LZ4s=don't care */
    ICP_QAT_HW_COMP_51_BMS_BMS_256KB = 0x1,
    /* Block Max Size (BMS) == 256 KB - LZ4 only */
    ICP_QAT_HW_COMP_51_BMS_BMS_1MB = 0x2,
    /* Block Max Size (BMS) == 1 MB - LZ4 only */
    ICP_QAT_HW_COMP_51_BMS_BMS_4MB = 0x3,
    /* Block Max Size (BMS) == 4 MB - LZ4 only */
} icp_qat_hw_comp_51_bms_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BMS_DEFAULT_VAL                          \
    ICP_QAT_HW_COMP_51_BMS_BMS_64KB

/*****************************************************************************/
/* SCB Mode Reset Mask, located in upper 32 bit */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SCB_MODE_RESET_MASK_BITPOS 18
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible SCB_MODE_RESET_MASK field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_SCB_MODE_RESET_MASK_DO_NOT_RESET_HB_HT = 0x0,
    /* Do not reset HB, HT at the block boundary */
    ICP_QAT_HW_COMP_51_SCB_MODE_RESET_MASK_RESET_HB_HT = 0x1,
    /* Reset HB, HT at the block boundary */
} icp_qat_hw_comp_51_scb_mode_reset_mask_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SCB_MODE_RESET_MASK_DEFAULT_VAL          \
    ICP_QAT_HW_COMP_51_SCB_MODE_RESET_MASK_DO_NOT_RESET_HB_HT

/*****************************************************************************/
/* ZSTD Frame Gen/Decode Enable, located in upper 32 bit */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_BITPOS 2
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible ZSTD_FRAME_GEN_DEC_EN field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_DISABLE = 0x0,
    /* ZSTD Frame header and content checksum generation/decode disabled */
    ICP_QAT_HW_COMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_ENABLE = 0x1,
    /* ZSTD Frame header and content checksum generation/decode enabled */
} icp_qat_hw_comp_51_zstd_frame_gen_dec_en_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_DEFAULT_VAL        \
    ICP_QAT_HW_COMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_ENABLE

/*****************************************************************************/
/* CnV Disable, located in upper 32 bit */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_CNV_DISABLE_BITPOS 1
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_CNV_DISABLE_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible CNV_DISABLE field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_CNV_DISABLE_CNV_ENABLED = 0x0,
    /* CNV is enabled */
    ICP_QAT_HW_COMP_51_CNV_DISABLE_CNV_DISABLED = 0x1,
    /* CNV is disabled */
} icp_qat_hw_comp_51_cnv_disable_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_CNV_DISABLE_DEFAULT_VAL                  \
    ICP_QAT_HW_COMP_51_CNV_DISABLE_CNV_ENABLED

/*****************************************************************************/
/* Auto Select Best Disable, located in upper 32 bit */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ASB_DISABLE_BITPOS 0
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ASB_DISABLE_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible ASB_DISABLE field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_ASB_DISABLE_ASB_ENABLED = 0x0,
    /* ASB is enabled */
    ICP_QAT_HW_COMP_51_ASB_DISABLE_ASB_DISABLED = 0x1,
    /* ASB is disabled */
} icp_qat_hw_comp_51_asb_disable_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ASB_DISABLE_DEFAULT_VAL                  \
    ICP_QAT_HW_COMP_51_ASB_DISABLE_ASB_ENABLED

/*****************************************************************************/
/* CHKN_BIT: Speculative Decoder Disable (INTERNAL_ONLY), located in lower 32
 * bit
 */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_BITPOS 21
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible SPEC_DECODER_INTERNAL_ONLY field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_SPEC_DECODER_INTERNAL_ONLY_NORMAL = 0x0,
    /* 0 - Normal Mode using Speculative Decoder */
    ICP_QAT_HW_COMP_51_SPEC_DECODER_INTERNAL_ONLY_DISABLED = 0x1,
    /* 1 - Speculative Decoder disabled */
} icp_qat_hw_comp_51_spec_decoder_internal_only_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_DEFAULT_VAL   \
    ICP_QAT_HW_COMP_51_SPEC_DECODER_INTERNAL_ONLY_NORMAL

/*****************************************************************************/
/* CHKN_BIT: Mini XCAM Disable (INTERNAL_ONLY), located in lower 32 bit */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_BITPOS 20
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible MINI_XCAM_INTERNAL_ONLY field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_MINI_XCAM_INTERNAL_ONLY_NORMAL = 0x0,
    /* 0 - Normal Mode using Speculative Decoder */
    ICP_QAT_HW_COMP_51_MINI_XCAM_INTERNAL_ONLY_DISABLED = 0x1,
    /* 1 - Speculative Decoder disabled */
} icp_qat_hw_comp_51_mini_xcam_internal_only_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_DEFAULT_VAL      \
    ICP_QAT_HW_COMP_51_MINI_XCAM_INTERNAL_ONLY_NORMAL

/*****************************************************************************/
/* CHKN_BIT: Disable ZSTD Repeated_Offset encoding (INTERNAL_ONLY), located in
 * lower 32 bit */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_REP_OFF_ENC_INTERNAL_ONLY_BITPOS 19
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_REP_OFF_ENC_INTERNAL_ONLY_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible REP_OFF_ENC_INTERNAL_ONLY field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_REP_OFF_ENC_INTERNAL_ONLY_ENABLED = 0x0,
    /* 0 - Repeated_Offset encoding is enabled */
    ICP_QAT_HW_COMP_51_REP_OFF_ENC_INTERNAL_ONLY_DISABLED = 0x1,
    /* 1 - Repeated_Offset encoding is disabled */
} icp_qat_hw_comp_51_rep_off_enc_internal_only_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_REP_OFF_ENC_INTERNAL_ONLY_DEFAULT_VAL    \
    ICP_QAT_HW_COMP_51_REP_OFF_ENC_INTERNAL_ONLY_ENABLED

/*****************************************************************************/
/* Enable Programmable Block Drop (INTERNAL_ONLY), located in lower 32 bit */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_PROG_BLOCK_DROP_INTERNAL_ONLY_BITPOS 18
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_PROG_BLOCK_DROP_INTERNAL_ONLY_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible PROG_BLOCK_DROP_INTERNAL_ONLY field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_PROG_BLOCK_DROP_INTERNAL_ONLY_DISABLE = 0x0,
    /* 0 - Disable Programmable Block Drop */
    ICP_QAT_HW_COMP_51_PROG_BLOCK_DROP_INTERNAL_ONLY_ENABLE = 0x1,
    /* 1 - Enable Programmable Block Drop */
} icp_qat_hw_comp_51_prog_block_drop_internal_only_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_PROG_BLOCK_DROP_INTERNAL_ONLY_DEFAULT_VAL \
    ICP_QAT_HW_COMP_51_PROG_BLOCK_DROP_INTERNAL_ONLY_DISABLE

/*****************************************************************************/
/* CHKN_BIT: Enable skip hash override (INTERNAL_ONLY), located in lower 32 bit
 */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_BITPOS 17
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible SKIP_HASH_OVERRIDE_INTERNAL_ONLY field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_DETERMINE_HASH_PARAMS =
        0x0,
    /* 0 - HW will determine param values based on SD and algo */
    ICP_QAT_HW_COMP_51_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_OVERRIDE_HASH_PARAMS =
        0x1,
    /* 1 - HW will use the override values provided in cfg register */
} icp_qat_hw_comp_51_skip_hash_override_internal_only_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_DEFAULT_VAL \
    ICP_QAT_HW_COMP_51_SKIP_HASH_OVERRIDE_INTERNAL_ONLY_DETERMINE_HASH_PARAMS

/*****************************************************************************/
/* History Buffer Size, located in lower 32 bit
 */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_HBS_BITPOS 14
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_HBS_MASK 0x7
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible HBS field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_HBS_32KB = 0x0,
    /* 000b - 32KB (DEFLATE) */
    ICP_QAT_HW_COMP_51_HBS_64KB = 0x1,
    /* 001b - 64KB (LZ4, LZ4s, ZSTD) */
} icp_qat_hw_comp_51_hbs_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_HBS_DEFAULT_VAL                          \
    ICP_QAT_HW_COMP_51_HBS_32KB

/*****************************************************************************/
/* Adaptive Block Drop Disable, located in lower 32 bit
 */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ABD_BITPOS 13
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ABD_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible ABD field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_ABD_ABD_ENABLED = 0x0,
    /* 0b - Feature enabled.  */
    ICP_QAT_HW_COMP_51_ABD_ABD_DISABLED = 0x1,
    /* 1b - Feature disabled. */
} icp_qat_hw_comp_51_abd_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_ABD_DEFAULT_VAL                          \
    ICP_QAT_HW_COMP_51_ABD_ABD_ENABLED

/*****************************************************************************/
/* Literal+Length Limit Block Drop Disable , located in lower 32 bit */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LLLBD_CTRL_BITPOS 12
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LLLBD_CTRL_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible LLLBD_CTRL field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_LLLBD_CTRL_LLLBD_ENABLED = 0x0,
    /* 0b - Feature enabled.  */
    ICP_QAT_HW_COMP_51_LLLBD_CTRL_LLLBD_DISABLED = 0x1,
    /* 1b - Feature disabled. */
} icp_qat_hw_comp_51_lllbd_ctrl_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LLLBD_CTRL_DEFAULT_VAL                   \
    ICP_QAT_HW_COMP_51_LLLBD_CTRL_LLLBD_ENABLED

/*****************************************************************************/
/* Search Depth (SD), located in lower 32 bit */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SEARCH_DEPTH_BITPOS 8
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SEARCH_DEPTH_MASK 0xf
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible SEARCH_DEPTH field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_SEARCH_DEPTH_LEVEL_1 = 0x1,
    /* 0001b - Level 1 (search depth = 2^1 = 2) */
    ICP_QAT_HW_COMP_51_SEARCH_DEPTH_LEVEL_6 = 0x3,
    /* 0011b - Level 6 (search depth = 2^3 = 8) */
    ICP_QAT_HW_COMP_51_SEARCH_DEPTH_LEVEL_9 = 0x4,
    /* 0100b - Level 9, non-deflate algos (search depth = 2^4 = 16) */
    ICP_QAT_HW_COMP_51_SEARCH_DEPTH_LEVEL_10 = 0x4,
    /* 0100b - Level 10, deflate only (search depth = 2^4 = 16) */
} icp_qat_hw_comp_51_search_depth_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SEARCH_DEPTH_DEFAULT_VAL                 \
    ICP_QAT_HW_COMP_51_SEARCH_DEPTH_LEVEL_1

/*****************************************************************************/
/* Compression Format (Also See CMD ID), located in lower 32 bit */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_FORMAT_BITPOS 5
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_FORMAT_MASK 0x7
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible FORMAT field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_FORMAT_ILZ77 = 0x1,
    /* iLZ77 (Deflate) */
    ICP_QAT_HW_COMP_51_FORMAT_LZ4 = 0x2,
    /* LZ4 */
    ICP_QAT_HW_COMP_51_FORMAT_LZ4s = 0x3,
    /* LZ4s */
    ICP_QAT_HW_COMP_51_FORMAT_ZSTD = 0x4,
    /* ZSTD */
} icp_qat_hw_comp_51_format_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_FORMAT_DEFAULT_VAL                       \
    ICP_QAT_HW_COMP_51_FORMAT_ILZ77

/*****************************************************************************/
/* Min Match, located in lower 32 bit */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS 4
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MIN_MATCH_CONTROL_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible MIN_MATCH_CONTROL field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_MIN_MATCH_CONTROL_MATCH_3B = 0x0,
    /* 0 - Match 3 B */
    ICP_QAT_HW_COMP_51_MIN_MATCH_CONTROL_MATCH_4B = 0x1,
    /* 1 - Match 4 B */
} icp_qat_hw_comp_51_min_match_control_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_MIN_MATCH_CONTROL_DEFAULT_VAL            \
    ICP_QAT_HW_COMP_51_MIN_MATCH_CONTROL_MATCH_3B

/*****************************************************************************/
/* Skip Hash Collision, located in lower 32 bit */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_COLLISION_BITPOS 3
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_COLLISION_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible SKIP_HASH_COLLISION field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_SKIP_HASH_COLLISION_ALLOW = 0x0,
    /* When set to 0, hash collisions are allowed.  */
    ICP_QAT_HW_COMP_51_SKIP_HASH_COLLISION_DONT_ALLOW = 0x1,
    /* When set to 0, hash collisions are allowed.  */
} icp_qat_hw_comp_51_skip_hash_collision_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_COLLISION_DEFAULT_VAL          \
    ICP_QAT_HW_COMP_51_SKIP_HASH_COLLISION_ALLOW

/*****************************************************************************/
/* Skip Hash Update, located in lower 32 bit */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_UPDATE_BITPOS 2
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_UPDATE_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible SKIP_HASH_UPDATE field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_SKIP_HASH_UPDATE_ALLOW = 0x0,
    /* 0 - hash updates are not skipped.  */
    ICP_QAT_HW_COMP_51_SKIP_HASH_UPDATE_DONT_ALLOW = 0x1,
    /* 1 - hash updates are skipped.  */
} icp_qat_hw_comp_51_skip_hash_update_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_SKIP_HASH_UPDATE_DEFAULT_VAL             \
    ICP_QAT_HW_COMP_51_SKIP_HASH_UPDATE_ALLOW

/*****************************************************************************/
/* 3-Byte Match Skip, located in lower 32 bit */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYTE_SKIP_BITPOS 1
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYTE_SKIP_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible BYTE_SKIP field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_BYTE_SKIP_3BYTE_TOKEN = 0x0,
    /* 0 - Use 3-byte token  */
    ICP_QAT_HW_COMP_51_BYTE_SKIP_3BYTE_LITERAL = 0x1,
    /* 0 - Use 3-byte literal  */
} icp_qat_hw_comp_51_byte_skip_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_BYTE_SKIP_DEFAULT_VAL                    \
    ICP_QAT_HW_COMP_51_BYTE_SKIP_3BYTE_TOKEN

/*****************************************************************************/
/* LZ4 Block Checksum Present, located in lower 32 bit */
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_BITPOS 0
#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible LZ4_BLOCK_CHECKSUM field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_COMP_51_LZ4_BLOCK_CHECKSUM_ABSENT = 0x0,
    /* the LZ4 Block does not contain the 4-byte checksum  */
    ICP_QAT_HW_COMP_51_LZ4_BLOCK_CHECKSUM_PRESENT = 0x1,
    /* LZ4 Block contains a 4-byte checksum.  */
} icp_qat_hw_comp_51_lz4_block_checksum_t;

#define ICP_QAT_HW_COMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_DEFAULT_VAL           \
    ICP_QAT_HW_COMP_51_LZ4_BLOCK_CHECKSUM_ABSENT

/*****************************************************************************/
/* Discard Decompression Output Data, located in upper 32 bit */
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_DISCARD_DATA_BITPOS 26
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_DISCARD_DATA_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible DISCARD_DATA field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_DECOMP_51_DISCARD_DATA_DISABLED = 0x0,
    /* 0 - Decompression produces output data i.e cleartext */
    ICP_QAT_HW_DECOMP_51_DISCARD_DATA_ENABLED = 0x1,
    /* 0 - Decompression does not produce output data */
} icp_qat_hw_decomp_51_discard_data_t;

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_DISCARD_DATA_DEFAULT_VAL               \
    ICP_QAT_HW_DECOMP_51_DISCARD_DATA_DISABLED

/*****************************************************************************/
/* Block Maximum Size (BMS), located in upper 32 bit */
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_BMS_BITPOS 19
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_BMS_MASK 0x3
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible BMS field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_DECOMP_51_BMS_BMS_64KB = 0x0,
    /* Block Max Size (BMS) == 64 KB - LZ4, ZSTD, ILZ77, LZ4s=don't care */
    ICP_QAT_HW_DECOMP_51_BMS_BMS_256KB = 0x1,
    /* Block Max Size (BMS) == 256 KB - LZ4 only */
    ICP_QAT_HW_DECOMP_51_BMS_BMS_1MB = 0x2,
    /* Block Max Size (BMS) == 1 MB - LZ4 only */
    ICP_QAT_HW_DECOMP_51_BMS_BMS_4MB = 0x3,
    /* Block Max Size (BMS) == 4 MB - LZ4 only */
} icp_qat_hw_decomp_51_bms_t;

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_BMS_DEFAULT_VAL                        \
    ICP_QAT_HW_DECOMP_51_BMS_BMS_64KB

/*****************************************************************************/
/* ZSTD Frame Gen/Decode Enable, located in upper 32 bit */
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_BITPOS 2
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible ZSTD_FRAME_GEN_DEC_EN field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_DECOMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_DISABLE = 0x0,
    /* ZSTD Frame header and content checksum generation/decode disabled */
    ICP_QAT_HW_DECOMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_ENABLE = 0x1,
    /* ZSTD Frame header and content checksum generation/decode enabled */
} icp_qat_hw_decomp_51_zstd_frame_gen_dec_en_t;

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_ZSTD_FRAME_GEN_DEC_EN_DEFAULT_VAL      \
    ICP_QAT_HW_DECOMP_51_ZSTD_FRAME_GEN_DEC_EN_ZSTD_FRAME_HDR_ENABLE

/*****************************************************************************/
/* CHKN_BIT: Speculative Decoder Disable (INTERNAL_ONLY), located in lower 32
 * bit
 */
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_BITPOS 21
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible SPEC_DECODER_INTERNAL_ONLY field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_DECOMP_51_SPEC_DECODER_INTERNAL_ONLY_NORMAL = 0x0,
    /* 0 - Normal Mode using Speculative Decoder */
    ICP_QAT_HW_DECOMP_51_SPEC_DECODER_INTERNAL_ONLY_DISABLED = 0x1,
    /* 1 - Speculative Decoder disabled */
} icp_qat_hw_decomp_51_spec_decoder_internal_only_t;

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_SPEC_DECODER_INTERNAL_ONLY_DEFAULT_VAL \
    ICP_QAT_HW_DECOMP_51_SPEC_DECODER_INTERNAL_ONLY_NORMAL

/*****************************************************************************/
/* CHKN_BIT: Mini XCAM Disable (INTERNAL_ONLY), located in lower 32 bit */
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_BITPOS 20
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible MINI_XCAM_INTERNAL_ONLY field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_DECOMP_51_MINI_XCAM_INTERNAL_ONLY_NORMAL = 0x0,
    /* 0 - Normal Mode using Speculative Decoder */
    ICP_QAT_HW_DECOMP_51_MINI_XCAM_INTERNAL_ONLY_DISABLED = 0x1,
    /* 1 - Speculative Decoder disabled */
} icp_qat_hw_decomp_51_mini_xcam_internal_only_t;

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_MINI_XCAM_INTERNAL_ONLY_DEFAULT_VAL    \
    ICP_QAT_HW_DECOMP_51_MINI_XCAM_INTERNAL_ONLY_NORMAL

/*****************************************************************************/
/* History Buffer Size, located in lower 32 bit
 */
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_HBS_BITPOS 14
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_HBS_MASK 0x7
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible HBS field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_DECOMP_51_HBS_32KB = 0x0,
    /* 000b - 32KB (DEFLATE) */
    ICP_QAT_HW_DECOMP_51_HBS_64KB = 0x1,
    /* 001b - 64KB (LZ4, LZ4s, ZSTD) */
} icp_qat_hw_decomp_51_hbs_t;

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_HBS_DEFAULT_VAL                        \
    ICP_QAT_HW_DECOMP_51_HBS_32KB

/*****************************************************************************/
/* Compression Format (Also See CMD ID), located in lower 32 bit */
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_FORMAT_BITPOS 5
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_FORMAT_MASK 0x7
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible FORMAT field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_DECOMP_51_FORMAT_ILZ77 = 0x1,
    /* iLZ77 (Deflate) */
    ICP_QAT_HW_DECOMP_51_FORMAT_LZ4 = 0x2,
    /* LZ4 */
    ICP_QAT_HW_DECOMP_51_FORMAT_RESERVED = 0x3,
    /* reserved */
    ICP_QAT_HW_DECOMP_51_FORMAT_ZSTD = 0x4,
    /* ZSTD */
} icp_qat_hw_decomp_51_format_t;

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_FORMAT_DEFAULT_VAL                     \
    ICP_QAT_HW_DECOMP_51_FORMAT_ILZ77

/*****************************************************************************/
/* LZ4 Block Checksum Present, located in lower 32 bit */
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_BITPOS 0
#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_MASK 0x1
/*
 ****************************************************************************
 * @ingroup icp_qat_hw_defs
 * @description
 *      Enumeration of possible LZ4_BLOCK_CHECKSUM field values
 *****************************************************************************/
typedef enum
{
    ICP_QAT_HW_DECOMP_51_LZ4_BLOCK_CHECKSUM_ABSENT = 0x0,
    /* the LZ4 Block does not contain the 4-byte checksum  */
    ICP_QAT_HW_DECOMP_51_LZ4_BLOCK_CHECKSUM_PRESENT = 0x1,
    /* LZ4 Block contains a 4-byte checksum.  */
} icp_qat_hw_decomp_51_lz4_block_checksum_t;

#define ICP_QAT_HW_DECOMP_51_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_DEFAULT_VAL         \
    ICP_QAT_HW_DECOMP_51_LZ4_BLOCK_CHECKSUM_ABSENT

#endif /* _ICP_QAT_HW_51_COMP_DEFS_H */
