# =======================================================================================
#
#      Filename:  perfmon_cascadelakeX_events.txt
#
#      Description:  Event list for Intel CascadeLake X
#
#      Version:   4.3.3
#      Released:  09.11.2018
#
#      Author:   Jan Treibig (jt), jan.treibig@gmail.com
#                Thomas Gruber (tr), thomas.roehl@googlemail.com
#      Project:  likwid
#
#      Copyright (C) 2018 RRZE, University Erlangen-Nuremberg
#
#      This program is free software: you can redistribute it and/or modify it under
#      the terms of the GNU General Public License as published by the Free Software
#      Foundation, either version 3 of the License, or (at your option) any later
#      version.
#
#      This program is distributed in the hope that it will be useful, but WITHOUT ANY
#      WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
#      PARTICULAR PURPOSE.  See the GNU General Public License for more details.
#
#      You should have received a copy of the GNU General Public License along with
#      this program.  If not, see <http://www.gnu.org/licenses/>.
#
# =======================================================================================

EVENT_TEMP_CORE          0x00   TMP0
UMASK_TEMP_CORE          0x00

EVENT_PWR_PKG_ENERGY          0x02   PWR0
UMASK_PWR_PKG_ENERGY          0x00

EVENT_PWR_PP0_ENERGY          0x01   PWR1
UMASK_PWR_PP0_ENERGY          0x00

EVENT_PWR_PP1_ENERGY          0x04   PWR2
UMASK_PWR_PP1_ENERGY          0x00

EVENT_PWR_DRAM_ENERGY          0x03   PWR3
UMASK_PWR_DRAM_ENERGY          0x00

EVENT_PWR_PLATFORM_ENERGY          0x05   PWR4
UMASK_PWR_PLATFORM_ENERGY          0x00

EVENT_VOLTAGE_CORE          0x00   VTG0
UMASK_VOLTAGE_CORE          0x00

EVENT_INSTR_RETIRED              0x00   FIXC0
UMASK_INSTR_RETIRED_ANY          0x00

EVENT_CPU_CLK_UNHALTED           0x00   FIXC1
UMASK_CPU_CLK_UNHALTED_CORE      0x00

EVENT_CPU_CLK_UNHALTED           0x00   FIXC2
UMASK_CPU_CLK_UNHALTED_REF       0x00

EVENT_ICACHE_16B_IFDATA_STALL    0x80 PMC
UMASK_ICACHE_16B_IFDATA_STALL    0x04

EVENT_ICACHE_64B_IFTAG           0x83 PMC
UMASK_ICACHE_64B_IFTAG_HIT       0x01
UMASK_ICACHE_64B_IFTAG_MISS      0x02
UMASK_ICACHE_64B_IFTAG_ALL       0x03
UMASK_ICACHE_64B_IFTAG_STALL     0x04

EVENT_CPU_CLOCK_UNHALTED         0x3C   PMC
UMASK_CPU_CLOCK_UNHALTED_THREAD_P  0x00
DEFAULT_OPTIONS_CPU_CLOCK_UNHALTED_THREAD_P_ANY EVENT_OPTION_ANYTHREAD=1
UMASK_CPU_CLOCK_UNHALTED_THREAD_P_ANY  0x00
UMASK_CPU_CLOCK_UNHALTED_REF_XCLK     0x01
DEFAULT_OPTIONS_CPU_CLOCK_UNHALTED_REF_XCLK_ANY EVENT_OPTION_ANYTHREAD=1
UMASK_CPU_CLOCK_UNHALTED_REF_XCLK_ANY     0x01
UMASK_CPU_CLOCK_UNHALTED_ONE_THREAD_ACTIVE 0x02
DEFAULT_OPTIONS_CPU_CLOCK_UNHALTED_TOTAL_CYCLES EVENT_OPTION_THRESHOLD=0x2,EVENT_OPTION_INVERT=0x1
UMASK_CPU_CLOCK_UNHALTED_TOTAL_CYCLES   0x00

EVENT_BACLEARS                      0xE6 PMC
UMASK_BACLEARS_ANY                  0x01

EVENT_ITLB_FLUSH                    0xAE PMC
UMASK_ITLB_FLUSH                    0x01

EVENT_ILD_STALL_LCP                 0x87 PMC
UMASK_ILD_STALL_LCP                 0x01

EVENT_IDQ_UOPS_NOT_DELIVERED            0x9C PMC
UMASK_IDQ_UOPS_NOT_DELIVERED_CORE       0x01
DEFAULT_OPTIONS_IDQ_UOPS_NOT_DELIVERED_CYCLES_0_UOPS_DELIV_CORE EVENT_OPTION_THRESHOLD=0x4
UMASK_IDQ_UOPS_NOT_DELIVERED_CYCLES_0_UOPS_DELIV_CORE 0x01
DEFAULT_OPTIONS_IDQ_UOPS_NOT_DELIVERED_CYCLES_LE_1_UOP_DELIV_CORE EVENT_OPTION_THRESHOLD=0x3
UMASK_IDQ_UOPS_NOT_DELIVERED_CYCLES_LE_1_UOP_DELIV_CORE 0x01
DEFAULT_OPTIONS_IDQ_UOPS_NOT_DELIVERED_CYCLES_LE_2_UOP_DELIV_CORE EVENT_OPTION_THRESHOLD=0x2
UMASK_IDQ_UOPS_NOT_DELIVERED_CYCLES_LE_2_UOP_DELIV_CORE 0x01
DEFAULT_OPTIONS_IDQ_UOPS_NOT_DELIVERED_CYCLES_LE_3_UOP_DELIV_CORE EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_UOPS_NOT_DELIVERED_CYCLES_LE_3_UOP_DELIV_CORE 0x01
DEFAULT_OPTIONS_IDQ_UOPS_NOT_DELIVERED_CYCLES_FE_WAS_OK EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=0x1
UMASK_IDQ_UOPS_NOT_DELIVERED_CYCLES_FE_WAS_OK 0x01

EVENT_DSB2MITE_SWITCHES_PENALTY_CYCLES 0xAB PMC
UMASK_DSB2MITE_SWITCHES_PENALTY_CYCLES 0x02

EVENT_INT_MISC                          0x0D PMC
UMASK_INT_MISC_RECOVERY_CYCLES          0x01
DEFAULT_OPTIONS_INT_MISC_RECOVERY_COUNT EVENT_OPTION_EDGE=1
UMASK_INT_MISC_RECOVERY_COUNT           0x01
DEFAULT_OPTIONS_INT_MISC_RECOVERY_CYCLES_ANY EVENT_OPTION_ANYTHREAD=0x1
UMASK_INT_MISC_RECOVERY_CYCLES_ANY      0x01
DEFAULT_OPTIONS_INT_MISC_RECOVERY_COUNT_ANY EVENT_OPTION_ANYTHREAD=0x1,EVENT_OPTION_EDGE=1
UMASK_INT_MISC_RECOVERY_COUNT_ANY       0x01
UMASK_INT_MISC_CLEAR_RESTEER_CYCLES     0x80
DEFAULT_OPTIONS_INT_MISC_CLEAR_RESTEER_COUNT EVENT_OPTION_EDGE=1
UMASK_INT_MISC_CLEAR_RESTEER_COUNT      0x80


EVENT_RESOURCE_STALLS                   0xA2 PMC
UMASK_RESOURCE_STALLS_ANY               0x01
UMASK_RESOURCE_STALLS_SB                0x08

EVENT_PARTIAL_RAT_STALLS_SCOREBOARD     0x59 PMC
UMASK_PARTIAL_RAT_STALLS_SCOREBOARD     0x01

EVENT_UOPS_ISSUED                0x0E  PMC
UMASK_UOPS_ISSUED_ANY            0x01
UMASK_UOPS_ISSUED_VECTOR_WIDTH_MISMATCH 0x02
UMASK_UOPS_ISSUED_SLOW_LEA       0x20
DEFAULT_OPTIONS_UOPS_ISSUED_USED_CYCLES EVENT_OPTION_THRESHOLD=0x1
UMASK_UOPS_ISSUED_USED_CYCLES   0x01
DEFAULT_OPTIONS_UOPS_ISSUED_STALL_CYCLES EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=1
UMASK_UOPS_ISSUED_STALL_CYCLES   0x01
DEFAULT_OPTIONS_UOPS_ISSUED_TOTAL_CYCLES EVENT_OPTION_THRESHOLD=0xA,EVENT_OPTION_INVERT=1
UMASK_UOPS_ISSUED_TOTAL_CYCLES   0x01
DEFAULT_OPTIONS_UOPS_ISSUED_CORE_USED_CYCLES EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_ANYTHREAD=1
UMASK_UOPS_ISSUED_CORE_USED_CYCLES   0x01
DEFAULT_OPTIONS_UOPS_ISSUED_CORE_STALL_CYCLES EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=1,EVENT_OPTION_ANYTHREAD=1
UMASK_UOPS_ISSUED_CORE_STALL_CYCLES   0x01
DEFAULT_OPTIONS_UOPS_ISSUED_CORE_TOTAL_CYCLES EVENT_OPTION_THRESHOLD=0xA,EVENT_OPTION_INVERT=1,EVENT_OPTION_ANYTHREAD=1
UMASK_UOPS_ISSUED_CORE_TOTAL_CYCLES   0x01
DEFAULT_OPTIONS_UOPS_ISSUED_CYCLES_GE_1_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x1
UMASK_UOPS_ISSUED_CYCLES_GE_1_UOPS_EXEC 0x01
DEFAULT_OPTIONS_UOPS_ISSUED_CYCLES_GE_2_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x2
UMASK_UOPS_ISSUED_CYCLES_GE_2_UOPS_EXEC 0x01
DEFAULT_OPTIONS_UOPS_ISSUED_CYCLES_GE_3_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x3
UMASK_UOPS_ISSUED_CYCLES_GE_3_UOPS_EXEC 0x01
DEFAULT_OPTIONS_UOPS_ISSUED_CYCLES_GE_4_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x4
UMASK_UOPS_ISSUED_CYCLES_GE_4_UOPS_EXEC 0x01
DEFAULT_OPTIONS_UOPS_ISSUED_CYCLES_GE_5_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x5
UMASK_UOPS_ISSUED_CYCLES_GE_5_UOPS_EXEC 0x01



EVENT_TX_EXEC                           0x5D PMC
UMASK_TX_EXEC_MISC1                     0x01
UMASK_TX_EXEC_MISC2                     0x02
UMASK_TX_EXEC_MISC3                     0x04
UMASK_TX_EXEC_MISC4                     0x08
UMASK_TX_EXEC_MISC5                     0x10

EVENT_RS_EVENTS_EMPTY                   0x5E PMC
UMASK_RS_EVENTS_EMPTY_CYCLES            0x01
DEFAULT_OPTIONS_RS_EVENTS_EMPTY_END     EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=0x1,EVENT_OPTION_EDGE=0x1
UMASK_RS_EVENTS_EMPTY_END               0x01

EVENT_HLE_RETIRED                       0xC8 PMC
UMASK_HLE_RETIRED_START                 0x01
UMASK_HLE_RETIRED_COMMIT                0x02
UMASK_HLE_RETIRED_ABORTED               0x04
UMASK_HLE_RETIRED_ABORTED_MEM           0x08
UMASK_HLE_RETIRED_ABORTED_TIMER         0x10
UMASK_HLE_RETIRED_ABORTED_UNFRIENDLY    0x20
UMASK_HLE_RETIRED_ABORTED_MEMTYPE       0x40
UMASK_HLE_RETIRED_ABORTED_EVENTS        0x80

EVENT_RTM_RETIRED                       0xC9 PMC
UMASK_RTM_RETIRED_START                 0x01
UMASK_RTM_RETIRED_COMMIT                0x02
UMASK_RTM_RETIRED_ABORTED               0x04
UMASK_RTM_RETIRED_ABORTED_MEM           0x08
UMASK_RTM_RETIRED_ABORTED_TIMER         0x10
UMASK_RTM_RETIRED_ABORTED_UNFRIENDLY    0x20
UMASK_RTM_RETIRED_ABORTED_MEMTYPE       0x40
UMASK_RTM_RETIRED_ABORTED_EVENTS        0x80

EVENT_MACHINE_CLEARS                    0xC3 PMC
DEFAULT_OPTIONS_MACHINE_CLEARS_COUNT    EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_EDGE=0x1
UMASK_MACHINE_CLEARS_COUNT              0x01
UMASK_MACHINE_CLEARS_MEMORY_ORDERING    0x02
UMASK_MACHINE_CLEARS_SMC                0x04

EVENT_HW_INTERRUPTS_RECEIVED            0xCB PMC
UMASK_HW_INTERRUPTS_RECEIVED            0x01

EVENT_INST_RETIRED                      0xC0 PMC
UMASK_INST_RETIRED_ANY                  0x00

EVENT_UOPS_RETIRED                       0xC2  PMC
UMASK_UOPS_RETIRED_ALL                   0x01
DEFAULT_OPTIONS_UOPS_RETIRED_CORE_ALL EVENT_OPTION_ANYTHREAD=1
UMASK_UOPS_RETIRED_CORE_ALL              0x01
UMASK_UOPS_RETIRED_RETIRE_SLOTS          0x02
DEFAULT_OPTIONS_UOPS_RETIRED_CORE_RETIRE_SLOTS EVENT_OPTION_ANYTHREAD=1
UMASK_UOPS_RETIRED_CORE_RETIRE_SLOTS     0x02
DEFAULT_OPTIONS_UOPS_RETIRED_USED_CYCLES EVENT_OPTION_THRESHOLD=0x1
UMASK_UOPS_RETIRED_USED_CYCLES           0x01
DEFAULT_OPTIONS_UOPS_RETIRED_STALL_CYCLES EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=1
UMASK_UOPS_RETIRED_STALL_CYCLES          0x01
DEFAULT_OPTIONS_UOPS_RETIRED_TOTAL_CYCLES EVENT_OPTION_THRESHOLD=0xA,EVENT_OPTION_INVERT=1
UMASK_UOPS_RETIRED_TOTAL_CYCLES          0x01
DEFAULT_OPTIONS_UOPS_RETIRED_CORE_USED_CYCLES EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_ANYTHREAD=1
UMASK_UOPS_RETIRED_CORE_USED_CYCLES      0x01
DEFAULT_OPTIONS_UOPS_RETIRED_CORE_STALL_CYCLES EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=1,EVENT_OPTION_ANYTHREAD=1
UMASK_UOPS_RETIRED_CORE_STALL_CYCLES     0x01
DEFAULT_OPTIONS_UOPS_RETIRED_CORE_TOTAL_CYCLES EVENT_OPTION_THRESHOLD=0xA,EVENT_OPTION_INVERT=1,EVENT_OPTION_ANYTHREAD=1
UMASK_UOPS_RETIRED_CORE_TOTAL_CYCLES     0x01
DEFAULT_OPTIONS_UOPS_RETIRED_CYCLES_GE_1_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x1
UMASK_UOPS_RETIRED_CYCLES_GE_1_UOPS_EXEC 0x01
DEFAULT_OPTIONS_UOPS_RETIRED_CYCLES_GE_2_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x2
UMASK_UOPS_RETIRED_CYCLES_GE_2_UOPS_EXEC 0x01
DEFAULT_OPTIONS_UOPS_RETIRED_CYCLES_GE_3_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x3
UMASK_UOPS_RETIRED_CYCLES_GE_3_UOPS_EXEC 0x01
DEFAULT_OPTIONS_UOPS_RETIRED_CYCLES_GE_4_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x4
UMASK_UOPS_RETIRED_CYCLES_GE_4_UOPS_EXEC 0x01
DEFAULT_OPTIONS_UOPS_RETIRED_CYCLES_GE_5_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x5
UMASK_UOPS_RETIRED_CYCLES_GE_5_UOPS_EXEC 0x01
DEFAULT_OPTIONS_UOPS_RETIRED_CYCLES_GE_6_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x6
UMASK_UOPS_RETIRED_CYCLES_GE_6_UOPS_EXEC 0x01
DEFAULT_OPTIONS_UOPS_RETIRED_CYCLES_GE_7_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x7
UMASK_UOPS_RETIRED_CYCLES_GE_7_UOPS_EXEC 0x01
DEFAULT_OPTIONS_UOPS_RETIRED_CYCLES_GE_8_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x8
UMASK_UOPS_RETIRED_CYCLES_GE_8_UOPS_EXEC 0x01

EVENT_BR_INST_RETIRED                   0xC4 PMC
UMASK_BR_INST_RETIRED_ALL_BRANCHES      0x00
UMASK_BR_INST_RETIRED_CONDITIONAL       0x01
UMASK_BR_INST_RETIRED_NEAR_CALL         0x02
UMASK_BR_INST_RETIRED_NEAR_RETURN       0x08
UMASK_BR_INST_RETIRED_NOT_TAKEN         0x10
UMASK_BR_INST_RETIRED_NEAR_TAKEN        0x20
UMASK_BR_INST_RETIRED_FAR_BRANCH        0x40

EVENT_BR_MISP_RETIRED                   0xC5 PMC
UMASK_BR_MISP_RETIRED_ALL_BRANCHES      0x00
UMASK_BR_MISP_RETIRED_CONDITIONAL       0x01
UMASK_BR_MISP_RETIRED_NEAR_TAKEN        0x20

EVENT_FP_ARITH_INST_RETIRED                     0xC7 PMC
UMASK_FP_ARITH_INST_RETIRED_SCALAR_DOUBLE       0x01
UMASK_FP_ARITH_INST_RETIRED_SCALAR_SINGLE       0x02
UMASK_FP_ARITH_INST_RETIRED_128B_PACKED_DOUBLE  0x04
UMASK_FP_ARITH_INST_RETIRED_128B_PACKED_SINGLE  0x08
UMASK_FP_ARITH_INST_RETIRED_256B_PACKED_DOUBLE  0x10
UMASK_FP_ARITH_INST_RETIRED_256B_PACKED_SINGLE  0x20
UMASK_FP_ARITH_INST_RETIRED_512B_PACKED_DOUBLE  0x40
UMASK_FP_ARITH_INST_RETIRED_512B_PACKED_SINGLE  0x80
UMASK_FP_ARITH_INST_RETIRED_DOUBLE              0x55
UMASK_FP_ARITH_INST_RETIRED_SINGLE              0xAA

EVENT_FP_ASSIST_ANY                     0xCA PMC
DEFAULT_OPTIONS_FP_ASSIST_ANY           EVENT_OPTION_THRESHOLD=0x1
UMASK_FP_ASSIST_ANY                     0x1E

EVENT_MEM_INST_RETIRED                  0xD0 PMC
UMASK_MEM_INST_RETIRED_STLB_MISS_LOADS  0x11
UMASK_MEM_INST_RETIRED_STLB_MISS_STORES 0x12
UMASK_MEM_INST_RETIRED_LOCK_LOADS       0x21
UMASK_MEM_INST_RETIRED_SPLIT_LOADS      0x41
UMASK_MEM_INST_RETIRED_SPLIT_STORES     0x42
UMASK_MEM_INST_RETIRED_ALL_LOADS        0x81
UMASK_MEM_INST_RETIRED_ALL_STORES       0x82
UMASK_MEM_INST_RETIRED_ALL              0x83

EVENT_MEM_LOAD_RETIRED                  0xD1 PMC
UMASK_MEM_LOAD_RETIRED_L1_HIT           0x01
UMASK_MEM_LOAD_RETIRED_L2_HIT           0x02
UMASK_MEM_LOAD_RETIRED_L3_HIT           0x04
UMASK_MEM_LOAD_RETIRED_L1_MISS          0x08
UMASK_MEM_LOAD_RETIRED_L2_MISS          0x10
UMASK_MEM_LOAD_RETIRED_L3_MISS          0x20
UMASK_MEM_LOAD_RETIRED_FB_HIT           0x40
UMASK_MEM_LOAD_RETIRED_L1_ALL           0x09
UMASK_MEM_LOAD_RETIRED_L2_ALL           0x12
UMASK_MEM_LOAD_RETIRED_L3_ALL           0x24
UMASK_MEM_LOAD_RETIRED_LOCAL_PMM        0x80

EVENT_MEM_LOAD_L3_HIT_RETIRED           0xD2 PMC
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_MISS 0x01
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_HIT  0x02
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_HITM 0x04
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_NONE 0x08
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_ALL  0x0F

EVENT_MEM_LOAD_L3_MISS_RETIRED              0xD3 PMC
UMASK_MEM_LOAD_L3_MISS_RETIRED_LOCAL_DRAM   0x01
UMASK_MEM_LOAD_L3_MISS_RETIRED_REMOTE_DRAM  0x02
UMASK_MEM_LOAD_L3_MISS_RETIRED_REMOTE_HITM  0x04
UMASK_MEM_LOAD_L3_MISS_RETIRED_REMOTE_FWD   0x08
UMASK_MEM_LOAD_L3_MISS_RETIRED_REMOTE_ALL   0x0E
UMASK_MEM_LOAD_L3_MISS_RETIRED_REMOTE_PMM 0x10

EVENT_MEM_LOAD_MISC_RETIRED             0xD4 PMC
UMASK_MEM_LOAD_MISC_RETIRED_UC          0x04

EVENT_MEM_TRANS_RETIRED                     0xCD PMC
UMASK_MEM_TRANS_RETIRED_LOAD_LATENCY_GT_4   0x01 0x0 0x04
UMASK_MEM_TRANS_RETIRED_LOAD_LATENCY_GT_8   0x01 0x0 0x08
UMASK_MEM_TRANS_RETIRED_LOAD_LATENCY_GT_16  0x01 0x0 0x10
UMASK_MEM_TRANS_RETIRED_LOAD_LATENCY_GT_32  0x01 0x0 0x20
UMASK_MEM_TRANS_RETIRED_LOAD_LATENCY_GT_64  0x01 0x0 0x40
UMASK_MEM_TRANS_RETIRED_LOAD_LATENCY_GT_128 0x01 0x0 0x80
UMASK_MEM_TRANS_RETIRED_LOAD_LATENCY_GT_256 0x01 0x0 0x100
UMASK_MEM_TRANS_RETIRED_LOAD_LATENCY_GT_512 0x01 0x0 0x200

EVENT_FRONTEND_RETIRED                  0xC6 PMC
UMASK_FRONTEND_RETIRED_DSB_MISS         0x01 0x00 0x11
UMASK_FRONTEND_RETIRED_L1I_MISS         0x01 0x00 0x12
UMASK_FRONTEND_RETIRED_L2_MISS          0x01 0x00 0x13
UMASK_FRONTEND_RETIRED_ITLB_MISS        0x01 0x00 0x14
UMASK_FRONTEND_RETIRED_STLB_MISS        0x01 0x00 0x15
UMASK_FRONTEND_RETIRED_LATENCY_GE_2     0x01 0x00 0x400206
UMASK_FRONTEND_RETIRED_LATENCY_GE_2_BUBBLES_GE_2 0x01 0x00 0x200206
UMASK_FRONTEND_RETIRED_LATENCY_GE_4     0x01 0x00 0x400406


EVENT_UOPS_EXECUTED                       0xB1   PMC
UMASK_UOPS_EXECUTED_THREAD                0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_USED_CYCLES EVENT_OPTION_THRESHOLD=0x1
UMASK_UOPS_EXECUTED_USED_CYCLES           0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_STALL_CYCLES EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=1
UMASK_UOPS_EXECUTED_STALL_CYCLES          0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_TOTAL_CYCLES EVENT_OPTION_THRESHOLD=0xA,EVENT_OPTION_INVERT=1
UMASK_UOPS_EXECUTED_TOTAL_CYCLES          0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_1_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x1
UMASK_UOPS_EXECUTED_CYCLES_GE_1_UOPS_EXEC 0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_2_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x2
UMASK_UOPS_EXECUTED_CYCLES_GE_2_UOPS_EXEC 0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_3_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x3
UMASK_UOPS_EXECUTED_CYCLES_GE_3_UOPS_EXEC 0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_4_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x4
UMASK_UOPS_EXECUTED_CYCLES_GE_4_UOPS_EXEC 0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_5_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x5
UMASK_UOPS_EXECUTED_CYCLES_GE_5_UOPS_EXEC 0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_6_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x6
UMASK_UOPS_EXECUTED_CYCLES_GE_6_UOPS_EXEC 0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_7_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x7
UMASK_UOPS_EXECUTED_CYCLES_GE_7_UOPS_EXEC 0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_8_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x8
UMASK_UOPS_EXECUTED_CYCLES_GE_8_UOPS_EXEC 0x01
UMASK_UOPS_EXECUTED_CORE                  0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_USED_CYCLES EVENT_OPTION_THRESHOLD=0x1
UMASK_UOPS_EXECUTED_CORE_USED_CYCLES           0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_STALL_CYCLES EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=1
UMASK_UOPS_EXECUTED_CORE_STALL_CYCLES          0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_TOTAL_CYCLES EVENT_OPTION_THRESHOLD=0xA,EVENT_OPTION_INVERT=1
UMASK_UOPS_EXECUTED_CORE_TOTAL_CYCLES          0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_1_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x1
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_1_UOPS_EXEC 0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_2_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x2
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_2_UOPS_EXEC 0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_3_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x3
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_3_UOPS_EXEC 0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_4_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x4
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_4_UOPS_EXEC 0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_5_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x5
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_5_UOPS_EXEC 0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_6_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x6
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_6_UOPS_EXEC 0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_7_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x7
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_7_UOPS_EXEC 0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_8_UOPS_EXEC EVENT_OPTION_THRESHOLD=0x8
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_8_UOPS_EXEC 0x02
UMASK_UOPS_EXECUTED_X87                 0x10


EVENT_EXE_ACTIVITY                      0xA6 PMC
UMASK_EXE_ACTIVITY_EXE_BOUND_0_PORTS    0x01
UMASK_EXE_ACTIVITY_1_PORTS_UTIL         0x02
UMASK_EXE_ACTIVITY_2_PORTS_UTIL         0x04
UMASK_EXE_ACTIVITY_3_PORTS_UTIL         0x08
UMASK_EXE_ACTIVITY_4_PORTS_UTIL         0x10
UMASK_EXE_ACTIVITY_BOUND_ON_STORES      0x40

EVENT_UOPS_DISPATCHED_PORT              0xA1 PMC
UMASK_UOPS_DISPATCHED_PORT_PORT_0       0x01
UMASK_UOPS_DISPATCHED_PORT_PORT_1       0x02
UMASK_UOPS_DISPATCHED_PORT_PORT_2       0x04
UMASK_UOPS_DISPATCHED_PORT_PORT_3       0x08
UMASK_UOPS_DISPATCHED_PORT_PORT_4       0x10
UMASK_UOPS_DISPATCHED_PORT_PORT_5       0x20
UMASK_UOPS_DISPATCHED_PORT_PORT_6       0x40
UMASK_UOPS_DISPATCHED_PORT_PORT_7       0x80
UMASK_UOPS_DISPATCHED_PORT_ARITH_PORTS      0x63
DEFAULT_OPTIONS_UOPS_DISPATCHED_PORT_ARITH_PORTS_CORE    EVENT_OPTION_ANYTHREAD=1
UMASK_UOPS_DISPATCHED_PORT_ARITH_PORTS_CORE 0x63
DEFAULT_OPTIONS_UOPS_DISPATCHED_PORT_DATA_PORTS    EVENT_OPTION_ANYTHREAD=1
UMASK_UOPS_DISPATCHED_PORT_DATA_PORTS       0x9C

EVENT_CYCLE_ACTIVITY                    0xA3 PMC
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_TOTAL EVENT_OPTION_THRESHOLD=0x4
UMASK_CYCLE_ACTIVITY_STALLS_TOTAL       0x04
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_NO_EXECUTE EVENT_OPTION_THRESHOLD=0x4
UMASK_CYCLE_ACTIVITY_CYCLES_NO_EXECUTE       0x04
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_L2_MISS EVENT_OPTION_THRESHOLD=0x1
UMASK_CYCLE_ACTIVITY_CYCLES_L2_MISS     0x01
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_L2_MISS EVENT_OPTION_THRESHOLD=0x5
UMASK_CYCLE_ACTIVITY_STALLS_L2_MISS     0x05
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_L2_PENDING EVENT_OPTION_THRESHOLD=0x1
UMASK_CYCLE_ACTIVITY_CYCLES_L2_PENDING     0x01
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_L2_PENDING EVENT_OPTION_THRESHOLD=0x5
UMASK_CYCLE_ACTIVITY_STALLS_L2_PENDING     0x05
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_L3_MISS EVENT_OPTION_THRESHOLD=0x2
UMASK_CYCLE_ACTIVITY_CYCLES_L3_MISS     0x02
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_L3_MISS EVENT_OPTION_THRESHOLD=0x6
UMASK_CYCLE_ACTIVITY_STALLS_L3_MISS     0x06
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_L3_PENDING EVENT_OPTION_THRESHOLD=0x2
UMASK_CYCLE_ACTIVITY_CYCLES_L3_PENDING     0x02
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_L3_PENDING EVENT_OPTION_THRESHOLD=0x6
UMASK_CYCLE_ACTIVITY_STALLS_L3_PENDING     0x06
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_MEM_ANY EVENT_OPTION_THRESHOLD=0x10
UMASK_CYCLE_ACTIVITY_CYCLES_MEM_ANY     0x10
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_MEM_ANY EVENT_OPTION_THRESHOLD=0x14
UMASK_CYCLE_ACTIVITY_STALLS_MEM_ANY     0x14
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_LDM_PENDING EVENT_OPTION_THRESHOLD=0x10
UMASK_CYCLE_ACTIVITY_CYCLES_LDM_PENDING     0x10
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_LDM_PENDING EVENT_OPTION_THRESHOLD=0x14
UMASK_CYCLE_ACTIVITY_STALLS_LDM_PENDING     0x14

EVENT_CYCLE_ACTIVITY_CYCLES_L1D_MISS  0xA3 PMC
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_L1D_MISS EVENT_OPTION_THRESHOLD=0x8
UMASK_CYCLE_ACTIVITY_CYCLES_L1D_MISS    0x08

EVENT_CYCLE_ACTIVITY_STALLS_L1D_MISS  0xA3 PMC
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_L1D_MISS EVENT_OPTION_THRESHOLD=0xC
UMASK_CYCLE_ACTIVITY_STALLS_L1D_MISS    0x0C

EVENT_CYCLE_ACTIVITY_CYCLES_L1D_PENDING 0xA3 PMC
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_L1D_PENDING EVENT_OPTION_THRESHOLD=0x8
UMASK_CYCLE_ACTIVITY_CYCLES_L1D_PENDING    0x08

EVENT_CYCLE_ACTIVITY_STALLS_L1D_PENDING 0xA3 PMC
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_L1D_PENDING EVENT_OPTION_THRESHOLD=0xC
UMASK_CYCLE_ACTIVITY_STALLS_L1D_PENDING    0x0C

EVENT_EPT_WALK_PENDING  0x4F PMC
UMASK_EPT_WALK_PENDING                  0x10

EVENT_ITLB_MISSES                       0x85 PMC
UMASK_ITLB_MISSES_CAUSES_A_WALK         0x01

UMASK_ITLB_MISSES_WALK_PENDING          0x10
UMASK_ITLB_MISSES_STLB_HIT              0x20
UMASK_ITLB_MISSES_WALK_COMPLETED        0x0E
UMASK_ITLB_MISSES_WALK_COMPLETED_4K     0x02
UMASK_ITLB_MISSES_WALK_COMPLETED_2M_4M  0x04
UMASK_ITLB_MISSES_WALK_COMPLETED_1G     0x08
DEFAULT_OPTIONS_ITLB_MISSES_WALK_ACTIVE EVENT_OPTION_THRESHOLD=0x1
UMASK_ITLB_MISSES_WALK_ACTIVE           0x10

EVENT_DTLB_LOAD_MISSES                      0x08 PMC
UMASK_DTLB_LOAD_MISSES_CAUSES_A_WALK        0x01
UMASK_DTLB_LOAD_MISSES_WALK_PENDING         0x10
UMASK_DTLB_LOAD_MISSES_STLB_HIT             0x20
UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED       0x0E
UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED_4K    0x02
UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED_2M_4M 0x04
UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED_1G    0x08
DEFAULT_OPTIONS_DTLB_LOAD_MISSES_WALK_ACTIVE EVENT_OPTION_THRESHOLD=0x1
UMASK_DTLB_LOAD_MISSES_WALK_ACTIVE          0x10

EVENT_DTLB_STORE_MISSES                      0x49 PMC
UMASK_DTLB_STORE_MISSES_CAUSES_A_WALK        0x01
UMASK_DTLB_STORE_MISSES_WALK_PENDING         0x10
UMASK_DTLB_STORE_MISSES_STLB_HIT             0x20
UMASK_DTLB_STORE_MISSES_WALK_COMPLETED       0x0E
UMASK_DTLB_STORE_MISSES_WALK_COMPLETED_4K    0x02
UMASK_DTLB_STORE_MISSES_WALK_COMPLETED_2M_4M 0x04
UMASK_DTLB_STORE_MISSES_WALK_COMPLETED_1G    0x08
DEFAULT_OPTIONS_DTLB_STORE_MISSES_WALK_ACTIVE EVENT_OPTION_THRESHOLD=0x1
UMASK_DTLB_STORE_MISSES_WALK_ACTIVE          0x10

EVENT_TLB_FLUSH                         0xBD PMC
UMASK_TLB_FLUSH_DTLB_THREAD             0x01
UMASK_TLB_FLUSH_STLB_ANY                0x20

EVENT_L1D                               0x51 PMC
UMASK_L1D_REPLACEMENT                   0x01
UMASK_L1D_M_EVICT                       0x04

EVENT_TX_MEM                            0x54 PMC
UMASK_TX_MEM_ABORT_CONFLICT             0x01
UMASK_TX_MEM_ABORT_CAPACITY             0x02
UMASK_TX_MEM_ABORT_HLE_STORE_TO_ELIDED_LOCK 0x04
UMASK_TX_MEM_ABORT_HLE_ELISION_BUFFER_NOT_EMPTY 0x08
UMASK_TX_MEM_ABORT_HLE_ELISION_BUFFER_MISMATCH 0x10
UMASK_TX_MEM_ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT 0x20
UMASK_TX_MEM_HLE_ELISION_BUFFER_FULL    0x40

EVENT_L1D_PEND_MISS                     0x48 PMC
UMASK_L1D_PEND_MISS_PENDING             0x01
UMASK_L1D_PEND_MISS_FB_FULL             0x02
DEFAULT_OPTIONS_L1D_PEND_MISS_PENDING_CYCLES EVENT_OPTION_THRESHOLD=0x1
UMASK_L1D_PEND_MISS_PENDING_CYCLES      0x01
DEFAULT_OPTIONS_L1D_PEND_MISS_PENDING_CYCLES_ANY EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_ANYTHREAD=0x1
UMASK_L1D_PEND_MISS_PENDING_CYCLES_ANY  0x01

EVENT_LOAD_HIT_PRE_SW_PF                0x4C PMC
UMASK_LOAD_HIT_PRE_SW_PF                0x01

EVENT_LOCK_CYCLES_CACHE_LOCK            0x63 PMC
UMASK_LOCK_CYCLES_CACHE_LOCK_DURATION   0x02
DEFAULT_OPTIONS_LOCK_CYCLES_CACHE_LOCK_COUNT EVENT_OPTION_EDGE=1
UMASK_LOCK_CYCLES_CACHE_LOCK_COUNT      0x02

EVENT_LD_BLOCKS                         0x03 PMC
UMASK_LD_BLOCKS_STORE_FORWARD           0x02
UMASK_LD_BLOCKS_NO_SR                   0x08

EVENT_LD_BLOCKS_PARTIAL_ADDRESS_ALIAS   0x07 PMC
UMASK_LD_BLOCKS_PARTIAL_ADDRESS_ALIAS   0x01

EVENT_OFFCORE_REQUESTS                  0xB0 PMC
UMASK_OFFCORE_REQUESTS_DEMAND_DATA_RD   0x01
UMASK_OFFCORE_REQUESTS_DEMAND_CODE_RD   0x02
UMASK_OFFCORE_REQUESTS_DEMAND_RFO       0x04
UMASK_OFFCORE_REQUESTS_ALL_DATA_RD      0x08
UMASK_OFFCORE_REQUESTS_L3_MISS_DEMAND_DATA_RD 0x10
UMASK_OFFCORE_REQUESTS_ALL_REQUESTS     0x80

EVENT_OFFCORE_REQUESTS_OUTSTANDING      0x60 PMC
UMASK_OFFCORE_REQUESTS_OUTSTANDING_DEMAND_DATA_RD 0x01
DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_DEMAND_DATA_RD_GE_6 EVENT_OPTION_THRESHOLD=0x6
UMASK_OFFCORE_REQUESTS_OUTSTANDING_DEMAND_DATA_RD_GE_6 0x01
UMASK_OFFCORE_REQUESTS_OUTSTANDING_DEMAND_CODE_RD 0x02
UMASK_OFFCORE_REQUESTS_OUTSTANDING_DEMAND_RFO 0x04
UMASK_OFFCORE_REQUESTS_OUTSTANDING_ALL_DATA_RD 0x08
UMASK_OFFCORE_REQUESTS_OUTSTANDING_L3_MISS_DEMAND_DATA_RD 0x10
DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_DATA_RD EVENT_OPTION_THRESHOLD=0x1
UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_DATA_RD 0x01
DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DATA_RD EVENT_OPTION_THRESHOLD=0x1
UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DATA_RD 0x08
DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_CODE_RD EVENT_OPTION_THRESHOLD=0x1
UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_CODE_RD 0x02
DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_RFO EVENT_OPTION_THRESHOLD=0x1
UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_RFO 0x04
DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_L3_MISS_DEMAND_DATA_RD EVENT_OPTION_THRESHOLD=0x1
UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_L3_MISS_DEMAND_DATA_RD 0x10
DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_L3_MISS_DEMAND_DATA_RD_GE_6 EVENT_OPTION_THRESHOLD=0x6
UMASK_OFFCORE_REQUESTS_OUTSTANDING_L3_MISS_DEMAND_DATA_RD_GE_6 0x10

EVENT_OFFCORE_REQUESTS_BUFFER_SQ_FULL   0xB2 PMC
UMASK_OFFCORE_REQUESTS_BUFFER_SQ_FULL   0x01

# The only officially released event is L2_TRANS_L2_WB
# All others count something but no guarantees
EVENT_L2_TRANS                0xF0  PMC
UMASK_L2_TRANS_DEMAND_DATA_RD 0x01
UMASK_L2_TRANS_RFO            0x02
UMASK_L2_TRANS_CODE_RD        0x04
UMASK_L2_TRANS_ALL_PF         0x08
UMASK_L2_TRANS_L1D_WB         0x10
UMASK_L2_TRANS_L2_FILL        0x20
UMASK_L2_TRANS_L2_WB          0x40
UMASK_L2_TRANS_ALL_REQUESTS   0x80

EVENT_LONGEST_LAT_CACHE                 0x2E PMC
UMASK_LONGEST_LAT_CACHE_MISS            0x41
UMASK_LONGEST_LAT_CACHE_REFERENCE       0x4F


EVENT_L2_RQSTS                          0x24 PMC
UMASK_L2_RQSTS_DEMAND_DATA_RD_MISS      0x21
UMASK_L2_RQSTS_DEMAND_DATA_RD_HIT       0x41
UMASK_L2_RQSTS_ALL_DEMAND_DATA_RD       0xE1
UMASK_L2_RQSTS_ALL_RFO                  0xE2
UMASK_L2_RQSTS_ALL_CODE_RD              0xE4
UMASK_L2_RQSTS_ALL_PF                   0xF8
UMASK_L2_RQSTS_PF_MISS                  0x38
UMASK_L2_RQSTS_PF_HIT                   0xD8
UMASK_L2_RQSTS_RFO_HIT                  0x42
UMASK_L2_RQSTS_RFO_MISS                 0x22
UMASK_L2_RQSTS_CODE_RD_HIT              0x44
UMASK_L2_RQSTS_CODE_RD_MISS             0x24
UMASK_L2_RQSTS_ALL_DEMAND_MISS          0x27
UMASK_L2_RQSTS_ALL_DEMAND_REFERENCES    0xE7
UMASK_L2_RQSTS_MISS                     0x3F
UMASK_L2_RQSTS_REFERENCES               0xFF

EVENT_IDQ                               0x79 PMC
UMASK_IDQ_MITE_UOPS                     0x04
UMASK_IDQ_DSB_UOPS                      0x08
UMASK_IDQ_MS_DSB_UOPS                   0x10
UMASK_IDQ_MS_MITE_UOPS                  0x20
UMASK_IDQ_MS_UOPS                       0x30
DEFAULT_OPTIONS_IDQ_MITE_CYCLES         EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_MITE_CYCLES                   0x04
DEFAULT_OPTIONS_IDQ_MITE_CYCLES_1_UOPS EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_MITE_CYCLES_1_UOPS            0x04
DEFAULT_OPTIONS_IDQ_MITE_CYCLES_2_UOPS EVENT_OPTION_THRESHOLD=0x2
UMASK_IDQ_MITE_CYCLES_2_UOPS            0x04
DEFAULT_OPTIONS_IDQ_MITE_CYCLES_3_UOPS EVENT_OPTION_THRESHOLD=0x3
UMASK_IDQ_MITE_CYCLES_3_UOPS            0x04
DEFAULT_OPTIONS_IDQ_MITE_CYCLES_4_UOPS EVENT_OPTION_THRESHOLD=0x4
UMASK_IDQ_MITE_CYCLES_4_UOPS            0x04
DEFAULT_OPTIONS_IDQ_MITE_CYCLES_5_UOPS EVENT_OPTION_THRESHOLD=0x5
UMASK_IDQ_MITE_CYCLES_5_UOPS            0x04
DEFAULT_OPTIONS_IDQ_MITE_CYCLES_6_UOPS EVENT_OPTION_THRESHOLD=0x6
UMASK_IDQ_MITE_CYCLES_6_UOPS            0x04
DEFAULT_OPTIONS_IDQ_DSB_CYCLES          EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_DSB_CYCLES                    0x08
DEFAULT_OPTIONS_IDQ_DSB_CYCLES_1_UOPS EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_DSB_CYCLES_1_UOPS             0x08
DEFAULT_OPTIONS_IDQ_DSB_CYCLES_2_UOPS EVENT_OPTION_THRESHOLD=0x2
UMASK_IDQ_DSB_CYCLES_2_UOPS             0x08
DEFAULT_OPTIONS_IDQ_DSB_CYCLES_3_UOPS EVENT_OPTION_THRESHOLD=0x3
UMASK_IDQ_DSB_CYCLES_3_UOPS             0x08
DEFAULT_OPTIONS_IDQ_DSB_CYCLES_4_UOPS EVENT_OPTION_THRESHOLD=0x4
UMASK_IDQ_DSB_CYCLES_4_UOPS             0x08
DEFAULT_OPTIONS_IDQ_DSB_CYCLES_5_UOPS EVENT_OPTION_THRESHOLD=0x5
UMASK_IDQ_DSB_CYCLES_5_UOPS             0x08
DEFAULT_OPTIONS_IDQ_DSB_CYCLES_6_UOPS EVENT_OPTION_THRESHOLD=0x6
UMASK_IDQ_DSB_CYCLES_6_UOPS             0x08
DEFAULT_OPTIONS_IDQ_MS_DSB_CYCLES       EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_MS_DSB_CYCLES                 0x10
DEFAULT_OPTIONS_IDQ_MS_DSB_CYCLES_1_UOPS EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_MS_DSB_CYCLES_1_UOPS          0x10
DEFAULT_OPTIONS_IDQ_MS_DSB_CYCLES_2_UOPS EVENT_OPTION_THRESHOLD=0x2
UMASK_IDQ_MS_DSB_CYCLES_2_UOPS          0x10
DEFAULT_OPTIONS_IDQ_MS_DSB_CYCLES_3_UOPS EVENT_OPTION_THRESHOLD=0x3
UMASK_IDQ_MS_DSB_CYCLES_3_UOPS          0x10
DEFAULT_OPTIONS_IDQ_MS_DSB_CYCLES_4_UOPS EVENT_OPTION_THRESHOLD=0x4
UMASK_IDQ_MS_DSB_CYCLES_4_UOPS          0x10
DEFAULT_OPTIONS_IDQ_MS_DSB_CYCLES_5_UOPS EVENT_OPTION_THRESHOLD=0x5
UMASK_IDQ_MS_DSB_CYCLES_5_UOPS          0x10
DEFAULT_OPTIONS_IDQ_MS_DSB_CYCLES_6_UOPS EVENT_OPTION_THRESHOLD=0x6
UMASK_IDQ_MS_DSB_CYCLES_6_UOPS          0x10
DEFAULT_OPTIONS_IDQ_MS_DSB_OCCUR        EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_EDGE=1
UMASK_IDQ_MS_DSB_OCCUR                  0x10
DEFAULT_OPTIONS_IDQ_MS_MITE_CYCLES      EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_MS_MITE_CYCLES                0x20
DEFAULT_OPTIONS_IDQ_MS_MITE_CYCLES_1_UOPS EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_MS_MITE_CYCLES_1_UOPS         0x20
DEFAULT_OPTIONS_IDQ_MS_MITE_CYCLES_2_UOPS EVENT_OPTION_THRESHOLD=0x2
UMASK_IDQ_MS_MITE_CYCLES_2_UOPS         0x20
DEFAULT_OPTIONS_IDQ_MS_MITE_CYCLES_3_UOPS EVENT_OPTION_THRESHOLD=0x3
UMASK_IDQ_MS_MITE_CYCLES_3_UOPS         0x20
DEFAULT_OPTIONS_IDQ_MS_MITE_CYCLES_4_UOPS EVENT_OPTION_THRESHOLD=0x4
UMASK_IDQ_MS_MITE_CYCLES_4_UOPS         0x20
DEFAULT_OPTIONS_IDQ_MS_MITE_CYCLES_5_UOPS EVENT_OPTION_THRESHOLD=0x5
UMASK_IDQ_MS_MITE_CYCLES_5_UOPS         0x20
DEFAULT_OPTIONS_IDQ_MS_MITE_CYCLES_6_UOPS EVENT_OPTION_THRESHOLD=0x6
UMASK_IDQ_MS_MITE_CYCLES_6_UOPS         0x20
DEFAULT_OPTIONS_IDQ_MS_CYCLES           EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_MS_CYCLES                     0x30
DEFAULT_OPTIONS_IDQ_MS_CYCLES_1_UOPS EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_MS_CYCLES_1_UOPS              0x30
DEFAULT_OPTIONS_IDQ_MS_CYCLES_2_UOPS EVENT_OPTION_THRESHOLD=0x2
UMASK_IDQ_MS_CYCLES_2_UOPS              0x30
DEFAULT_OPTIONS_IDQ_MS_CYCLES_3_UOPS EVENT_OPTION_THRESHOLD=0x3
UMASK_IDQ_MS_CYCLES_3_UOPS              0x30
DEFAULT_OPTIONS_IDQ_MS_CYCLES_4_UOPS EVENT_OPTION_THRESHOLD=0x4
UMASK_IDQ_MS_CYCLES_4_UOPS              0x30
DEFAULT_OPTIONS_IDQ_MS_CYCLES_5_UOPS EVENT_OPTION_THRESHOLD=0x5
UMASK_IDQ_MS_CYCLES_5_UOPS              0x30
DEFAULT_OPTIONS_IDQ_MS_CYCLES_6_UOPS EVENT_OPTION_THRESHOLD=0x6
UMASK_IDQ_MS_CYCLES_6_UOPS              0x30
DEFAULT_OPTIONS_IDQ_MS_SWITCHES         EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_EDGE=1
UMASK_IDQ_MS_SWITCHES                   0x30
DEFAULT_OPTIONS_IDQ_ALL_DSB_CYCLES_ANY_UOPS EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_ALL_DSB_CYCLES_ANY_UOPS       0x18
DEFAULT_OPTIONS_IDQ_ALL_DSB_CYCLES_1_UOPS EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_ALL_DSB_CYCLES_1_UOPS         0x18
DEFAULT_OPTIONS_IDQ_ALL_DSB_CYCLES_2_UOPS EVENT_OPTION_THRESHOLD=0x2
UMASK_IDQ_ALL_DSB_CYCLES_2_UOPS         0x18
DEFAULT_OPTIONS_IDQ_ALL_DSB_CYCLES_3_UOPS EVENT_OPTION_THRESHOLD=0x3
UMASK_IDQ_ALL_DSB_CYCLES_3_UOPS         0x18
DEFAULT_OPTIONS_IDQ_ALL_DSB_CYCLES_4_UOPS EVENT_OPTION_THRESHOLD=0x4
UMASK_IDQ_ALL_DSB_CYCLES_4_UOPS         0x18
DEFAULT_OPTIONS_IDQ_ALL_DSB_CYCLES_5_UOPS EVENT_OPTION_THRESHOLD=0x5
UMASK_IDQ_ALL_DSB_CYCLES_5_UOPS         0x18
DEFAULT_OPTIONS_IDQ_ALL_DSB_CYCLES_6_UOPS EVENT_OPTION_THRESHOLD=0x6
UMASK_IDQ_ALL_DSB_CYCLES_6_UOPS         0x18
DEFAULT_OPTIONS_IDQ_ALL_MITE_CYCLES_ANY_UOPS  EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_ALL_MITE_CYCLES_ANY_UOPS      0x24
DEFAULT_OPTIONS_IDQ_ALL_MITE_CYCLES_1_UOPS EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_ALL_MITE_CYCLES_1_UOPS        0x24
DEFAULT_OPTIONS_IDQ_ALL_MITE_CYCLES_2_UOPS EVENT_OPTION_THRESHOLD=0x2
UMASK_IDQ_ALL_MITE_CYCLES_2_UOPS        0x24
DEFAULT_OPTIONS_IDQ_ALL_MITE_CYCLES_3_UOPS EVENT_OPTION_THRESHOLD=0x3
UMASK_IDQ_ALL_MITE_CYCLES_3_UOPS        0x24
DEFAULT_OPTIONS_IDQ_ALL_MITE_CYCLES_4_UOPS EVENT_OPTION_THRESHOLD=0x4
UMASK_IDQ_ALL_MITE_CYCLES_4_UOPS        0x24
DEFAULT_OPTIONS_IDQ_ALL_MITE_CYCLES_5_UOPS EVENT_OPTION_THRESHOLD=0x5
UMASK_IDQ_ALL_MITE_CYCLES_5_UOPS        0x24
DEFAULT_OPTIONS_IDQ_ALL_MITE_CYCLES_6_UOPS EVENT_OPTION_THRESHOLD=0x6
UMASK_IDQ_ALL_MITE_CYCLES_6_UOPS        0x24
DEFAULT_OPTIONS_IDQ_ALL_CYCLES_ANY_UOPS  EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_ALL_CYCLES_ANY_UOPS      0x3C
DEFAULT_OPTIONS_IDQ_ALL_CYCLES_1_UOPS EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_ALL_CYCLES_1_UOPS        0x3C
DEFAULT_OPTIONS_IDQ_ALL_CYCLES_2_UOPS EVENT_OPTION_THRESHOLD=0x2
UMASK_IDQ_ALL_CYCLES_2_UOPS        0x3C
DEFAULT_OPTIONS_IDQ_ALL_CYCLES_3_UOPS EVENT_OPTION_THRESHOLD=0x3
UMASK_IDQ_ALL_CYCLES_3_UOPS        0x3C
DEFAULT_OPTIONS_IDQ_ALL_CYCLES_4_UOPS EVENT_OPTION_THRESHOLD=0x4
UMASK_IDQ_ALL_CYCLES_4_UOPS        0x3C
DEFAULT_OPTIONS_IDQ_ALL_CYCLES_5_UOPS EVENT_OPTION_THRESHOLD=0x5
UMASK_IDQ_ALL_CYCLES_5_UOPS        0x3C
DEFAULT_OPTIONS_IDQ_ALL_CYCLES_6_UOPS EVENT_OPTION_THRESHOLD=0x6
UMASK_IDQ_ALL_CYCLES_6_UOPS        0x3C

EVENT_ROB_MISC_EVENTS_LBR_INSERTS       0xCC PMC
UMASK_ROB_MISC_EVENTS_LBR_INSERTS       0x20

# Intel released only the event L2_LINES_IN.ALL for SKX
# Since this event has the umask 0x1F, the each bit has
# a meaning, so I added the I, S and E events. I didn't
# find the meaning of the other two bits 0x08 and 0x10.
EVENT_L2_LINES_IN                       0xF1 PMC
UMASK_L2_LINES_IN_I                     0x01
UMASK_L2_LINES_IN_S                     0x02
UMASK_L2_LINES_IN_E                     0x04
UMASK_L2_LINES_IN_ALL                   0x1F

EVENT_L2_LINES_OUT                      0xF2 PMC
UMASK_L2_LINES_OUT_SILENT               0x01
UMASK_L2_LINES_OUT_NON_SILENT           0x02
UMASK_L2_LINES_OUT_USELESS_PREF         0x04

EVENT_SQ_MISC                           0xF4 PMC
UMASK_SQ_MISC_SPLIT_LOCK                0x10

EVENT_ARITH_DIVIDER                     0x14 PMC
UMASK_ARITH_DIVIDER_ACTIVE              0x01
DEFAULT_OPTIONS_ARITH_DIVIDER_COUNT     EVENT_OPTION_EDGE=0x1,EVENT_OPTION_THRESHOLD=0x1
UMASK_ARITH_DIVIDER_COUNT               0x01

EVENT_LSD_UOPS                 0xA8   PMC
UMASK_LSD_UOPS                 0x01
DEFAULT_OPTIONS_LSD_UOPS_CYCLES_1 EVENT_OPTION_THRESHOLD=0x1
UMASK_LSD_UOPS_CYCLES_1         0x01
DEFAULT_OPTIONS_LSD_UOPS_CYCLES_2 EVENT_OPTION_THRESHOLD=0x2
UMASK_LSD_UOPS_CYCLES_2         0x01
DEFAULT_OPTIONS_LSD_UOPS_CYCLES_3 EVENT_OPTION_THRESHOLD=0x3
UMASK_LSD_UOPS_CYCLES_3         0x01
DEFAULT_OPTIONS_LSD_UOPS_CYCLES_4 EVENT_OPTION_THRESHOLD=0x4
UMASK_LSD_UOPS_CYCLES_4         0x01
DEFAULT_OPTIONS_LSD_UOPS_CYCLES_ACTIVE EVENT_OPTION_THRESHOLD=0x01
UMASK_LSD_UOPS_CYCLES_ACTIVE        0x01
DEFAULT_OPTIONS_LSD_UOPS_CYCLES_INACTIVE EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=1
UMASK_LSD_UOPS_CYCLES_INACTIVE         0x01

EVENT_OTHER_ASSISTS_ANY                 0xC1 PMC
UMASK_OTHER_ASSISTS_ANY                 0x3F

EVENT_FRONTEND_RETIRED_LATENCY          0xC6 PMC
UMASK_FRONTEND_RETIRED_LATENCY_GE_8     0x01 0x00 0x400806
UMASK_FRONTEND_RETIRED_LATENCY_GE_16    0x01 0x00 0x401006
UMASK_FRONTEND_RETIRED_LATENCY_GE_32    0x01 0x00 0x402006
UMASK_FRONTEND_RETIRED_LATENCY_GE_64    0x01 0x00 0x404006
UMASK_FRONTEND_RETIRED_LATENCY_GE_128   0x01 0x00 0x408006
UMASK_FRONTEND_RETIRED_LATENCY_GE_256   0x01 0x00 0x410006
UMASK_FRONTEND_RETIRED_LATENCY_GE_512   0x01 0x00 0x420006
UMASK_FRONTEND_RETIRED_LATENCY_GE_2_BUBBLES_GE_1 0x01 0x00 0x100206
UMASK_FRONTEND_RETIRED_LATENCY_GE_2_BUBBLES_GE_3 0x01 0x00 0x300206

EVENT_CORE_POWER                        0x28 PMC
UMASK_CORE_POWER_LVL0_TURBO_LICENSE     0x07
UMASK_CORE_POWER_LVL1_TURBO_LICENSE     0x18
UMASK_CORE_POWER_LVL2_TURBO_LICENSE     0x20

EVENT_MEMORY_DISAMBIGUATION_HISTORY_RESET   0x09 PMC
UMASK_MEMORY_DISAMBIGUATION_HISTORY_RESET   0x01

# Errata CLX3
EVENT_IDI_MISC                          0xFE PMC
UMASK_IDI_MISC_WB_UPGRADE               0x02
UMASK_IDI_MISC_WB_DOWNGRADE             0x04

EVENT_OFFCORE_RESPONSE_0                            0xB7 PMC
OPTIONS_OFFCORE_RESPONSE_0_OPTIONS                  EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_MATCH1_MASK
UMASK_OFFCORE_RESPONSE_0_OPTIONS                    0x01 0xFF 0xFF

EVENT_OFFCORE_RESPONSE_1                            0xBB PMC
OPTIONS_OFFCORE_RESPONSE_1_OPTIONS                  EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_MATCH1_MASK
UMASK_OFFCORE_RESPONSE_1_OPTIONS                    0x01 0xFF 0xFF

EVENT_EVENT_MSG                     0x42 UBOX
UMASK_EVENT_MSG_VLW_RCVD            0x01
UMASK_EVENT_MSG_MSI_RCVD            0x02
UMASK_EVENT_MSG_IPI_RCVD            0x04
UMASK_EVENT_MSG_DOORBELL_RCVD       0x08
UMASK_EVENT_MSG_INT_PRIO            0x10

EVENT_LOCK_CYCLES                   0x44 UBOX
UMASK_LOCK_CYCLES                   0x00

EVENT_PHOLD_CYCLES                  0x45 UBOX
UMASK_PHOLD_CYCLES_ASSERT_TO_ACK    0x01

EVENT_RACU_DRNG                 0x4C UBOX
UMASK_RACU_DRNG_RDRAND          0x01
UMASK_RACU_DRNG_RDSEED          0x02
UMASK_RACU_DRNG_PFTCH_BUF_EMPTY 0x04

EVENT_RACU_REQUESTS                 0x46 UBOX
UMASK_RACU_REQUESTS                 0x00

EVENT_UNCORE_CLOCK                  0x00 UBOXFIX
UMASK_UNCORE_CLOCK                  0x00

EVENT_2LM_NM_SETCONFLICTS           0x64 CBOX
UMASK_2LM_NM_SETCONFLICTS_SF        0x01
UMASK_2LM_NM_SETCONFLICTS_LLC       0x02
UMASK_2LM_NM_SETCONFLICTS_TOR       0x04
UMASK_2LM_NM_SETCONFLICTS_TOR_REJECT 0x08
UMASK_2LM_NM_SETCONFLICTS_IODC      0x10

EVENT_SF_EVICTION                   0x3D CBOX
UMASK_SF_EVICTION_M                 0x01
UMASK_SF_EVICTION_E                 0x02
UMASK_SF_EVICTION_S                 0x04
UMASK_SF_EVICTION_ANY               0x07


EVENT_BYPASS_CHA_IMC                0x57 CBOX
UMASK_BYPASS_CHA_IMC_TAKEN          0x01
UMASK_BYPASS_CHA_IMC_INTERMEDIATE   0x02
UMASK_BYPASS_CHA_IMC_NOT_TAKEN      0x04

EVENT_CBOX_CLOCKTICKS               0x00 CBOX
UMASK_CBOX_CLOCKTICKS               0x00

EVENT_CORE_PMA                      0x17 CBOX
UMASK_CORE_PMA_C1_STATE             0x01
UMASK_CORE_PMA_C1_TRANSITION        0x02
UMASK_CORE_PMA_C6_STATE             0x04
UMASK_CORE_PMA_C6_TRANSITION        0x08
UMASK_CORE_PMA_GV                   0x10

EVENT_CORE_SNP                      0x33 CBOX
UMASK_CORE_SNP_EXT_ONE              0x21
UMASK_CORE_SNP_EXT_GTONE            0x22
UMASK_CORE_SNP_EXT_REMOTE           0x24
UMASK_CORE_SNP_CORE_ONE             0x41
UMASK_CORE_SNP_CORE_GTONE           0x42
UMASK_CORE_SNP_CORE_REMOTE          0x44
UMASK_CORE_SNP_EVICT_ONE            0x81
UMASK_CORE_SNP_EVICT_GTONE          0x82
UMASK_CORE_SNP_EVICT_REMOTE         0x84
UMASK_CORE_SNP_ANY_ONE              0xE1
UMASK_CORE_SNP_ANY_GTONE            0xE2
UMASK_CORE_SNP_ANY_REMOTE           0xE4

EVENT_COUNTER0_OCCUPANCY            0x1F CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0|CBOX24C0|CBOX25C0|CBOX26C0|CBOX27C0
UMASK_COUNTER0_OCCUPANCY            0x00
DEFAULT_OPTIONS_COUNTER0_OCCUPANCY_COUNT EVENT_OPTION_THRESHOLD=0x01
UMASK_COUNTER0_OCCUPANCY_COUNT      0x00

EVENT_DIR_LOOKUP                    0x53 CBOX
UMASK_DIR_LOOKUP_SNP                0x01
UMASK_DIR_LOOKUP_NO_SNP             0x02

EVENT_DIR_UPDATE                    0x54 CBOX
UMASK_DIR_UPDATE_HA                 0x01
UMASK_DIR_UPDATE_TOR                0x02

EVENT_HITME_HIT                     0x5F CBOX
UMASK_HITME_HIT_EX_RDS              0x01
UMASK_HITME_HIT_SHARED_OWNREQ       0x04
UMASK_HITME_HIT_WBMTOE              0x08
UMASK_HITME_HIT_WBMTOI_OR_S         0x10

EVENT_HITME_LOOKUP                  0x5E CBOX
UMASK_HITME_LOOKUP_READ             0x01
UMASK_HITME_LOOKUP_WRITE            0x02

EVENT_HITME_MISS                    0x60 CBOX
UMASK_HITME_MISS_SHARED_RDINVOWN    0x20
UMASK_HITME_MISS_NOTSHARED_RDINVOWN 0x40
UMASK_HITME_MISS_READ_OR_INV        0x80

EVENT_HITME_UPDATE                          0x61 CBOX
UMASK_HITME_UPDATE_DEALLOCATE_RSPFWDI_LOC   0x01
UMASK_HITME_UPDATE_RSPFWDI_REM              0x02
UMASK_HITME_UPDATE_SHARED                   0x04
UMASK_HITME_UPDATE_RDINVOWN                 0x08
UMASK_HITME_UPDATE_DEALLOCATE               0x10

EVENT_IMC_READS_COUNT               0x59 CBOX
UMASK_IMC_READS_COUNT_NORMAL        0x01
UMASK_IMC_READS_COUNT_PRIORITY      0x02
UMASK_IMC_READS_COUNT_ANY           0x03

EVENT_IMC_WRITES_COUNT                      0x5B CBOX
UMASK_IMC_WRITES_COUNT_FULL                 0x01
UMASK_IMC_WRITES_COUNT_PARTIAL              0x02
UMASK_IMC_WRITES_COUNT_FULL_PRIORITY        0x04
UMASK_IMC_WRITES_COUNT_PARTIAL_PRIORITY     0x08
UMASK_IMC_WRITES_COUNT_FULL_MIG             0x10
UMASK_IMC_WRITES_COUNT_PARTIAL_MIG          0x20
UMASK_IMC_WRITES_COUNT_ANY                  0x3F

EVENT_IODC_ALLOC                    0x62 CBOX
UMASK_IODC_ALLOC_INVITOM            0x01
UMASK_IODC_ALLOC_IODCFULL           0x02
UMASK_IODC_ALLOC_OSBGATED           0x04

EVENT_IODC_DEALLOC                  0x63 CBOX
UMASK_IODC_DEALLOC_WBMTOE           0x01
UMASK_IODC_DEALLOC_WBMTOI           0x02
UMASK_IODC_DEALLOC_WBPUSHMTOI       0x04
UMASK_IODC_DEALLOC_SNPOUT           0x08
UMASK_IODC_DEALLOC_ALL              0x10

EVENT_LLC_LOOKUP                    0x34 CBOX
OPTIONS_LLC_LOOKUP_DATA_READ        EVENT_OPTION_STATE_MASK
UMASK_LLC_LOOKUP_DATA_READ          0x03
OPTIONS_LLC_LOOKUP_WRITE            EVENT_OPTION_STATE_MASK
UMASK_LLC_LOOKUP_WRITE              0x05
OPTIONS_LLC_LOOKUP_REMOTE_SNOOP     EVENT_OPTION_STATE_MASK
UMASK_LLC_LOOKUP_REMOTE_SNOOP       0x09
OPTIONS_LLC_LOOKUP_ANY              EVENT_OPTION_STATE_MASK
UMASK_LLC_LOOKUP_ANY                0x11
OPTIONS_LLC_LOOKUP_LOCAL            EVENT_OPTION_STATE_MASK
UMASK_LLC_LOOKUP_LOCAL              0x31
OPTIONS_LLC_LOOKUP_REMOTE           EVENT_OPTION_STATE_MASK
UMASK_LLC_LOOKUP_REMOTE             0x91

EVENT_LLC_VICTIMS                   0x37 CBOX
UMASK_LLC_VICTIMS_M_STATE           0x01
UMASK_LLC_VICTIMS_E_STATE           0x02
UMASK_LLC_VICTIMS_S_STATE           0x04
UMASK_LLC_VICTIMS_F_STATE           0x08
UMASK_LLC_VICTIMS_ANY_STATE         0x0F
UMASK_LLC_VICTIMS_LOCAL             0x20
UMASK_LLC_VICTIMS_REMOTE            0x80
UMASK_LLC_VICTIMS_M_LOCAL           0x21
UMASK_LLC_VICTIMS_E_LOCAL           0x22
UMASK_LLC_VICTIMS_S_LOCAL           0x24
UMASK_LLC_VICTIMS_F_LOCAL           0x28
UMASK_LLC_VICTIMS_ANY_LOCAL         0x2F
UMASK_LLC_VICTIMS_M_REMOTE          0x81
UMASK_LLC_VICTIMS_E_REMOTE          0x82
UMASK_LLC_VICTIMS_S_REMOTE          0x84
UMASK_LLC_VICTIMS_F_REMOTE          0x88
UMASK_LLC_VICTIMS_ANY_REMOTE        0x8F
UMASK_LLC_VICTIMS_M_ANY             0xA1
UMASK_LLC_VICTIMS_E_ANY             0xA2
UMASK_LLC_VICTIMS_S_ANY             0xA4
UMASK_LLC_VICTIMS_F_ANY             0xA8
UMASK_LLC_VICTIMS_ANY_ANY           0xAF

EVENT_MISC                          0x39 CBOX
UMASK_MISC_RSPI_WAS_FSE             0x01
UMASK_MISC_WC_ALIASING              0x02
UMASK_MISC_RFO_HIT_S                0x08
UMASK_MISC_CVZERO_PREFETCH_VICTIM   0x10
UMASK_MISC_CVZERO_PREFETCH_MISS     0x20

EVENT_OSB_EDR                       0x55 CBOX
UMASK_OSB_EDR                       0x00

EVENT_READ_NO_CREDITS               0x58 CBOX
UMASK_READ_NO_CREDITS_MC0_SMI0      0x01
UMASK_READ_NO_CREDITS_MC1_SMI1      0x02
UMASK_READ_NO_CREDITS_MC_ALL        0x03
UMASK_READ_NO_CREDITS_EDC0_SMI2     0x04
UMASK_READ_NO_CREDITS_EDC1_SMI3     0x08
UMASK_READ_NO_CREDITS_EDC2_SMI4     0x10
UMASK_READ_NO_CREDITS_EDC3_SMI5     0x20
UMASK_READ_NO_CREDITS_EDC_ALL       0x3C

EVENT_WRITE_NO_CREDITS               0x5A CBOX
UMASK_WRITE_NO_CREDITS_MC0_SMI0      0x01
UMASK_WRITE_NO_CREDITS_MC1_SMI1      0x02
UMASK_WRITE_NO_CREDITS_MC_ALL        0x03
UMASK_WRITE_NO_CREDITS_EDC0_SMI2     0x04
UMASK_WRITE_NO_CREDITS_EDC1_SMI3     0x08
UMASK_WRITE_NO_CREDITS_EDC2_SMI4     0x10
UMASK_WRITE_NO_CREDITS_EDC3_SMI5     0x20
UMASK_WRITE_NO_CREDITS_EDC_ALL       0x3C

EVENT_REQUESTS                      0x50 CBOX
UMASK_REQUESTS_READS_LOCAL          0x01
UMASK_REQUESTS_READS_REMOTE         0x02
UMASK_REQUESTS_READS                0x03
UMASK_REQUESTS_WRITES_LOCAL         0x04
UMASK_REQUESTS_WRITES_REMOTE        0x08
UMASK_REQUESTS_WRITES               0x0C
UMASK_REQUESTS_INVITOE_LOCAL        0x10
UMASK_REQUESTS_INVITOE_REMOTE       0x20
UMASK_REQUESTS_INVITOE              0x30

EVENT_RXC_INSERTS                   0x13 CBOX
UMASK_RXC_INSERTS_IRQ               0x01
UMASK_RXC_INSERTS_IRQ_REJ           0x02
UMASK_RXC_INSERTS_IPQ               0x04
UMASK_RXC_INSERTS_PRQ               0x10
UMASK_RXC_INSERTS_PRQ_REJ           0x20
UMASK_RXC_INSERTS_RRQ               0x20
UMASK_RXC_INSERTS_WBQ               0x40

EVENT_RXC_IPQ0_REJECT               0x22 CBOX
UMASK_RXC_IPQ0_REJECT_AD_REQ_VN0    0x01
UMASK_RXC_IPQ0_REJECT_AD_RSP_VN0    0x02
UMASK_RXC_IPQ0_REJECT_BL_RSP_VN0    0x04
UMASK_RXC_IPQ0_REJECT_BL_WB_VN0     0x08
UMASK_RXC_IPQ0_REJECT_BL_NCB_VN0    0x10
UMASK_RXC_IPQ0_REJECT_BL_NCS_VN0    0x20
UMASK_RXC_IPQ0_REJECT_AK_NON_UPI    0x40
UMASK_RXC_IPQ0_REJECT_IV_NON_UPI    0x80

EVENT_RXC_IPQ1_REJECT               0x23 CBOX
UMASK_RXC_IPQ1_REJECT_ANY0          0x01
UMASK_RXC_IPQ1_REJECT_HA            0x02
UMASK_RXC_IPQ1_REJECT_LLC_VICTIM    0x04
UMASK_RXC_IPQ1_REJECT_SF_VICTIM     0x08
UMASK_RXC_IPQ1_REJECT_VICTIM        0x10
UMASK_RXC_IPQ1_REJECT_LLC_OR_SF_WAY 0x20
UMASK_RXC_IPQ1_REJECT_ALLOW_SNP     0x40
UMASK_RXC_IPQ1_REJECT_PA_MATCH      0x80

EVENT_RXC_IRQ0_REJECT               0x18 CBOX
UMASK_RXC_IRQ0_REJECT_AD_REQ_VN0    0x01
UMASK_RXC_IRQ0_REJECT_AD_RSP_VN0    0x02
UMASK_RXC_IRQ0_REJECT_BL_RSP_VN0    0x04
UMASK_RXC_IRQ0_REJECT_BL_WB_VN0     0x08
UMASK_RXC_IRQ0_REJECT_BL_NCB_VN0    0x10
UMASK_RXC_IRQ0_REJECT_BL_NCS_VN0    0x20
UMASK_RXC_IRQ0_REJECT_AK_NON_UPI    0x40
UMASK_RXC_IRQ0_REJECT_IV_NON_UPI    0x80

EVENT_RXC_IRQ1_REJECT               0x19 CBOX
UMASK_RXC_IRQ1_REJECT_ANY0          0x01
UMASK_RXC_IRQ1_REJECT_HA            0x02
UMASK_RXC_IRQ1_REJECT_LLC_VICTIM    0x04
UMASK_RXC_IRQ1_REJECT_SF_VICTIM     0x08
UMASK_RXC_IRQ1_REJECT_VICTIM        0x10
UMASK_RXC_IRQ1_REJECT_LLC_OR_SF_WAY 0x20
UMASK_RXC_IRQ1_REJECT_ALLOW_SNP     0x40
UMASK_RXC_IRQ1_REJECT_PA_MATCH      0x80

EVENT_RXC_ISMQ0_REJECT               0x24 CBOX
UMASK_RXC_ISMQ0_REJECT_AD_REQ_VN0    0x01
UMASK_RXC_ISMQ0_REJECT_AD_RSP_VN0    0x02
UMASK_RXC_ISMQ0_REJECT_BL_RSP_VN0    0x04
UMASK_RXC_ISMQ0_REJECT_BL_WB_VN0     0x08
UMASK_RXC_ISMQ0_REJECT_BL_NCB_VN0    0x10
UMASK_RXC_ISMQ0_REJECT_BL_NCS_VN0    0x20
UMASK_RXC_ISMQ0_REJECT_AK_NON_UPI    0x40
UMASK_RXC_ISMQ0_REJECT_IV_NON_UPI    0x80

EVENT_RXC_ISMQ1_REJECT               0x25 CBOX
UMASK_RXC_ISMQ1_REJECT_ANY0          0x01
UMASK_RXC_ISMQ1_REJECT_HA            0x02

EVENT_RXC_ISMQ0_RETRY               0x2C CBOX
UMASK_RXC_ISMQ0_RETRY_AD_REQ_VN0    0x01
UMASK_RXC_ISMQ0_RETRY_AD_RSP_VN0    0x02
UMASK_RXC_ISMQ0_RETRY_BL_RSP_VN0    0x04
UMASK_RXC_ISMQ0_RETRY_BL_WB_VN0     0x08
UMASK_RXC_ISMQ0_RETRY_BL_NCB_VN0    0x10
UMASK_RXC_ISMQ0_RETRY_BL_NCS_VN0    0x20
UMASK_RXC_ISMQ0_RETRY_AK_NON_UPI    0x40
UMASK_RXC_ISMQ0_RETRY_IV_NON_UPI    0x80

EVENT_RXC_ISMQ1_RETRY               0x2D CBOX
UMASK_RXC_ISMQ1_RETRY_ANY0          0x01
UMASK_RXC_ISMQ1_RETRY_HA            0x02

EVENT_RXC_OCCUPANCY                 0x11 CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0|CBOX24C0|CBOX25C0|CBOX26C0|CBOX27C0
UMASK_RXC_OCCUPANCY_IRQ             0x01
UMASK_RXC_OCCUPANCY_IPQ             0x04
UMASK_RXC_OCCUPANCY_RRQ             0x40
UMASK_RXC_OCCUPANCY_WBQ             0x80

EVENT_RXC_OTHER0_RETRY              0x2E CBOX
UMASK_RXC_OTHER0_RETRY_AD_REQ_VN0   0x01
UMASK_RXC_OTHER0_RETRY_AD_RSP_VN0   0x02
UMASK_RXC_OTHER0_RETRY_BL_RSP_VN0   0x04
UMASK_RXC_OTHER0_RETRY_BL_WB_VN0    0x08
UMASK_RXC_OTHER0_RETRY_BL_NCB_VN0   0x10
UMASK_RXC_OTHER0_RETRY_BL_NCS_VN0   0x20
UMASK_RXC_OTHER0_RETRY_AK_NON_UPI   0x40
UMASK_RXC_OTHER0_RETRY_IV_NON_UPI   0x80

EVENT_RXC_OTHER1_REJECT               0x2F CBOX
UMASK_RXC_OTHER1_REJECT_ANY0          0x01
UMASK_RXC_OTHER1_REJECT_HA            0x02
UMASK_RXC_OTHER1_REJECT_LLC_VICTIM    0x04
UMASK_RXC_OTHER1_REJECT_SF_VICTIM     0x08
UMASK_RXC_OTHER1_REJECT_VICTIM        0x10
UMASK_RXC_OTHER1_REJECT_LLC_OR_SF_WAY 0x20
UMASK_RXC_OTHER1_REJECT_ALLOW_SNP     0x40
UMASK_RXC_OTHER1_REJECT_PA_MATCH      0x80

EVENT_RXC_PRQ0_REJECT               0x20 CBOX
UMASK_RXC_PRQ0_REJECT_AD_REQ_VN0    0x01
UMASK_RXC_PRQ0_REJECT_AD_RSP_VN0    0x02
UMASK_RXC_PRQ0_REJECT_BL_RSP_VN0    0x04
UMASK_RXC_PRQ0_REJECT_BL_WB_VN0     0x08
UMASK_RXC_PRQ0_REJECT_BL_NCB_VN0    0x10
UMASK_RXC_PRQ0_REJECT_BL_NCS_VN0    0x20
UMASK_RXC_PRQ0_REJECT_AK_NON_UPI    0x40
UMASK_RXC_PRQ0_REJECT_IV_NON_UPI    0x80

EVENT_RXC_PRQ1_REJECT               0x21 CBOX
UMASK_RXC_PRQ1_REJECT_ANY0          0x01
UMASK_RXC_PRQ1_REJECT_HA            0x02
UMASK_RXC_PRQ1_REJECT_LLC_VICTIM    0x04
UMASK_RXC_PRQ1_REJECT_SF_VICTIM     0x08
UMASK_RXC_PRQ1_REJECT_VICTIM        0x10
UMASK_RXC_PRQ1_REJECT_LLC_OR_SF_WAY 0x20
UMASK_RXC_PRQ1_REJECT_ALLOW_SNP     0x40
UMASK_RXC_PRQ1_REJECT_PA_MATCH      0x80

EVENT_RXC_REQ_Q0_RETRY              0x2A CBOX
UMASK_RXC_REQ_Q0_RETRY_AD_REQ_VN0   0x01
UMASK_RXC_REQ_Q0_RETRY_AD_RSP_VN0   0x02
UMASK_RXC_REQ_Q0_RETRY_BL_RSP_VN0   0x04
UMASK_RXC_REQ_Q0_RETRY_BL_WB_VN0    0x08
UMASK_RXC_REQ_Q0_RETRY_BL_NCB_VN0   0x10
UMASK_RXC_REQ_Q0_RETRY_BL_NCS_VN0   0x20
UMASK_RXC_REQ_Q0_RETRY_AK_NON_UPI   0x40
UMASK_RXC_REQ_Q0_RETRY_IV_NON_UPI   0x80

EVENT_RXC_REQ_Q1_RETRY               0x2B CBOX
UMASK_RXC_REQ_Q1_RETRY_ANY0          0x01
UMASK_RXC_REQ_Q1_RETRY_HA            0x02
UMASK_RXC_REQ_Q1_RETRY_LLC_VICTIM    0x04
UMASK_RXC_REQ_Q1_RETRY_SF_VICTIM     0x08
UMASK_RXC_REQ_Q1_RETRY_VICTIM        0x10
UMASK_RXC_REQ_Q1_RETRY_LLC_OR_SF_WAY 0x20
UMASK_RXC_REQ_Q1_RETRY_ALLOW_SNP     0x40
UMASK_RXC_REQ_Q1_RETRY_PA_MATCH      0x80

EVENT_RXC_RRQ0_REJECT               0x26 CBOX
UMASK_RXC_RRQ0_REJECT_AD_REQ_VN0    0x01
UMASK_RXC_RRQ0_REJECT_AD_RSP_VN0    0x02
UMASK_RXC_RRQ0_REJECT_BL_RSP_VN0    0x04
UMASK_RXC_RRQ0_REJECT_BL_WB_VN0     0x08
UMASK_RXC_RRQ0_REJECT_BL_NCB_VN0    0x10
UMASK_RXC_RRQ0_REJECT_BL_NCS_VN0    0x20
UMASK_RXC_RRQ0_REJECT_AK_NON_UPI    0x40
UMASK_RXC_RRQ0_REJECT_IV_NON_UPI    0x80

EVENT_RXC_RRQ1_REJECT               0x27 CBOX
UMASK_RXC_RRQ1_REJECT_ANY0          0x01
UMASK_RXC_RRQ1_REJECT_HA            0x02
UMASK_RXC_RRQ1_REJECT_LLC_VICTIM    0x04
UMASK_RXC_RRQ1_REJECT_SF_VICTIM     0x08
UMASK_RXC_RRQ1_REJECT_VICTIM        0x10
UMASK_RXC_RRQ1_REJECT_LLC_OR_SF_WAY 0x20
UMASK_RXC_RRQ1_REJECT_ALLOW_SNP     0x40
UMASK_RXC_RRQ1_REJECT_PA_MATCH      0x80

EVENT_RXC_WBQ0_REJECT               0x28 CBOX
UMASK_RXC_WBQ0_REJECT_AD_REQ_VN0    0x01
UMASK_RXC_WBQ0_REJECT_AD_RSP_VN0    0x02
UMASK_RXC_WBQ0_REJECT_BL_RSP_VN0    0x04
UMASK_RXC_WBQ0_REJECT_BL_WB_VN0     0x08
UMASK_RXC_WBQ0_REJECT_BL_NCB_VN0    0x10
UMASK_RXC_WBQ0_REJECT_BL_NCS_VN0    0x20
UMASK_RXC_WBQ0_REJECT_AK_NON_UPI    0x40
UMASK_RXC_WBQ0_REJECT_IV_NON_UPI    0x80

EVENT_RXC_WBQ1_REJECT               0x29 CBOX
UMASK_RXC_WBQ1_REJECT_ANY0          0x01
UMASK_RXC_WBQ1_REJECT_HA            0x02
UMASK_RXC_WBQ1_REJECT_LLC_VICTIM    0x04
UMASK_RXC_WBQ1_REJECT_SF_VICTIM     0x08
UMASK_RXC_WBQ1_REJECT_VICTIM        0x10
UMASK_RXC_WBQ1_REJECT_LLC_OR_SF_WAY 0x20
UMASK_RXC_WBQ1_REJECT_ALLOW_SNP     0x40
UMASK_RXC_WBQ1_REJECT_PA_MATCH      0x80

EVENT_SNOOPS_SENT                   0x51 CBOX
UMASK_SNOOPS_SENT_ALL               0x01
UMASK_SNOOPS_SENT_LOCAL             0x04
UMASK_SNOOPS_SENT_REMOTE            0x08
UMASK_SNOOPS_SENT_BCST_LOCAL        0x10
UMASK_SNOOPS_SENT_BCST_REMOTE       0x20
UMASK_SNOOPS_SENT_DIRECT_LOCAL      0x40
UMASK_SNOOPS_SENT_DIRECT_REMOTE     0x80

EVENT_SNOOPS_RESP                   0x5C CBOX
UMASK_SNOOPS_RESP_RSPI              0x01
UMASK_SNOOPS_RESP_RSPS              0x02
UMASK_SNOOPS_RESP_RSPIFWD           0x04
UMASK_SNOOPS_RESP_RSPSFWD           0x08
UMASK_SNOOPS_RESP_RSP_WBWB          0x10
UMASK_SNOOPS_RESP_RSP_FWD_WB        0x20
UMASK_SNOOPS_RESP_RSPCNFLCTS        0x40
UMASK_SNOOPS_RESP_RSPFWD            0x80

EVENT_SNOOPS_RESP_LOCAL                   0x5D CBOX
UMASK_SNOOPS_RESP_LOCAL_RSPI              0x01
UMASK_SNOOPS_RESP_LOCAL_RSPS              0x02
UMASK_SNOOPS_RESP_LOCAL_RSPIFWD           0x04
UMASK_SNOOPS_RESP_LOCAL_RSPSFWD           0x08
UMASK_SNOOPS_RESP_LOCAL_RSP_WBWB          0x10
UMASK_SNOOPS_RESP_LOCAL_RSP_FWD_WB        0x20
UMASK_SNOOPS_RESP_LOCAL_RSPCNFLCTS        0x40
UMASK_SNOOPS_RESP_LOCAL_RSPFWD            0x80

EVENT_TOR_INSERTS                   0x35 CBOX
OPTIONS_TOR_INSERTS_IRQ             EVENT_OPTION_OPCODE_MASK
UMASK_TOR_INSERTS_IRQ               0x01
OPTIONS_TOR_INSERTS_EVICT           EVENT_OPTION_OPCODE_MASK
UMASK_TOR_INSERTS_EVICT             0x02
OPTIONS_TOR_INSERTS_PRQ             EVENT_OPTION_OPCODE_MASK
UMASK_TOR_INSERTS_PRQ               0x04
OPTIONS_TOR_INSERTS_IPQ             EVENT_OPTION_OPCODE_MASK
UMASK_TOR_INSERTS_IPQ               0x08
OPTIONS_TOR_INSERTS_HIT             EVENT_OPTION_OPCODE_MASK
UMASK_TOR_INSERTS_HIT               0x10
OPTIONS_TOR_INSERTS_IA_HIT          EVENT_OPTION_OPCODE_MASK
UMASK_TOR_INSERTS_IA_HIT            0x11
OPTIONS_TOR_INSERTS_IO_HIT          EVENT_OPTION_OPCODE_MASK
UMASK_TOR_INSERTS_IO_HIT            0x14
OPTIONS_TOR_INSERTS_ALL_HIT         EVENT_OPTION_OPCODE_MASK
UMASK_TOR_INSERTS_ALL_HIT           0x15
OPTIONS_TOR_INSERTS_MISS            EVENT_OPTION_OPCODE_MASK
UMASK_TOR_INSERTS_MISS              0x20
OPTIONS_TOR_INSERTS_IA_MISS         EVENT_OPTION_OPCODE_MASK
UMASK_TOR_INSERTS_IA_MISS           0x21
OPTIONS_TOR_INSERTS_IO_MISS         EVENT_OPTION_OPCODE_MASK
UMASK_TOR_INSERTS_IO_MISS           0x24
OPTIONS_TOR_INSERTS_ALL_MISS        EVENT_OPTION_OPCODE_MASK
UMASK_TOR_INSERTS_ALL_MISS          0x25
OPTIONS_TOR_INSERTS_IA              EVENT_OPTION_OPCODE_MASK
UMASK_TOR_INSERTS_IA                0x31
OPTIONS_TOR_INSERTS_IO              EVENT_OPTION_OPCODE_MASK
UMASK_TOR_INSERTS_IO                0x34
OPTIONS_TOR_INSERTS_ALL_IO_IA       EVENT_OPTION_OPCODE_MASK
UMASK_TOR_INSERTS_ALL_IO_IA         0x35

EVENT_TOR_OCCUPANCY                   0x36 CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0|CBOX24C0|CBOX25C0|CBOX26C0|CBOX27C0
OPTIONS_TOR_OCCUPANCY_IRQ             EVENT_OPTION_OPCODE_MASK
UMASK_TOR_OCCUPANCY_IRQ               0x01
OPTIONS_TOR_OCCUPANCY_EVICT           EVENT_OPTION_OPCODE_MASK
UMASK_TOR_OCCUPANCY_EVICT             0x02
OPTIONS_TOR_OCCUPANCY_PRQ             EVENT_OPTION_OPCODE_MASK
UMASK_TOR_OCCUPANCY_PRQ               0x04
OPTIONS_TOR_OCCUPANCY_IPQ             EVENT_OPTION_OPCODE_MASK
UMASK_TOR_OCCUPANCY_IPQ               0x08
OPTIONS_TOR_OCCUPANCY_HIT             EVENT_OPTION_OPCODE_MASK
UMASK_TOR_OCCUPANCY_HIT               0x10
OPTIONS_TOR_OCCUPANCY_IA_HIT          EVENT_OPTION_OPCODE_MASK
UMASK_TOR_OCCUPANCY_IA_HIT            0x11
OPTIONS_TOR_OCCUPANCY_IO_HIT          EVENT_OPTION_OPCODE_MASK
UMASK_TOR_OCCUPANCY_IO_HIT            0x14
OPTIONS_TOR_OCCUPANCY_ALL_HIT         EVENT_OPTION_OPCODE_MASK
UMASK_TOR_OCCUPANCY_ALL_HIT           0x17
OPTIONS_TOR_OCCUPANCY_MISS            EVENT_OPTION_OPCODE_MASK
UMASK_TOR_OCCUPANCY_MISS              0x20
OPTIONS_TOR_OCCUPANCY_IA_MISS         EVENT_OPTION_OPCODE_MASK
UMASK_TOR_OCCUPANCY_IA_MISS           0x21
OPTIONS_TOR_OCCUPANCY_IO_MISS         EVENT_OPTION_OPCODE_MASK
UMASK_TOR_OCCUPANCY_IO_MISS           0x24
OPTIONS_TOR_OCCUPANCY_ALL_MISS        EVENT_OPTION_OPCODE_MASK
UMASK_TOR_OCCUPANCY_ALL_MISS          0x27
OPTIONS_TOR_OCCUPANCY_IA              EVENT_OPTION_OPCODE_MASK
UMASK_TOR_OCCUPANCY_IA                0x31
OPTIONS_TOR_OCCUPANCY_IO              EVENT_OPTION_OPCODE_MASK
UMASK_TOR_OCCUPANCY_IO                0x34

EVENT_WB_PUSH_MTOI                  0x56 CBOX
UMASK_WB_PUSH_MTOI_LLC              0x01
UMASK_WB_PUSH_MTOI_MEM              0x02

EVENT_XSNP_RESP                     0x32 CBOX
UMASK_XSNP_RESP_EXT_RSP_HITFSE      0x21
UMASK_XSNP_RESP_EXT_RSPS_FWDFE      0x22
UMASK_XSNP_RESP_EXT_RSPI_FWDFE      0x24
UMASK_XSNP_RESP_EXT_RSPS_FWDM       0x28
UMASK_XSNP_RESP_EXT_RSPI_FWDM       0x30
UMASK_XSNP_RESP_CORE_RSP_HITFSE     0x41
UMASK_XSNP_RESP_CORE_RSPS_FWDFE     0x42
UMASK_XSNP_RESP_CORE_RSPI_FWDFE     0x44
UMASK_XSNP_RESP_CORE_RSPS_FWDM      0x48
UMASK_XSNP_RESP_CORE_RSPI_FWDM      0x50
UMASK_XSNP_RESP_EVICT_RSP_HITFSE    0x81
UMASK_XSNP_RESP_EVICT_RSPS_FWDFE    0x82
UMASK_XSNP_RESP_EVICT_RSPI_FWDFE    0x84
UMASK_XSNP_RESP_EVICT_RSPS_FWDM     0x88
UMASK_XSNP_RESP_EVICT_RSPI_FWDM     0x90
UMASK_XSNP_RESP_ANY_RSP_HITFSE      0xE1
UMASK_XSNP_RESP_ANY_RSPS_FWDFE      0xE2
UMASK_XSNP_RESP_ANY_RSPI_FWDFE      0xE4
UMASK_XSNP_RESP_ANY_RSPS_FWDM       0xE8

EVENT_ACT_COUNT                     0x01 MBOX
UMASK_ACT_COUNT_RD                  0x01
UMASK_ACT_COUNT_WR                  0x02
UMASK_ACT_COUNT_BYP                 0x08

EVENT_BYP_CMDS                      0xA1 MBOX
UMASK_BYP_CMDS_ACT                  0x01
UMASK_BYP_CMDS_CAS                  0x02
UMASK_BYP_CMDS_PRE                  0x04

EVENT_CAS_COUNT                     0x04 MBOX
UMASK_CAS_COUNT_RD_REG              0x01
UMASK_CAS_COUNT_RD_UNDERFILL        0x02
UMASK_CAS_COUNT_RD                  0x03
UMASK_CAS_COUNT_WR_WMM              0x04
UMASK_CAS_COUNT_WR_RMM              0x08
UMASK_CAS_COUNT_WR                  0x0C
UMASK_CAS_COUNT_RD_WMM              0x10
UMASK_CAS_COUNT_RD_RMM              0x20
UMASK_CAS_COUNT_RD_ISOCH            0x40
UMASK_CAS_COUNT_WR_ISOCH            0x80

EVENT_PMM_RPQ_OCCUPANCY             0xE0 MBOX
UMASK_PMM_RPQ_OCCUPANCY_ALL         0x01

EVENT_PMM_RPQ_INSERTS               0xE3 MBOX
UMASK_PMM_RPQ_INSERTS               0x00

EVENT_PMM_CMD1                      0xEA MBOX
UMASK_PMM_CMD1_ALL                  0x01
UMASK_PMM_CMD1_RD                   0x02
UMASK_PMM_CMD1_WR                   0x04
UMASK_PMM_CMD1_UFILL_RD             0x08

EVENT_PMM_WPQ_OCCUPANCY             0xE4 MBOX
UMASK_PMM_WPQ_OCCUPANCY_ALL         0x01

EVENT_PMM_WPQ_INSERTS               0xE7 MBOX
UMASK_PMM_WPQ_INSERTS               0x00

EVENT_POWER_CHANNEL_PPD             0x85 MBOX
UMASK_POWER_CHANNEL_PPD             0x00

EVENT_POWER_SELF_REFRESH            0x43 MBOX
UMASK_POWER_SELF_REFRESH            0x00

EVENT_PRE_COUNT                     0x02 MBOX
UMASK_PRE_COUNT_PAGE_MISS           0x01
UMASK_PRE_COUNT_RD                  0x04

EVENT_RPQ_INSERTS                   0x10 MBOX
UMASK_RPQ_INSERTS                   0x00

EVENT_RPQ_OCCUPANCY                 0x80 MBOX
UMASK_RPQ_OCCUPANCY                 0x00

EVENT_M_TAGCHK                      0xD3 MBOX
UMASK_M_TAGCHK_HIT                  0x01
UMASK_M_TAGCHK_MISS_CLEAN           0x02
UMASK_M_TAGCHK_MISS_DIRTY           0x04

EVENT_WPQ_INSERTS                   0x20 MBOX
UMASK_WPQ_INSERTS                   0x00

EVENT_WPQ_OCCUPANCY                 0x81 MBOX
UMASK_WPQ_OCCUPANCY                 0x00



EVENT_DRAM_CLOCKTICKS               0x00 MBOX0FIX|MBOX1FIX|MBOX2FIX|MBOX3FIX|MBOX4FIX|MBOX5FIX
UMASK_DRAM_CLOCKTICKS               0x00

EVENT_WBOX_CLOCKTICKS               0x00 WBOX
UMASK_WBOX_CLOCKTICKS               0x00

EVENT_CORE_TRANSITION_CYCLES        0x60 WBOX
UMASK_CORE_TRANSITION_CYCLES        0x00

EVENT_CTS_EVENT0                    0x11 WBOX
UMASK_CTS_EVENT0                    0x00

EVENT_CTS_EVENT1                    0x12 WBOX
UMASK_CTS_EVENT1                    0x00

EVENT_DEMOTIONS                     0x30 WBOX
UMASK_DEMOTIONS                     0x00

EVENT_FIVR_PS_PS0_CYCLES            0x75 WBOX
UMASK_FIVR_PS_PS0_CYCLES            0x00

EVENT_FIVR_PS_PS1_CYCLES            0x76 WBOX
UMASK_FIVR_PS_PS1_CYCLES            0x00

EVENT_FIVR_PS_PS2_CYCLES            0x77 WBOX
UMASK_FIVR_PS_PS2_CYCLES            0x00

EVENT_FIVR_PS_PS3_CYCLES            0x78 WBOX
UMASK_FIVR_PS_PS3_CYCLES            0x00

EVENT_FREQ_MAX_LIMIT_THERMAL_CYCLES 0x04 WBOX
UMASK_FREQ_MAX_LIMIT_THERMAL_CYCLES 0x00

EVENT_FREQ_MAX_POWER_CYCLES         0x05 WBOX
UMASK_FREQ_MAX_POWER_CYCLES         0x00

EVENT_FREQ_MIN_IO_P_CYCLES          0x73 WBOX
UMASK_FREQ_MIN_IO_P_CYCLES          0x00

EVENT_FREQ_TRANS_CYCLES             0x74 WBOX
UMASK_FREQ_TRANS_CYCLES             0x00

EVENT_MCP_PROCHOT_CYCLES            0x06 WBOX
UMASK_MCP_PROCHOT_CYCLES            0x00

EVENT_MEMORY_PHASE_SHEDDING_CYCLES  0x2F WBOX
UMASK_MEMORY_PHASE_SHEDDING_CYCLES  0x00

EVENT_PKG_RESIDENCY_C0_CYCLES       0x2A WBOX
UMASK_PKG_RESIDENCY_C0_CYCLES       0x00

EVENT_PKG_RESIDENCY_C2E_CYCLES      0x2B WBOX
UMASK_PKG_RESIDENCY_C2E_CYCLES      0x00

EVENT_PKG_RESIDENCY_C3_CYCLES       0x2C WBOX
UMASK_PKG_RESIDENCY_C3_CYCLES       0x00

EVENT_PKG_RESIDENCY_C6_CYCLES       0x2D WBOX
UMASK_PKG_RESIDENCY_C6_CYCLES       0x00

EVENT_PMAX_THROTTLED_CYCLES         0x07 WBOX
UMASK_PMAX_THROTTLED_CYCLES         0x00

EVENT_PROCHOT_EXTERNAL_CYCLES       0x0A WBOX
UMASK_PROCHOT_EXTERNAL_CYCLES       0x00

EVENT_PROCHOT_INTERNAL_CYCLES       0x09 WBOX
UMASK_PROCHOT_INTERNAL_CYCLES       0x00

EVENT_TOTAL_TRANSITION_CYCLES       0x72 WBOX
UMASK_TOTAL_TRANSITION_CYCLES       0x00

EVENT_VR_HOT_CYCLES                 0x42 WBOX
UMASK_VR_HOT_CYCLES                 0x00

EVENT_CORES_IN_C3                       0x00 WBOX0FIX
UMASK_CORES_IN_C3                       0x00

EVENT_CORES_IN_C6                       0x00 WBOX1FIX
UMASK_CORES_IN_C6                       0x00

EVENT_CORES_IN_P3                       0x00 WBOX2FIX
UMASK_CORES_IN_P3                       0x00

EVENT_CORES_IN_P6                       0x00 WBOX3FIX
UMASK_CORES_IN_P6                       0x00

EVENT_M2M_CLOCKTICKS                   0x00 M2M
UMASK_M2M_CLOCKTICKS                   0x00

EVENT_BYPASS_M2M_EGRESS             0x22 M2M
UMASK_BYPASS_M2M_EGRESS_TAKEN       0x01
UMASK_BYPASS_M2M_EGRESS_NOT_TAKEN   0x02

EVENT_BYPASS_M2M_INGRESS            0x21 M2M
UMASK_BYPASS_M2M_INGRESS_TAKEN      0x01
UMASK_BYPASS_M2M_INGRESS_NOT_TAKEN  0x02

EVENT_DDRT_RPQ_CYCLES_REG               0x4F M2M
UMASK_DDRT_RPQ_CYCLES_REG_CREDITS_CHN0  0x01
UMASK_DDRT_RPQ_CYCLES_REG_CREDITS_CHN1  0x02
UMASK_DDRT_RPQ_CYCLES_REG_CREDITS_CHN2  0x04
DEFAULT_OPTIONS_DDRT_RPQ_CYCLES_REG_NO_CREDITS_CHN0 EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_DDRT_RPQ_CYCLES_REG_NO_CREDITS_CHN0  0x01
DEFAULT_OPTIONS_DDRT_RPQ_CYCLES_REG_NO_CREDITS_CHN1 EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_DDRT_RPQ_CYCLES_REG_NO_CREDITS_CHN1  0x02
DEFAULT_OPTIONS_DDRT_RPQ_CYCLES_REG_NO_CREDITS_CHN2 EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_DDRT_RPQ_CYCLES_REG_NO_CREDITS_CHN2  0x03

EVENT_DDRT_WPQ_CYCLES_REG               0x51 M2M
UMASK_DDRT_WPQ_CYCLES_REG_CREDITS_CHN0  0x01
UMASK_DDRT_WPQ_CYCLES_REG_CREDITS_CHN1  0x02
UMASK_DDRT_WPQ_CYCLES_REG_CREDITS_CHN2  0x04
DEFAULT_OPTIONS_DDRT_WPQ_CYCLES_REG_NO_CREDITS_CHN0 EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_DDRT_WPQ_CYCLES_REG_NO_CREDITS_CHN0  0x01
DEFAULT_OPTIONS_DDRT_WPQ_CYCLES_REG_NO_CREDITS_CHN1 EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_DDRT_WPQ_CYCLES_REG_NO_CREDITS_CHN1  0x02
DEFAULT_OPTIONS_DDRT_WPQ_CYCLES_REG_NO_CREDITS_CHN2 EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_DDRT_WPQ_CYCLES_REG_NO_CREDITS_CHN2  0x03

EVENT_DIRECT2CORE_NOT_TAKEN_DIRSTATE    0x24 M2M
UMASK_DIRECT2CORE_NOT_TAKEN_DIRSTATE    0x00

EVENT_DIRECT2CORE_TAKEN                 0x24 M2M
UMASK_DIRECT2CORE_TAKEN                 0x00

EVENT_DIRECT2CORE_TXN_OVERRIDE          0x25 M2M
UMASK_DIRECT2CORE_TXN_OVERRIDE          0x00

EVENT_DIRECT2UPI_NOT_TAKEN_CREDITS      0x28 M2M
UMASK_DIRECT2UPI_NOT_TAKEN_CREDITS      0x00

EVENT_DIRECT2UPI_NOT_TAKEN_DIRSTATE     0x27 M2M
UMASK_DIRECT2UPI_NOT_TAKEN_DIRSTATE     0x00

EVENT_DIRECT2UPI_TAKEN                  0x26 M2M
UMASK_DIRECT2UPI_TAKEN                  0x00

EVENT_DIRECT2UPI_TXN_OVERRIDE           0x29 M2M
UMASK_DIRECT2UPI_TXN_OVERRIDE           0x00

EVENT_DIRECTORY_HIT                     0x2A M2M
UMASK_DIRECTORY_HIT_DIRTY_I             0x01
UMASK_DIRECTORY_HIT_DIRTY_S             0x02
UMASK_DIRECTORY_HIT_DIRTY_P             0x04
UMASK_DIRECTORY_HIT_DIRTY_A             0x08
UMASK_DIRECTORY_HIT_CLEAN_I             0x10
UMASK_DIRECTORY_HIT_CLEAN_S             0x20
UMASK_DIRECTORY_HIT_CLEAN_P             0x40
UMASK_DIRECTORY_HIT_CLEAN_A             0x80

EVENT_DIRECTORY_LOOKUP                  0x2D M2M
UMASK_DIRECTORY_LOOKUP_ANY              0x01
UMASK_DIRECTORY_LOOKUP_STATE_I          0x02
UMASK_DIRECTORY_LOOKUP_STATE_S          0x04
UMASK_DIRECTORY_LOOKUP_STATE_A          0x08

EVENT_DIRECTORY_MISS                     0x2B M2M
UMASK_DIRECTORY_MISS_DIRTY_I             0x01
UMASK_DIRECTORY_MISS_DIRTY_S             0x02
UMASK_DIRECTORY_MISS_DIRTY_P             0x04
UMASK_DIRECTORY_MISS_DIRTY_A             0x08
UMASK_DIRECTORY_MISS_CLEAN_I             0x10
UMASK_DIRECTORY_MISS_CLEAN_S             0x20
UMASK_DIRECTORY_MISS_CLEAN_P             0x40
UMASK_DIRECTORY_MISS_CLEAN_A             0x80

EVENT_DIRECTORY_UPDATE                  0x2E M2M
UMASK_DIRECTORY_UPDATE_ANY              0x01
UMASK_DIRECTORY_UPDATE_I2S              0x02
UMASK_DIRECTORY_UPDATE_I2A              0x04
UMASK_DIRECTORY_UPDATE_S2I              0x08
UMASK_DIRECTORY_UPDATE_S2A              0x10
UMASK_DIRECTORY_UPDATE_A2I              0x20
UMASK_DIRECTORY_UPDATE_A2S              0x40

EVENT_IMC_READS                         0x37 M2M
UMASK_IMC_READS_NORMAL                  0x01
UMASK_IMC_READS_ISOCH                   0x02
UMASK_IMC_READS_ALL                     0x04
UMASK_IMC_READS_TO_DDRT                 0x08
UMASK_IMC_READS_TO_PMM                  0x08
UMASK_IMC_READS_FROM_TRANSGRESS         0x10

EVENT_IMC_WRITES                         0x38 M2M
UMASK_IMC_WRITES_FULL                    0x01
UMASK_IMC_WRITES_PARTIAL                 0x02
UMASK_IMC_WRITES_FULL_ISOCH              0x04
UMASK_IMC_WRITES_PARTIAL_ISOCH           0x08
UMASK_IMC_WRITES_ALL                     0x10
UMASK_IMC_WRITES_TO_DDRT                 0x20
UMASK_IMC_WRITES_TO_PMM                  0x20
UMASK_IMC_WRITES_FROM_TRANSGRESS         0x40
UMASK_IMC_WRITES_NI                      0x80

EVENT_PCOMMITS                          0x65 M2M
UMASK_PCOMMITS                          0x00

EVENT_PCOMMIT_COALESCED                 0x66 M2M
UMASK_PCOMMIT_COALESCED                 0x00

EVENT_PKT_MATCH                         0x4C M2M
UMASK_PKT_MATCH_MESH                    0x01
UMASK_PKT_MATCH_MC                      0x02

EVENT_PREFCAM_CYCLES_FULL               0x53 M2M
UMASK_PREFCAM_CYCLES_FULL               0x00

EVENT_PREFCAM_CYCLES_NE                 0x54 M2M
UMASK_PREFCAM_CYCLES_NE                 0x00

EVENT_PREFCAM_DEMAND_PROMOTIONS         0x56 M2M
UMASK_PREFCAM_DEMAND_PROMOTIONS         0x00

EVENT_PREFCAM_INSERTS                   0x57 M2M
UMASK_PREFCAM_INSERTS                   0x00

EVENT_PREFCAM_OCCUPANCY                 0x55 M2M
UMASK_PREFCAM_OCCUPANCY                 0x00

EVENT_RPQ_CYCLES_REG                    0x43 M2M
UMASK_RPQ_CYCLES_REG_CREDITS_CHN0       0x01
UMASK_RPQ_CYCLES_REG_CREDITS_CHN1       0x02
UMASK_RPQ_CYCLES_REG_CREDITS_CHN2       0x04
DEFAULT_OPTIONS_RPQ_CYCLES_REG_NO_CREDITS_CHN0 EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_RPQ_CYCLES_REG_NO_CREDITS_CHN0    0x01
DEFAULT_OPTIONS_RPQ_CYCLES_REG_NO_CREDITS_CHN1 EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_RPQ_CYCLES_REG_NO_CREDITS_CHN1    0x02
DEFAULT_OPTIONS_RPQ_CYCLES_REG_NO_CREDITS_CHN2 EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_RPQ_CYCLES_REG_NO_CREDITS_CHN2    0x04

EVENT_RPQ_CYCLES_SPEC                    0x44 M2M
UMASK_RPQ_CYCLES_SPEC_CREDITS_CHN0       0x01
UMASK_RPQ_CYCLES_SPEC_CREDITS_CHN1       0x02
UMASK_RPQ_CYCLES_SPEC_CREDITS_CHN2       0x04
DEFAULT_OPTIONS_RPQ_CYCLES_SPEC_NO_CREDITS_CHN0 EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_RPQ_CYCLES_SPEC_NO_CREDITS_CHN0    0x01
DEFAULT_OPTIONS_RPQ_CYCLES_SPEC_NO_CREDITS_CHN1 EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_RPQ_CYCLES_SPEC_NO_CREDITS_CHN1    0x02
DEFAULT_OPTIONS_RPQ_CYCLES_SPEC_NO_CREDITS_CHN2 EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_RPQ_CYCLES_SPEC_NO_CREDITS_CHN2    0x04

EVENT_RXC_AD_CYCLES_FULL                0x04 M2M
UMASK_RXC_AD_CYCLES_FULL                0x00

EVENT_RXC_AD_CYCLES_NE                0x03 M2M
UMASK_RXC_AD_CYCLES_NE                0x00

EVENT_RXC_AD_INSERTS                0x01 M2M
UMASK_RXC_AD_INSERTS                0x00

EVENT_RXC_AD_OCCUPANCY                0x02 M2M
UMASK_RXC_AD_OCCUPANCY                0x00

EVENT_RXC_BL_CYCLES_FULL                0x08 M2M
UMASK_RXC_BL_CYCLES_FULL                0x00

EVENT_RXC_BL_CYCLES_NE                0x07 M2M
UMASK_RXC_BL_CYCLES_NE                0x00

EVENT_RXC_BL_INSERTS                0x05 M2M
UMASK_RXC_BL_INSERTS                0x00

EVENT_RXC_BL_OCCUPANCY                0x06 M2M
UMASK_RXC_BL_OCCUPANCY                0x00

EVENT_SCOREBOARD_AD_RETRY_ACCEPTS       0x33 M2M
UMASK_SCOREBOARD_AD_RETRY_ACCEPTS       0x00

EVENT_SCOREBOARD_AD_RETRY_REJECTS       0x34 M2M
UMASK_SCOREBOARD_AD_RETRY_REJECTS       0x00

EVENT_SCOREBOARD_BL_RETRY_ACCEPTS       0x35 M2M
UMASK_SCOREBOARD_BL_RETRY_ACCEPTS       0x00

EVENT_SCOREBOARD_BL_RETRY_REJECTS       0x36 M2M
UMASK_SCOREBOARD_BL_RETRY_REJECTS       0x00

EVENT_SCOREBOARD_CYCLES_REG                    0x59 M2M
UMASK_SCOREBOARD_CYCLES_REG_CREDITS_CHN0       0x01
UMASK_SCOREBOARD_CYCLES_REG_CREDITS_CHN1       0x02
UMASK_SCOREBOARD_CYCLES_REG_CREDITS_CHN2       0x04
DEFAULT_OPTIONS_SCOREBOARD_CYCLES_REG_NO_CREDITS_CHN0 EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_SCOREBOARD_CYCLES_REG_NO_CREDITS_CHN0    0x01
DEFAULT_OPTIONS_SCOREBOARD_CYCLES_REG_NO_CREDITS_CHN1 EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_SCOREBOARD_CYCLES_REG_NO_CREDITS_CHN1    0x02
DEFAULT_OPTIONS_SCOREBOARD_CYCLES_REG_NO_CREDITS_CHN2 EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_SCOREBOARD_CYCLES_REG_NO_CREDITS_CHN2    0x04

EVENT_SCOREBOARD_RD_RETRY_ACCEPTS       0x2F M2M
UMASK_SCOREBOARD_RD_RETRY_ACCEPTS       0x00

EVENT_SCOREBOARD_RD_RETRY_REJECTS       0x30 M2M
UMASK_SCOREBOARD_RD_RETRY_REJECTS       0x00

EVENT_SCOREBOARD_WR_RETRY_ACCEPTS       0x31 M2M
UMASK_SCOREBOARD_WR_RETRY_ACCEPTS       0x00

EVENT_SCOREBOARD_WR_RETRY_REJECTS       0x32 M2M
UMASK_SCOREBOARD_WR_RETRY_REJECTS       0x00

EVENT_TAG_HIT                           0x2C M2M
UMASK_TAG_HIT_NM_DRD_HIT_CLEAN          0x01
UMASK_TAG_HIT_NM_DRD_HIT_DIRTY          0x02
UMASK_TAG_HIT_NM_UFILL_HIT_CLEAN        0x04
UMASK_TAG_HIT_NM_UFILL_HIT_DIRTY        0x08

EVENT_TGR_AD_CREDITS                    0x41 M2M
UMASK_TGR_AD_CREDITS                    0x00

EVENT_TGR_BL_CREDITS                    0x42 M2M
UMASK_TGR_BL_CREDITS                    0x00

EVENT_TRACKER_CYCLES_FULL               0x45 M2M
UMASK_TRACKER_CYCLES_FULL_CHN0          0x01
UMASK_TRACKER_CYCLES_FULL_CHN1          0x02
UMASK_TRACKER_CYCLES_FULL_CHN2          0x04
UMASK_TRACKER_CYCLES_FULL_ALL           0x07

EVENT_TRACKER_CYCLES_NE                 0x46 M2M
UMASK_TRACKER_CYCLES_NE_CHN0            0x01
UMASK_TRACKER_CYCLES_NE_CHN1            0x02
UMASK_TRACKER_CYCLES_NE_CHN2            0x04
UMASK_TRACKER_CYCLES_NE_ALL             0x07

EVENT_TRACKER_CYCLES_INSERTS               0x47 M2M
UMASK_TRACKER_CYCLES_INSERTS_CHN0          0x01
UMASK_TRACKER_CYCLES_INSERTS_CHN1          0x02
UMASK_TRACKER_CYCLES_INSERTS_CHN2          0x04
UMASK_TRACKER_CYCLES_INSERTS_ALL           0x07

EVENT_TRACKER_PENDING_OCCUPANCY         0x48 M2M
UMASK_TRACKER_PENDING_OCCUPANCY         0x00

EVENT_TXC_AD_CREDITS_ACQUIRED           0x0D M2M
UMASK_TXC_AD_CREDITS_ACQUIRED           0x00

EVENT_TXC_AD_CREDITS_OCCUPANCY          0x0E M2M
UMASK_TXC_AD_CREDITS_OCCUPANCY          0x00

EVENT_TXC_AD_CYCLES_FULL                0x0C M2M
UMASK_TXC_AD_CYCLES_FULL                0x00

EVENT_TXC_AD_CYCLES_NE                  0x0B M2M
UMASK_TXC_AD_CYCLES_NE                  0x00

EVENT_TXC_AD_INSERTS                    0x09 M2M
UMASK_TXC_AD_INSERTS                    0x00

EVENT_TXC_AD_NO_CREDIT_CYCLES           0x0F M2M
UMASK_TXC_AD_NO_CREDIT_CYCLES           0x00

EVENT_TXC_AD_NO_CREDIT_STALLED          0x10 M2M
UMASK_TXC_AD_NO_CREDIT_STALLED          0x00

EVENT_TXC_AD_OCCUPANCY                  0x0A M2M
UMASK_TXC_AD_OCCUPANCY                  0x00

EVENT_TXC_AK                            0x39 M2M
UMASK_TXC_AK_NDR                        0x01
UMASK_TXC_AK_CRD_CBO                    0x02

EVENT_TXC_AK_CREDITS_ACQUIRED           0x1D M2M
UMASK_TXC_AK_CREDITS_ACQUIRED_CMS0      0x01
UMASK_TXC_AK_CREDITS_ACQUIRED_CMS1      0x02
UMASK_TXC_AK_CREDITS_ACQUIRED_ALL       0x03

EVENT_TXC_AK_CREDITS_OCCUPANCY          0x1E M2M
UMASK_TXC_AK_CREDITS_OCCUPANCY_CMS0     0x01
UMASK_TXC_AK_CREDITS_OCCUPANCY_CMS1     0x02
UMASK_TXC_AK_CREDITS_OCCUPANCY_ALL      0x03

EVENT_TXC_AK_CYCLES_FULL                0x14 M2M
UMASK_TXC_AK_CYCLES_FULL_CMS0           0x01
UMASK_TXC_AK_CYCLES_FULL_CMS1           0x02
UMASK_TXC_AK_CYCLES_FULL_ALL            0x03
UMASK_TXC_AK_CYCLES_FULL_PCOMMIT        0x04
UMASK_TXC_AK_CYCLES_FULL_RDCRD0         0x08
UMASK_TXC_AK_CYCLES_FULL_WRCRD0         0x10
UMASK_TXC_AK_CYCLES_FULL_WRCMP0         0x20
UMASK_TXC_AK_CYCLES_FULL_RDCRD1         0x88
UMASK_TXC_AK_CYCLES_FULL_WRCRD1         0x90
UMASK_TXC_AK_CYCLES_FULL_WRCMP1         0xA0

EVENT_TXC_AK_CYCLES_NE                  0x13 M2M
UMASK_TXC_AK_CYCLES_NE_CMS0             0x01
UMASK_TXC_AK_CYCLES_NE_CMS1             0x02
UMASK_TXC_AK_CYCLES_NE_ALL              0x03
UMASK_TXC_AK_CYCLES_NE_PCOMMIT          0x04
UMASK_TXC_AK_CYCLES_NE_RDCRD            0x08
UMASK_TXC_AK_CYCLES_NE_WRCRD            0x10
UMASK_TXC_AK_CYCLES_NE_WRCMP            0x20

EVENT_TXC_AK_INSERTS                    0x11 M2M
UMASK_TXC_AK_INSERTS_CMS0               0x01
UMASK_TXC_AK_INSERTS_CMS1               0x02
UMASK_TXC_AK_INSERTS_ALL                0x03
UMASK_TXC_AK_INSERTS_WRCRD              0x04
UMASK_TXC_AK_INSERTS_RDCRD              0x04
UMASK_TXC_AK_INSERTS_WRCMP              0x08
UMASK_TXC_AK_INSERTS_PREF_RD_CAM_HIT    0x10

EVENT_TXC_AK_NO_CREDIT_CYCLES           0x1F M2M
UMASK_TXC_AK_NO_CREDIT_CYCLES_CMS0      0x01
UMASK_TXC_AK_NO_CREDIT_CYCLES_CMS1      0x02
UMASK_TXC_AK_NO_CREDIT_CYCLES_ALL       0x03

EVENT_TXC_AK_NO_CREDIT_STALLED          0x20 M2M
UMASK_TXC_AK_NO_CREDIT_STALLED_CMS0     0x01
UMASK_TXC_AK_NO_CREDIT_STALLED_CMS1     0x02
UMASK_TXC_AK_NO_CREDIT_STALLED_ALL      0x03

EVENT_TXC_AK_OCCUPANCY                  0x12 M2M
UMASK_TXC_AK_OCCUPANCY_CMS0             0x01
UMASK_TXC_AK_OCCUPANCY_CMS1             0x02
UMASK_TXC_AK_OCCUPANCY_ALL              0x03
UMASK_TXC_AK_OCCUPANCY_PCOMMIT          0x04
UMASK_TXC_AK_OCCUPANCY_RDCRD            0x08
UMASK_TXC_AK_OCCUPANCY_WRCRD            0x10
UMASK_TXC_AK_OCCUPANCY_WRCMP            0x20

EVENT_TXC_AK_SIDEBAND                   0x6B M2M
UMASK_TXC_AK_SIDEBAND_RD                0x01
UMASK_TXC_AK_SIDEBAND_WR                0x02

EVENT_TXC_BL                            0x40 M2M
UMASK_TXC_BL_DRS_CACHE                  0x01
UMASK_TXC_BL_DRS_CORE                   0x02
UMASK_TXC_BL_DRS_UPI                    0x04

EVENT_TXC_BL_CREDITS_ACQUIRED           0x19 M2M
UMASK_TXC_BL_CREDITS_ACQUIRED_CMS0      0x01
UMASK_TXC_BL_CREDITS_ACQUIRED_CMS1      0x02
UMASK_TXC_BL_CREDITS_ACQUIRED_ALL       0x03

EVENT_TXC_BL_CREDITS_OCCUPANCY          0x1E M2M
UMASK_TXC_BL_CREDITS_OCCUPANCY_CMS0     0x01
UMASK_TXC_BL_CREDITS_OCCUPANCY_CMS1     0x02
UMASK_TXC_BL_CREDITS_OCCUPANCY_ALL      0x03

EVENT_TXC_BL_CYCLES_FULL                0x18 M2M
UMASK_TXC_BL_CYCLES_FULL_CMS0           0x01
UMASK_TXC_BL_CYCLES_FULL_CMS1           0x02
UMASK_TXC_BL_CYCLES_FULL_ALL            0x03

EVENT_TXC_BL_CYCLES_NE                  0x17 M2M
UMASK_TXC_BL_CYCLES_NE_CMS0             0x01
UMASK_TXC_BL_CYCLES_NE_CMS1             0x02
UMASK_TXC_BL_CYCLES_NE_ALL              0x03

EVENT_TXC_BL_INSERTS                    0x15 M2M
UMASK_TXC_BL_INSERTS_CMS0               0x01
UMASK_TXC_BL_INSERTS_CMS1               0x02
UMASK_TXC_BL_INSERTS_ALL                0x03

EVENT_TXC_BL_NO_CREDIT_CYCLES           0x1B M2M
UMASK_TXC_BL_NO_CREDIT_CYCLES_CMS0      0x01
UMASK_TXC_BL_NO_CREDIT_CYCLES_CMS1      0x02
UMASK_TXC_BL_NO_CREDIT_CYCLES_ALL       0x03

EVENT_TXC_BL_NO_CREDIT_STALLED          0x1C M2M
UMASK_TXC_BL_NO_CREDIT_STALLED_CMS0     0x01
UMASK_TXC_BL_NO_CREDIT_STALLED_CMS1     0x02
UMASK_TXC_BL_NO_CREDIT_STALLED_ALL      0x03

EVENT_TXC_BL_OCCUPANCY                  0x16 M2M
UMASK_TXC_BL_OCCUPANCY_CMS0             0x01
UMASK_TXC_BL_OCCUPANCY_CMS1             0x02
UMASK_TXC_BL_OCCUPANCY_ALL              0x03

EVENT_WPQ_CYCLES_REG                    0x4D M2M
UMASK_WPQ_CYCLES_REG_CREDITS_CHN0       0x01
UMASK_WPQ_CYCLES_REG_CREDITS_CHN1       0x02
UMASK_WPQ_CYCLES_REG_CREDITS_CHN2       0x04
UMASK_WPQ_CYCLES_REG_CREDITS_ALL        0x07
DEFAULT_OPTIONS_WPQ_CYCLES_REG_NO_CREDITS_CHN0 EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_WPQ_CYCLES_REG_NO_CREDITS_CHN0    0x01
DEFAULT_OPTIONS_WPQ_CYCLES_REG_NO_CREDITS_CHN1 EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_WPQ_CYCLES_REG_NO_CREDITS_CHN1    0x02
DEFAULT_OPTIONS_WPQ_CYCLES_REG_NO_CREDITS_CHN2 EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_WPQ_CYCLES_REG_NO_CREDITS_CHN2    0x04
DEFAULT_OPTIONS_WPQ_CYCLES_REG_NO_CREDITS_ALL EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_WPQ_CYCLES_REG_NO_CREDITS_ALL     0x07

EVENT_WPQ_CYCLES_SPEC                    0x4E M2M
UMASK_WPQ_CYCLES_SPEC_CREDITS_CHN0       0x01
UMASK_WPQ_CYCLES_SPEC_CREDITS_CHN1       0x02
UMASK_WPQ_CYCLES_SPEC_CREDITS_CHN2       0x04
UMASK_WPQ_CYCLES_SPEC_CREDITS_ALL        0x07
DEFAULT_OPTIONS_WPQ_CYCLES_SPEC_NO_CREDITS_CHN0 EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_WPQ_CYCLES_SPEC_NO_CREDITS_CHN0    0x01
DEFAULT_OPTIONS_WPQ_CYCLES_SPEC_NO_CREDITS_CHN1 EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_WPQ_CYCLES_SPEC_NO_CREDITS_CHN1    0x02
DEFAULT_OPTIONS_WPQ_CYCLES_SPEC_NO_CREDITS_CHN2 EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_WPQ_CYCLES_SPEC_NO_CREDITS_CHN2    0x04
DEFAULT_OPTIONS_WPQ_CYCLES_SPEC_NO_CREDITS_ALL EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=1
UMASK_WPQ_CYCLES_SPEC_NO_CREDITS_ALL     0x07

EVENT_WRITE_TRACKER_CYCLES_FULL         0x4A M2M
UMASK_WRITE_TRACKER_CYCLES_FULL_CH0     0x01
UMASK_WRITE_TRACKER_CYCLES_FULL_CH1     0x02
UMASK_WRITE_TRACKER_CYCLES_FULL_CH2     0x04
UMASK_WRITE_TRACKER_CYCLES_FULL_ALL     0x07

EVENT_WRITE_TRACKER_CYCLES_NE         0x4B M2M
UMASK_WRITE_TRACKER_CYCLES_NE_CH0     0x01
UMASK_WRITE_TRACKER_CYCLES_NE_CH1     0x02
UMASK_WRITE_TRACKER_CYCLES_NE_CH2     0x04
UMASK_WRITE_TRACKER_CYCLES_NE_ALL     0x07

EVENT_WRITE_TRACKER_INSERTS         0x61 M2M
UMASK_WRITE_TRACKER_INSERTS_CH0     0x01
UMASK_WRITE_TRACKER_INSERTS_CH1     0x02
UMASK_WRITE_TRACKER_INSERTS_CH2     0x04
UMASK_WRITE_TRACKER_INSERTS_ALL     0x07

EVENT_WRITE_TRACKER_OCCUPANCY         0x60 M2M
UMASK_WRITE_TRACKER_OCCUPANCY_CH0     0x01
UMASK_WRITE_TRACKER_OCCUPANCY_CH1     0x02
UMASK_WRITE_TRACKER_OCCUPANCY_CH2     0x04
UMASK_WRITE_TRACKER_OCCUPANCY_ALL     0x07

EVENT_SBOX_CLOCKTICKS               0x01 SBOX
UMASK_SBOX_CLOCKTICKS               0x00

EVENT_DIRECT_ATTEMPTS               0x12 SBOX
UMASK_DIRECT_ATTEMPTS_D2C           0x01
UMASK_DIRECT_ATTEMPTS_D2K           0x02

EVENT_FLOWQ_NO_VNA_CRD              0x18 SBOX|CBOX|PBOX
UMASK_FLOWQ_NO_VNA_CRD_AD_VNA_EQ0   0x01
UMASK_FLOWQ_NO_VNA_CRD_AD_VNA_EQ1   0x02
UMASK_FLOWQ_NO_VNA_CRD_AD_VNA_EQ2   0x04
UMASK_FLOWQ_NO_VNA_CRD_BL_VNA_EQ0   0x08
UMASK_FLOWQ_NO_VNA_CRD_AK_VNA_EQ0   0x10
UMASK_FLOWQ_NO_VNA_CRD_AK_VNA_EQ1   0x20
UMASK_FLOWQ_NO_VNA_CRD_AK_VNA_EQ2   0x40
UMASK_FLOWQ_NO_VNA_CRD_AK_VNA_EQ3   0x80

EVENT_L1_POWER_CYCLES               0x21 SBOX
UMASK_L1_POWER_CYCLES               0x00

EVENT_M3_BYP_BLOCKED                    0x14 SBOX
UMASK_M3_BYP_BLOCKED_FLOWQ_AD_VNA_LE2   0x01
UMASK_M3_BYP_BLOCKED_FLOWQ_BL_VNA_EQ0   0x02
UMASK_M3_BYP_BLOCKED_FLOWQ_AK_VNA_LE3   0x04
UMASK_M3_BYP_BLOCKED_BGF_CRD            0x08
UMASK_M3_BYP_BLOCKED_GV_BLOCK           0x10

EVENT_M3_CRD_RETURN_BLOCKED         0x16 SBOX
UMASK_M3_CRD_RETURN_BLOCKED         0x00

EVENT_M3_RXQ_BLOCKED                    0x15 SBOX
UMASK_M3_RXQ_BLOCKED_FLOWQ_AD_VNA_LE2   0x01
UMASK_M3_RXQ_BLOCKED_FLOWQ_AD_VNA_BTW_2_THRESH 0x02
UMASK_M3_RXQ_BLOCKED_FLOWQ_BL_VNA_EQ0   0x04
UMASK_M3_RXQ_BLOCKED_FLOWQ_BL_VNA_BTW_0_THRESH  0x08
UMASK_M3_RXQ_BLOCKED_FLOWQ_AK_VNA_LE3   0x10
UMASK_M3_RXQ_BLOCKED_BGF_CRD            0x20
UMASK_M3_RXQ_BLOCKED_GV_BLOCK           0x40

EVENT_PHY_INIT_CYCLES                   0x20 SBOX
UMASK_PHY_INIT_CYCLES                   0x00

EVENT_POWER_L1_NACK                     0x23 SBOX
UMASK_POWER_L1_NACK                     0x00

EVENT_POWER_L1_REQ                      0x22 SBOX
UMASK_POWER_L1_REQ                      0x00

EVENT_REQ_SLOT2_FROM_M3                 0x46 SBOX
UMASK_REQ_SLOT2_FROM_M3_VNA             0x01
UMASK_REQ_SLOT2_FROM_M3_VN0             0x02
UMASK_REQ_SLOT2_FROM_M3_VN1             0x04
UMASK_REQ_SLOT2_FROM_M3_ACK             0x08

EVENT_RXL0P_POWER_CYCLES                0x25 SBOX
UMASK_RXL0P_POWER_CYCLES                0x00

EVENT_RXL0P_POWER_TRANSITION_COUNT      0x25 SBOX
DEFAULT_OPTIONS_RXL0P_POWER_TRANSITION_COUNT EVENT_OPTION_EDGE=0x01
UMASK_RXL0P_POWER_TRANSITION_COUNT      0x00

EVENT_RXL0_POWER_CYCLES                 0x24 SBOX
UMASK_RXL0_POWER_CYCLES                 0x00

EVENT_RXL_BASIC_HDR_MATCH               0x05 SBOX
UMASK_RXL_BASIC_HDR_MATCH_REQ           0x08 0x00 0x00
UMASK_RXL_BASIC_HDR_MATCH_REQ_OPC       0x08 0x00 0x01
UMASK_RXL_BASIC_HDR_MATCH_SNP           0x09 0x00 0x00
UMASK_RXL_BASIC_HDR_MATCH_SNP_OPC       0x09 0x00 0x01
UMASK_RXL_BASIC_HDR_MATCH_RSP_NODATA    0x0A 0x00 0x00
UMASK_RXL_BASIC_HDR_MATCH_RSP_NODATA_OPC 0x0A 0x00 0x01
UMASK_RXL_BASIC_HDR_MATCH_RSP_DATA      0x0C 0x00 0x00
UMASK_RXL_BASIC_HDR_MATCH_RSP_DATA_OPC  0x0C 0x00 0x01
UMASK_RXL_BASIC_HDR_MATCH_WB            0x0D 0x00 0x00
UMASK_RXL_BASIC_HDR_MATCH_WB_OPC        0x0D 0x00 0x01
UMASK_RXL_BASIC_HDR_MATCH_NCB           0x0E 0x00 0x00
UMASK_RXL_BASIC_HDR_MATCH_NCB_OPC       0x0E 0x00 0x01
UMASK_RXL_BASIC_HDR_MATCH_NCS           0x0F 0x00 0x00
UMASK_RXL_BASIC_HDR_MATCH_NCS_OPC       0x0F 0x00 0x01

EVENT_RXL_BYPASSED                      0x31 SBOX
UMASK_RXL_BYPASSED_SLOT0                0x01
UMASK_RXL_BYPASSED_SLOT1                0x02
UMASK_RXL_BYPASSED_SLOT2                0x04

EVENT_RXL_CREDITS_CONSUMED_VN0          0x39 SBOX
UMASK_RXL_CREDITS_CONSUMED_VN0          0x00

EVENT_RXL_CREDITS_CONSUMED_VN1          0x3A SBOX
UMASK_RXL_CREDITS_CONSUMED_VN1          0x00

EVENT_RXL_CREDITS_CONSUMED_VNA          0x38 SBOX
UMASK_RXL_CREDITS_CONSUMED_VNA          0x00

EVENT_RXL_FLITS                         0x03 SBOX
UMASK_RXL_FLITS_SLOT0                   0x01
UMASK_RXL_FLITS_SLOT1                   0x02
UMASK_RXL_FLITS_SLOT2                   0x04
UMASK_RXL_FLITS_DATA                    0x08
UMASK_RXL_FLITS_ALL_DATA                0x0F
UMASK_RXL_FLITS_LLCRD                   0x10
UMASK_RXL_FLITS_NULL                    0x20
UMASK_RXL_FLITS_LLCTRL                  0x40
UMASK_RXL_FLITS_IDLE                    0x47
UMASK_RXL_FLITS_PROTHDR                 0x80
UMASK_RXL_FLITS_NON_DATA                0xB7

EVENT_RXL_INSERTS                       0x30 SBOX
UMASK_RXL_INSERTS                       0x00

EVENT_RXL_OCCUPANCY                      0x32 SBOX
UMASK_RXL_OCCUPANCY_SLOT0                0x01
UMASK_RXL_OCCUPANCY_SLOT1                0x02
UMASK_RXL_OCCUPANCY_SLOT2                0x04

EVENT_RXL_SLOT_BYPASS                   0x33 SBOX
UMASK_RXL_SLOT_BYPASS_S0_RXQ1           0x01
UMASK_RXL_SLOT_BYPASS_S0_RXQ2           0x02
UMASK_RXL_SLOT_BYPASS_S1_RXQ0           0x04
UMASK_RXL_SLOT_BYPASS_S1_RXQ2           0x08
UMASK_RXL_SLOT_BYPASS_S2_RXQ0           0x10
UMASK_RXL_SLOT_BYPASS_S2_RXQ1           0x20

EVENT_TXL0P_CLK_ACTIVE                  0x2A SBOX
UMASK_TXL0P_CLK_ACTIVE_CFG_CTL          0x01
UMASK_TXL0P_CLK_ACTIVE_RXQ              0x02
UMASK_TXL0P_CLK_ACTIVE_RXQ_BYPASS       0x04
UMASK_TXL0P_CLK_ACTIVE_RXQ_CRED         0x08
UMASK_TXL0P_CLK_ACTIVE_TXQ              0x10
UMASK_TXL0P_CLK_ACTIVE_RETRY            0x20
UMASK_TXL0P_CLK_ACTIVE_DFX              0x40
UMASK_TXL0P_CLK_ACTIVE_SPARE            0x80

EVENT_TXL0P_POWER_CYCLES                0x27 SBOX
UMASK_TXL0P_POWER_CYCLES                0x00

EVENT_TXL0P_POWER_TRANSITION_COUNT      0x27 SBOX
DEFAULT_OPTIONS_TXL0P_POWER_TRANSITION_COUNT EVENT_OPTION_EDGE=0x01
UMASK_TXL0P_POWER_TRANSITION_COUNT      0x00

EVENT_TXL0P_POWER_CYCLES_LL_ENTER       0x28 SBOX
UMASK_TXL0P_POWER_CYCLES_LL_ENTER       0x00

EVENT_TXL0P_POWER_CYCLES_M3_EXIT        0x29 SBOX
UMASK_TXL0P_POWER_CYCLES_M3_EXIT        0x00

EVENT_TXL0_POWER_CYCLES                 0x26 SBOX
UMASK_TXL0_POWER_CYCLES                 0x00

EVENT_TXL_BASIC_HDR_MATCH               0x04 SBOX
UMASK_TXL_BASIC_HDR_MATCH_REQ           0x08 0x00 0x00
UMASK_TXL_BASIC_HDR_MATCH_REQ_OPC       0x08 0x00 0x01
UMASK_TXL_BASIC_HDR_MATCH_SNP           0x09 0x00 0x00
UMASK_TXL_BASIC_HDR_MATCH_SNP_OPC       0x09 0x00 0x01
UMASK_TXL_BASIC_HDR_MATCH_RSP_NODATA    0x0A 0x00 0x00
UMASK_TXL_BASIC_HDR_MATCH_RSP_NODATA_OPC 0x0A 0x00 0x01
UMASK_TXL_BASIC_HDR_MATCH_RSP_DATA      0x0C 0x00 0x00
UMASK_TXL_BASIC_HDR_MATCH_RSP_DATA_OPC  0x0C 0x00 0x01
UMASK_TXL_BASIC_HDR_MATCH_WB            0x0D 0x00 0x00
UMASK_TXL_BASIC_HDR_MATCH_WB_OPC        0x0D 0x00 0x01
UMASK_TXL_BASIC_HDR_MATCH_NCB           0x0E 0x00 0x00
UMASK_TXL_BASIC_HDR_MATCH_NCB_OPC       0x0E 0x00 0x01
UMASK_TXL_BASIC_HDR_MATCH_NCS           0x0F 0x00 0x00
UMASK_TXL_BASIC_HDR_MATCH_NCS_OPC       0x0F 0x00 0x01

EVENT_TXL_BYPASSED                      0x41 SBOX
UMASK_TXL_BYPASSED                      0x00

EVENT_TXL_FLITS                         0x02 SBOX
UMASK_TXL_FLITS_SLOT0                   0x01
UMASK_TXL_FLITS_SLOT1                   0x02
UMASK_TXL_FLITS_SLOT2                   0x04
UMASK_TXL_FLITS_DATA                    0x08
UMASK_TXL_FLITS_ALL_DATA                0x0F
UMASK_TXL_FLITS_LLCRD                   0x10
UMASK_TXL_FLITS_NULL                    0x20
UMASK_TXL_FLITS_LLCTRL                  0x40
UMASK_TXL_FLITS_IDLE                    0x47
UMASK_TXL_FLITS_PROTHDR                 0x80
UMASK_TXL_FLITS_NON_DATA                0xB7

EVENT_TXL_INSERTS                       0x40 SBOX
UMASK_TXL_INSERTS                       0x00

EVENT_TXL_OCCUPANCY                      0x42 SBOX
UMASK_TXL_OCCUPANCY_SLOT0                0x01
UMASK_TXL_OCCUPANCY_SLOT1                0x02
UMASK_TXL_OCCUPANCY_SLOT2                0x04

EVENT_VNA_CREDIT_RETURN_BLOCKED_VN01    0x45 SBOX
UMASK_VNA_CREDIT_RETURN_BLOCKED_VN01    0x00

EVENT_VNA_CREDIT_RETURN_OCCUPANCY       0x44 SBOX
UMASK_VNA_CREDIT_RETURN_OCCUPANCY       0x00

EVENT_PBOX_CLOCKTICKS                   0x01 PBOX
UMASK_PBOX_CLOCKTICKS                   0x00

EVENT_IIO_CREDITS_ACQUIRED              0x33 PBOX
UMASK_IIO_CREDITS_ACQUIRED_DRS_0        0x01
UMASK_IIO_CREDITS_ACQUIRED_DRS_1        0x02
UMASK_IIO_CREDITS_ACQUIRED_NCB_0        0x04
UMASK_IIO_CREDITS_ACQUIRED_NCB_1        0x08
UMASK_IIO_CREDITS_ACQUIRED_NCS_0        0x10
UMASK_IIO_CREDITS_ACQUIRED_NCS_1        0x20

EVENT_IIO_CREDITS_REJECT                0x34 PBOX
UMASK_IIO_CREDITS_REJECT_DRS            0x08
UMASK_IIO_CREDITS_REJECT_NCB            0x10
UMASK_IIO_CREDITS_REJECT_NCS            0x20

EVENT_IIO_CREDITS_USED              0x32 PBOX
UMASK_IIO_CREDITS_USED_DRS_0        0x01
UMASK_IIO_CREDITS_USED_DRS_1        0x02
UMASK_IIO_CREDITS_USED_NCB_0        0x04
UMASK_IIO_CREDITS_USED_NCB_1        0x08
UMASK_IIO_CREDITS_USED_NCS_0        0x10
UMASK_IIO_CREDITS_USED_NCS_1        0x20

EVENT_RXC_CYCLES_NE                 0x10 PBOX
UMASK_RXC_CYCLES_NE_CBO_IDI         0x01
UMASK_RXC_CYCLES_NE_CBO_NCB         0x02
UMASK_RXC_CYCLES_NE_CBO_NCS         0x04
UMASK_RXC_CYCLES_NE_QPI_INCS        0x10
UMASK_RXC_CYCLES_NE_IIO_INCB        0x20
UMASK_RXC_CYCLES_NE_IIO_INCS        0x40
UMASK_RXC_CYCLES_NE_ALL             0x80

EVENT_RXC_INSERTS                 0x11 PBOX
UMASK_RXC_INSERTS_CBO_IDI         0x01
UMASK_RXC_INSERTS_CBO_NCB         0x02
UMASK_RXC_INSERTS_CBO_NCS         0x04
UMASK_RXC_INSERTS_QPI_INCS        0x10
UMASK_RXC_INSERTS_IIO_INCB        0x20
UMASK_RXC_INSERTS_IIO_INCS        0x40
UMASK_RXC_INSERTS_ALL             0x80

EVENT_RXC_OCCUPANCY                 0x13 PBOX0C0|PBOX1C0|PBOX2C0|PBOX3C0
UMASK_RXC_OCCUPANCY_CBO_IDI         0x01
UMASK_RXC_OCCUPANCY_CBO_NCB         0x02
UMASK_RXC_OCCUPANCY_CBO_NCS         0x04
UMASK_RXC_OCCUPANCY_QPI_INCS        0x10
UMASK_RXC_OCCUPANCY_IIO_INCB        0x20
UMASK_RXC_OCCUPANCY_IIO_INCS        0x40
UMASK_RXC_OCCUPANCY_ALL             0x80

EVENT_TXC_CREDITS               0x2D PBOX0C0|PBOX1C0|PBOX2C0|PBOX3C0|PBOX0C1|PBOX1C1|PBOX2C1|PBOX3C1
UMASK_TXC_CREDITS_PRQ_0         0x01
UMASK_TXC_CREDITS_PRQ_1         0x02
UMASK_TXC_CREDITS_ISOCH_0       0x04
UMASK_TXC_CREDITS_ISOCH_1       0x08

EVENT_TXC_CYCLES_FULL           0x25 PBOX
UMASK_TXC_CYCLES_FULL_AD_0      0x01
UMASK_TXC_CYCLES_FULL_AK_0      0x02
UMASK_TXC_CYCLES_FULL_BL_0      0x04
UMASK_TXC_CYCLES_FULL_AD_1      0x08
UMASK_TXC_CYCLES_FULL_AK_1      0x10
UMASK_TXC_CYCLES_FULL_BL_1      0x20

EVENT_TXC_CYCLES_NE           0x23 PBOX
UMASK_TXC_CYCLES_NE_AD_0      0x01
UMASK_TXC_CYCLES_NE_AK_0      0x02
UMASK_TXC_CYCLES_NE_BL_0      0x04
UMASK_TXC_CYCLES_NE_AD_1      0x08
UMASK_TXC_CYCLES_NE_AK_1      0x10
UMASK_TXC_CYCLES_NE_BL_1      0x20

EVENT_TXC_INSERTS               0x24 PBOX
UMASK_TXC_INSERTS_AD_0          0x01
UMASK_TXC_INSERTS_AK_0          0x02
UMASK_TXC_INSERTS_BL_0          0x04
UMASK_TXC_INSERTS_AK_CRD_0      0x08
UMASK_TXC_INSERTS_AD_1          0x10
UMASK_TXC_INSERTS_AK_1          0x20
UMASK_TXC_INSERTS_BL_1          0x40
UMASK_TXC_INSERTS_AK_CRD_1      0x80

EVENT_TXC_OCCUPANCY             0x27 PBOX0C0|PBOX1C0|PBOX2C0|PBOX3C0
UMASK_TXC_OCCUPANCY_AD_0        0x01
UMASK_TXC_OCCUPANCY_AK_0        0x02
UMASK_TXC_OCCUPANCY_BL_0        0x04
UMASK_TXC_OCCUPANCY_AD_1        0x08
UMASK_TXC_OCCUPANCY_AK_1        0x10
UMASK_TXC_OCCUPANCY_BL_1        0x20

EVENT_RBOX_CLOCKTICKS           0x01 RBOX
UMASK_RBOX_CLOCKTICKS           0x00

EVENT_CHA_AD_CREDITS_EMPTY      0x22 RBOX
UMASK_CHA_AD_CREDITS_EMPTY_VNA  0x01
UMASK_CHA_AD_CREDITS_EMPTY_WB   0x02
UMASK_CHA_AD_CREDITS_EMPTY_REQ  0x04
UMASK_CHA_AD_CREDITS_EMPTY_SNP  0x08

EVENT_D2C_SENT                  0x2B RBOX
UMASK_D2C_SENT                  0x00

EVENT_D2U_SENT                  0x2A RBOX
UMASK_D2U_SENT                  0x00

EVENT_M2_BL_CREDITS_EMPTY                   0x23 RBOX
UMASK_M2_BL_CREDITS_EMPTY_IIO0_IIO1_NCB     0x01
UMASK_M2_BL_CREDITS_EMPTY_IIO2_NCB          0x02
UMASK_M2_BL_CREDITS_EMPTY_IIO3_NCB          0x04
UMASK_M2_BL_CREDITS_EMPTY_IIO4_NCB          0x08
UMASK_M2_BL_CREDITS_EMPTY_IIO5_NCB          0x10
UMASK_M2_BL_CREDITS_EMPTY_NCS               0x20
UMASK_M2_BL_CREDITS_EMPTY_NCS_SEL           0x40

EVENT_MULTI_SLOT_RCVD               0x3E RBOX
UMASK_MULTI_SLOT_RCVD_AD_SLOT0      0x01
UMASK_MULTI_SLOT_RCVD_AD_SLOT1      0x02
UMASK_MULTI_SLOT_RCVD_AD_SLOT2      0x04
UMASK_MULTI_SLOT_RCVD_BL_SLOT0      0x10
UMASK_MULTI_SLOT_RCVD_AK_SLOT0      0x20
UMASK_MULTI_SLOT_RCVD_AK_SLOT2      0x40

EVENT_RXC_ARB_LOST_VN0              0x4B RBOX
UMASK_RXC_ARB_LOST_VN0_AD_REQ       0x01
UMASK_RXC_ARB_LOST_VN0_AD_SNP       0x02
UMASK_RXC_ARB_LOST_VN0_AD_RSP       0x04
UMASK_RXC_ARB_LOST_VN0_BL_RSP       0x08
UMASK_RXC_ARB_LOST_VN0_BL_WB        0x10
UMASK_RXC_ARB_LOST_VN0_BL_NCB       0x20
UMASK_RXC_ARB_LOST_VN0_BL_NCS       0x40

EVENT_RXC_ARB_LOST_VN1              0x4C RBOX
UMASK_RXC_ARB_LOST_VN1_AD_REQ       0x01
UMASK_RXC_ARB_LOST_VN1_AD_SNP       0x02
UMASK_RXC_ARB_LOST_VN1_AD_RSP       0x04
UMASK_RXC_ARB_LOST_VN1_BL_RSP       0x08
UMASK_RXC_ARB_LOST_VN1_BL_WB        0x10
UMASK_RXC_ARB_LOST_VN1_BL_NCB       0x20
UMASK_RXC_ARB_LOST_VN1_BL_NCS       0x40

EVENT_RXC_ARB_MISC                   0x4D RBOX
UMASK_RXC_ARB_MISC_PAR_BIAS_VN0      0x01
UMASK_RXC_ARB_MISC_PAR_BIAS_VN1      0x02
UMASK_RXC_ARB_MISC_NO_PROG_AD_VN0    0x04
UMASK_RXC_ARB_MISC_NO_PROG_AD_VN1    0x08
UMASK_RXC_ARB_MISC_NO_PROG_BL_VN0    0x10
UMASK_RXC_ARB_MISC_NO_PROG_BL_VN1    0x20
UMASK_RXC_ARB_MISC_ADBL_PARALLEL_WIN 0x40

EVENT_RXC_ARB_NOAD_REQ_VN0              0x49 RBOX
UMASK_RXC_ARB_NOAD_REQ_VN0_AD_REQ       0x01
UMASK_RXC_ARB_NOAD_REQ_VN0_AD_SNP       0x02
UMASK_RXC_ARB_NOAD_REQ_VN0_AD_RSP       0x04
UMASK_RXC_ARB_NOAD_REQ_VN0_BL_RSP       0x08
UMASK_RXC_ARB_NOAD_REQ_VN0_BL_WB        0x10
UMASK_RXC_ARB_NOAD_REQ_VN0_BL_NCB       0x20
UMASK_RXC_ARB_NOAD_REQ_VN0_BL_NCS       0x40

EVENT_RXC_ARB_NOAD_REQ_VN1              0x4A RBOX
UMASK_RXC_ARB_NOAD_REQ_VN1_AD_REQ       0x01
UMASK_RXC_ARB_NOAD_REQ_VN1_AD_SNP       0x02
UMASK_RXC_ARB_NOAD_REQ_VN1_AD_RSP       0x04
UMASK_RXC_ARB_NOAD_REQ_VN1_BL_RSP       0x08
UMASK_RXC_ARB_NOAD_REQ_VN1_BL_WB        0x10
UMASK_RXC_ARB_NOAD_REQ_VN1_BL_NCB       0x20
UMASK_RXC_ARB_NOAD_REQ_VN1_BL_NCS       0x40

EVENT_RXC_ARB_NOCRED_VN0              0x47 RBOX
UMASK_RXC_ARB_NOCRED_VN0_AD_REQ       0x01
UMASK_RXC_ARB_NOCRED_VN0_AD_SNP       0x02
UMASK_RXC_ARB_NOCRED_VN0_AD_RSP       0x04
UMASK_RXC_ARB_NOCRED_VN0_BL_RSP       0x08
UMASK_RXC_ARB_NOCRED_VN0_BL_WB        0x10
UMASK_RXC_ARB_NOCRED_VN0_BL_NCB       0x20
UMASK_RXC_ARB_NOCRED_VN0_BL_NCS       0x40

EVENT_RXC_ARB_NOCRED_VN1              0x48 RBOX
UMASK_RXC_ARB_NOCRED_VN1_AD_REQ       0x01
UMASK_RXC_ARB_NOCRED_VN1_AD_SNP       0x02
UMASK_RXC_ARB_NOCRED_VN1_AD_RSP       0x04
UMASK_RXC_ARB_NOCRED_VN1_BL_RSP       0x08
UMASK_RXC_ARB_NOCRED_VN1_BL_WB        0x10
UMASK_RXC_ARB_NOCRED_VN1_BL_NCB       0x20
UMASK_RXC_ARB_NOCRED_VN1_BL_NCS       0x40

EVENT_RXC_BYPASSED                  0x40 RBOX
UMASK_RXC_BYPASSED_AD_S0_IDLE       0x01
UMASK_RXC_BYPASSED_AD_S0_BL_ARB     0x02
UMASK_RXC_BYPASSED_AD_S1_BL_SLOT    0x04
UMASK_RXC_BYPASSED_AD_S2_BL_SLOT    0x08

EVENT_RXC_COLLISION_VN0              0x50 RBOX
UMASK_RXC_COLLISION_VN0_AD_REQ       0x01
UMASK_RXC_COLLISION_VN0_AD_SNP       0x02
UMASK_RXC_COLLISION_VN0_AD_RSP       0x04
UMASK_RXC_COLLISION_VN0_BL_RSP       0x08
UMASK_RXC_COLLISION_VN0_BL_WB        0x10
UMASK_RXC_COLLISION_VN0_BL_NCB       0x20
UMASK_RXC_COLLISION_VN0_BL_NCS       0x40

EVENT_RXC_COLLISION_VN1              0x51 RBOX
UMASK_RXC_COLLISION_VN1_AD_REQ       0x01
UMASK_RXC_COLLISION_VN1_AD_SNP       0x02
UMASK_RXC_COLLISION_VN1_AD_RSP       0x04
UMASK_RXC_COLLISION_VN1_BL_RSP       0x08
UMASK_RXC_COLLISION_VN1_BL_WB        0x10
UMASK_RXC_COLLISION_VN1_BL_NCB       0x20
UMASK_RXC_COLLISION_VN1_BL_NCS       0x40

EVENT_RXC_CRD_MISC                  0x60 RBOX
UMASK_RXC_CRD_MISC_ANY_BGF_FIFO     0x01
UMASK_RXC_CRD_MISC_ANY_BGF_PATH     0x02
UMASK_RXC_CRD_MISC_NO_D2K_FOR_ARB   0x04

EVENT_RXC_CRD_OCC                   0x61 RBOX
UMASK_RXC_CRD_OCC_VNA_IN_USE        0x01
UMASK_RXC_CRD_OCC_FLITS_IN_FIFO     0x02
UMASK_RXC_CRD_OCC_FLITS_IN_PATH     0x04
UMASK_RXC_CRD_OCC_TXQ_CRD           0x08
UMASK_RXC_CRD_OCC_D2K_CRD           0x10
UMASK_RXC_CRD_OCC_P1P_TOTAL         0x20
UMASK_RXC_CRD_OCC_P1P_FIFO          0x40

EVENT_RXC_CYCLES_NE_VN0             0x43 RBOX
UMASK_RXC_CYCLES_NE_VN0_AD_REQ      0x01
UMASK_RXC_CYCLES_NE_VN0_AD_SNP      0x02
UMASK_RXC_CYCLES_NE_VN0_AD_RSP      0x04
UMASK_RXC_CYCLES_NE_VN0_BL_RSP      0x08
UMASK_RXC_CYCLES_NE_VN0_BL_WB       0x10
UMASK_RXC_CYCLES_NE_VN0_BL_NCB      0x20
UMASK_RXC_CYCLES_NE_VN0_BL_NCS      0x40

EVENT_RXC_CYCLES_NE_VN1             0x44 RBOX
UMASK_RXC_CYCLES_NE_VN1_AD_REQ      0x01
UMASK_RXC_CYCLES_NE_VN1_AD_SNP      0x02
UMASK_RXC_CYCLES_NE_VN1_AD_RSP      0x04
UMASK_RXC_CYCLES_NE_VN1_BL_RSP      0x08
UMASK_RXC_CYCLES_NE_VN1_BL_WB       0x10
UMASK_RXC_CYCLES_NE_VN1_BL_NCB      0x20
UMASK_RXC_CYCLES_NE_VN1_BL_NCS      0x40

EVENT_RXC_FLITS_DATA_NOT_SENT           0x57 RBOX
UMASK_RXC_FLITS_DATA_NOT_SENT_ALL       0x01
UMASK_RXC_FLITS_DATA_NOT_SENT_NO_BGF    0x02
UMASK_RXC_FLITS_DATA_NOT_SENT_NO_TXQ    0x04

EVENT_RXC_FLITS_GEN_BL              0x59 RBOX
UMASK_RXC_FLITS_GEN_BL_P0_WAIT      0x01
UMASK_RXC_FLITS_GEN_BL_P1_WAIT      0x02
UMASK_RXC_FLITS_GEN_BL_P1P_TO_LIMBO 0x04
UMASK_RXC_FLITS_GEN_BL_P1P_BUSY     0x08
UMASK_RXC_FLITS_GEN_BL_P1P_AT_LIMIT 0x10
UMASK_RXC_FLITS_GEN_BL_P1P_HOLD_P0  0x20
UMASK_RXC_FLITS_GEN_BL_P1P_FIFO_FULL 0x40

EVENT_RXC_FLITS_MISC                0x5A RBOX
UMASK_RXC_FLITS_MISC                0x00

EVENT_RXC_FLITS_SENT                0x56 RBOX
UMASK_RXC_FLITS_SENT_1_MSG          0x01
UMASK_RXC_FLITS_SENT_2_MSGS         0x02
UMASK_RXC_FLITS_SENT_3_MSGS         0x04
UMASK_RXC_FLITS_SENT_1_MSG_VNX      0x08
UMASK_RXC_FLITS_SENT_SLOTS_1        0x10
UMASK_RXC_FLITS_SENT_SLOTS_2        0x20
UMASK_RXC_FLITS_SENT_SLOTS_3        0x40

EVENT_RXC_FLITS_SLOT_BL             0x58 RBOX
UMASK_RXC_FLITS_SLOT_BL_ALL         0x01
UMASK_RXC_FLITS_SLOT_BL_NEED_DATA   0x02
UMASK_RXC_FLITS_SLOT_BL_P0_WAIT     0x04
UMASK_RXC_FLITS_SLOT_BL_P1_WAIT     0x08
UMASK_RXC_FLITS_SLOT_BL_P1_NOT_REQ  0x10
UMASK_RXC_FLITS_SLOT_BL_P1_NOT_REQ_BUT_BUBBLE 0x20
UMASK_RXC_FLITS_SLOT_BL_P1_NOT_REQ_NOT_AVAIL  0x40

EVENT_RXC_FLIT_GEN_HDR1                 0x53 RBOX
UMASK_RXC_FLIT_GEN_HDR1_ACCUM           0x01
UMASK_RXC_FLIT_GEN_HDR1_ACCUM_READ      0x02
UMASK_RXC_FLIT_GEN_HDR1_ACCUM_WASTED    0x04
UMASK_RXC_FLIT_GEN_HDR1_AHEAD_BLOCKED   0x08
UMASK_RXC_FLIT_GEN_HDR1_AHEAD_MSG       0x10
UMASK_RXC_FLIT_GEN_HDR1_PAR             0x20
UMASK_RXC_FLIT_GEN_HDR1_PAR_MSG         0x40
UMASK_RXC_FLIT_GEN_HDR1_PAR_FLIT        0x80

EVENT_RXC_FLIT_GEN_HDR2                 0x54 RBOX
UMASK_RXC_FLIT_GEN_HDR2_RMSTALL         0x01
UMASK_RXC_FLIT_GEN_HDR2_RMSTALL_NOMSG   0x02

EVENT_RXC_FLIT_NOT_SENT                 0x55 RBOX
UMASK_RXC_FLIT_NOT_SENT_ALL             0x01
UMASK_RXC_FLIT_NOT_SENT_NO_BGF_CRD      0x02
UMASK_RXC_FLIT_NOT_SENT_NO_TXQ_CRD      0x04
UMASK_RXC_FLIT_NOT_SENT_NO_BGF_NO_MSG   0x08
UMASK_RXC_FLIT_NOT_SENT_NO_TXQ_NO_MSG   0x10
UMASK_RXC_FLIT_NOT_SENT_ONE_TAKEN       0x20
UMASK_RXC_FLIT_NOT_SENT_TWO_TAKEN       0x40
UMASK_RXC_FLIT_NOT_SENT_THREE_TAKEN     0x80

EVENT_RXC_HELD                          0x52 RBOX
UMASK_RXC_HELD_VN0                      0x01
UMASK_RXC_HELD_VN1                      0x02
UMASK_RXC_HELD_PARALLEL_ATTEMPT         0x04
UMASK_RXC_HELD_PARALLEL_SUCCESS         0x08
UMASK_RXC_HELD_PARALLEL_AD_LOST         0x10
UMASK_RXC_HELD_PARALLEL_BL_LOST         0x20
UMASK_RXC_HELD_CANT_SLOT_AD             0x40
UMASK_RXC_HELD_CANT_SLOT_BL             0x80

EVENT_RXC_INSERTS_VN0              0x41 RBOX
UMASK_RXC_INSERTS_VN0_AD_REQ       0x01
UMASK_RXC_INSERTS_VN0_AD_SNP       0x02
UMASK_RXC_INSERTS_VN0_AD_RSP       0x04
UMASK_RXC_INSERTS_VN0_BL_RSP       0x08
UMASK_RXC_INSERTS_VN0_BL_WB        0x10
UMASK_RXC_INSERTS_VN0_BL_NCB       0x20
UMASK_RXC_INSERTS_VN0_BL_NCS       0x40

EVENT_RXC_INSERTS_VN1              0x42 RBOX
UMASK_RXC_INSERTS_VN1_AD_REQ       0x01
UMASK_RXC_INSERTS_VN1_AD_SNP       0x02
UMASK_RXC_INSERTS_VN1_AD_RSP       0x04
UMASK_RXC_INSERTS_VN1_BL_RSP       0x08
UMASK_RXC_INSERTS_VN1_BL_WB        0x10
UMASK_RXC_INSERTS_VN1_BL_NCB       0x20
UMASK_RXC_INSERTS_VN1_BL_NCS       0x40

EVENT_RXC_OCCUPANCY_VN0              0x45 RBOX
UMASK_RXC_OCCUPANCY_VN0_AD_REQ       0x01
UMASK_RXC_OCCUPANCY_VN0_AD_SNP       0x02
UMASK_RXC_OCCUPANCY_VN0_AD_RSP       0x04
UMASK_RXC_OCCUPANCY_VN0_BL_RSP       0x08
UMASK_RXC_OCCUPANCY_VN0_BL_WB        0x10
UMASK_RXC_OCCUPANCY_VN0_BL_NCB       0x20
UMASK_RXC_OCCUPANCY_VN0_BL_NCS       0x40

EVENT_RXC_OCCUPANCY_VN1              0x46 RBOX
UMASK_RXC_OCCUPANCY_VN1_AD_REQ       0x01
UMASK_RXC_OCCUPANCY_VN1_AD_SNP       0x02
UMASK_RXC_OCCUPANCY_VN1_AD_RSP       0x04
UMASK_RXC_OCCUPANCY_VN1_BL_RSP       0x08
UMASK_RXC_OCCUPANCY_VN1_BL_WB        0x10
UMASK_RXC_OCCUPANCY_VN1_BL_NCB       0x20
UMASK_RXC_OCCUPANCY_VN1_BL_NCS       0x40

EVENT_RXC_PACKING_MISS_VN0              0x4E RBOX
UMASK_RXC_PACKING_MISS_VN0_AD_REQ       0x01
UMASK_RXC_PACKING_MISS_VN0_AD_SNP       0x02
UMASK_RXC_PACKING_MISS_VN0_AD_RSP       0x04
UMASK_RXC_PACKING_MISS_VN0_BL_RSP       0x08
UMASK_RXC_PACKING_MISS_VN0_BL_WB        0x10
UMASK_RXC_PACKING_MISS_VN0_BL_NCB       0x20
UMASK_RXC_PACKING_MISS_VN0_BL_NCS       0x40

EVENT_RXC_PACKING_MISS_VN1              0x4F RBOX
UMASK_RXC_PACKING_MISS_VN1_AD_REQ       0x01
UMASK_RXC_PACKING_MISS_VN1_AD_SNP       0x02
UMASK_RXC_PACKING_MISS_VN1_AD_RSP       0x04
UMASK_RXC_PACKING_MISS_VN1_BL_RSP       0x08
UMASK_RXC_PACKING_MISS_VN1_BL_WB        0x10
UMASK_RXC_PACKING_MISS_VN1_BL_NCB       0x20
UMASK_RXC_PACKING_MISS_VN1_BL_NCS       0x40

EVENT_RXC_SMI3_PFTCH                    0x62 RBOX
UMASK_RXC_SMI3_PFTCH_ARRIVED            0x01
UMASK_RXC_SMI3_PFTCH_ARB_LOST           0x02
UMASK_RXC_SMI3_PFTCH_SLOTTED            0x04
UMASK_RXC_SMI3_PFTCH_DROP_OLD           0x08
UMASK_RXC_SMI3_PFTCH_DROP_WRAP          0x10

EVENT_RXC_VNA_CRD                       0x5B RBOX
UMASK_RXC_VNA_CRD_USED                  0x01
UMASK_RXC_VNA_CRD_CORRECTED             0x02
UMASK_RXC_VNA_CRD_LT1                   0x04
UMASK_RXC_VNA_CRD_LT4                   0x08
UMASK_RXC_VNA_CRD_LT5                   0x10
UMASK_RXC_VNA_CRD_ANY_IN_USE            0x20

EVENT_TXC_AD_ARB_FAIL                   0x30 RBOX
UMASK_TXC_AD_ARB_FAIL_VN0_REQ           0x01
UMASK_TXC_AD_ARB_FAIL_VN0_SNP           0x02
UMASK_TXC_AD_ARB_FAIL_VN0_RSP           0x04
UMASK_TXC_AD_ARB_FAIL_VN0_WB            0x08
UMASK_TXC_AD_ARB_FAIL_VN1_REQ           0x10
UMASK_TXC_AD_ARB_FAIL_VN1_SNP           0x20
UMASK_TXC_AD_ARB_FAIL_VN1_RSP           0x40
UMASK_TXC_AD_ARB_FAIL_VN1_WB            0x80

EVENT_TXC_AD_FLQ_BYPASS                 0x2C RBOX
UMASK_TXC_AD_FLQ_BYPASS_AD_SLOT0        0x01
UMASK_TXC_AD_FLQ_BYPASS_AD_SLOT1        0x02
UMASK_TXC_AD_FLQ_BYPASS_AD_SLOT2        0x04
UMASK_TXC_AD_FLQ_BYPASS_BL_EARLY_RSP    0x08

EVENT_TXC_AD_FLQ_CYCLES_NE                   0x27 RBOX
UMASK_TXC_AD_FLQ_CYCLES_NE_VN0_REQ           0x01
UMASK_TXC_AD_FLQ_CYCLES_NE_VN0_SNP           0x02
UMASK_TXC_AD_FLQ_CYCLES_NE_VN0_RSP           0x04
UMASK_TXC_AD_FLQ_CYCLES_NE_VN0_WB            0x08
UMASK_TXC_AD_FLQ_CYCLES_NE_VN1_REQ           0x10
UMASK_TXC_AD_FLQ_CYCLES_NE_VN1_SNP           0x20
UMASK_TXC_AD_FLQ_CYCLES_NE_VN1_RSP           0x40
UMASK_TXC_AD_FLQ_CYCLES_NE_VN1_WB            0x80

EVENT_TXC_AD_FLQ_INSERTS                   0x2D RBOX
UMASK_TXC_AD_FLQ_INSERTS_VN0_REQ           0x01
UMASK_TXC_AD_FLQ_INSERTS_VN0_SNP           0x02
UMASK_TXC_AD_FLQ_INSERTS_VN0_RSP           0x04
UMASK_TXC_AD_FLQ_INSERTS_VN0_WB            0x08
UMASK_TXC_AD_FLQ_INSERTS_VN1_REQ           0x10
UMASK_TXC_AD_FLQ_INSERTS_VN1_SNP           0x20
UMASK_TXC_AD_FLQ_INSERTS_VN1_RSP           0x40
UMASK_TXC_AD_FLQ_INSERTS_VN1_WB            0x80

EVENT_TXC_AD_FLQ_OCCUPANCY                   0x1C RBOX0C0|RBOX1C0|RBOX2C0|RBOX3C0
UMASK_TXC_AD_FLQ_OCCUPANCY_VN0_REQ           0x01
UMASK_TXC_AD_FLQ_OCCUPANCY_VN0_SNP           0x02
UMASK_TXC_AD_FLQ_OCCUPANCY_VN0_RSP           0x04
UMASK_TXC_AD_FLQ_OCCUPANCY_VN0_WB            0x08
UMASK_TXC_AD_FLQ_OCCUPANCY_VN1_REQ           0x10
UMASK_TXC_AD_FLQ_OCCUPANCY_VN1_SNP           0x20
UMASK_TXC_AD_FLQ_OCCUPANCY_VN1_RSP           0x40
UMASK_TXC_AD_FLQ_OCCUPANCY_VN1_WB            0x80

EVENT_TXC_AD_SNPF_GRP1_VN1                  0x3C RBOX0C0|RBOX1C0|RBOX2C0|RBOX3C0
UMASK_TXC_AD_SNPF_GRP1_VN1_VN0_PEER_UPI0    0x01
UMASK_TXC_AD_SNPF_GRP1_VN1_VN0_PEER_UPI1    0x02
UMASK_TXC_AD_SNPF_GRP1_VN1_VN0_CHA          0x04
UMASK_TXC_AD_SNPF_GRP1_VN1_VN1_PEER_UPI0    0x08
UMASK_TXC_AD_SNPF_GRP1_VN1_VN1_PEER_UPI1    0x10
UMASK_TXC_AD_SNPF_GRP1_VN1_VN1_CHA          0x20
UMASK_TXC_AD_SNPF_GRP1_VN1_VN0_NON_IDLE     0x40
UMASK_TXC_AD_SNPF_GRP1_VN1_VN1_NON_IDLE     0x80

EVENT_TXC_AD_SNPF_GRP2_VN1                  0x3D RBOX
UMASK_TXC_AD_SNPF_GRP2_VN1_VN0_SNPFP_NONSNP 0x01
UMASK_TXC_AD_SNPF_GRP2_VN1_VN1_SNPFP_NONSNP 0x02
UMASK_TXC_AD_SNPF_GRP2_VN1_VN0_SNPFP_VN2SNP 0x04
UMASK_TXC_AD_SNPF_GRP2_VN1_VN1_SNPFP_VN2SNP 0x08

EVENT_TXC_AD_SPEC_ARB_CRD_AVAIL                   0x34 RBOX
UMASK_TXC_AD_SPEC_ARB_CRD_AVAIL_VN0_REQ           0x01
UMASK_TXC_AD_SPEC_ARB_CRD_AVAIL_VN0_SNP           0x02
UMASK_TXC_AD_SPEC_ARB_CRD_AVAIL_VN0_WB            0x08
UMASK_TXC_AD_SPEC_ARB_CRD_AVAIL_VN1_REQ           0x10
UMASK_TXC_AD_SPEC_ARB_CRD_AVAIL_VN1_SNP           0x20
UMASK_TXC_AD_SPEC_ARB_CRD_AVAIL_VN1_WB            0x80

EVENT_TXC_AD_SPEC_ARB_NEW_MSG                   0x33 RBOX
UMASK_TXC_AD_SPEC_ARB_NEW_MSG_VN0_REQ           0x01
UMASK_TXC_AD_SPEC_ARB_NEW_MSG_VN0_SNP           0x02
UMASK_TXC_AD_SPEC_ARB_NEW_MSG_VN0_WB            0x08
UMASK_TXC_AD_SPEC_ARB_NEW_MSG_VN1_REQ           0x10
UMASK_TXC_AD_SPEC_ARB_NEW_MSG_VN1_SNP           0x20
UMASK_TXC_AD_SPEC_ARB_NEW_MSG_VN1_WB            0x80

EVENT_TXC_AD_SPEC_ARB_NO_OTHER_PEND                   0x32 RBOX
UMASK_TXC_AD_SPEC_ARB_NO_OTHER_PEND_VN0_REQ           0x01
UMASK_TXC_AD_SPEC_ARB_NO_OTHER_PEND_VN0_SNP           0x02
UMASK_TXC_AD_SPEC_ARB_NO_OTHER_PEND_VN0_RSP           0x04
UMASK_TXC_AD_SPEC_ARB_NO_OTHER_PEND_VN0_WB            0x08
UMASK_TXC_AD_SPEC_ARB_NO_OTHER_PEND_VN1_REQ           0x10
UMASK_TXC_AD_SPEC_ARB_NO_OTHER_PEND_VN1_SNP           0x20
UMASK_TXC_AD_SPEC_ARB_NO_OTHER_PEND_VN1_RSP           0x40
UMASK_TXC_AD_SPEC_ARB_NO_OTHER_PEND_VN1_WB            0x80

EVENT_TXC_AK_FLQ_INSERTS            0x2F RBOX
UMASK_TXC_AK_FLQ_INSERTS            0x00

EVENT_TXC_AK_FLQ_OCCUPANCY          0x1E RBOX0C0|RBOX1C0|RBOX2C0|RBOX3C0
UMASK_TXC_AK_FLQ_OCCUPANCY          0x00

EVENT_TXC_BL_ARB_FAIL                   0x35 RBOX
UMASK_TXC_BL_ARB_FAIL_VN0_RSP           0x01
UMASK_TXC_BL_ARB_FAIL_VN0_WB            0x02
UMASK_TXC_BL_ARB_FAIL_VN0_NCB           0x04
UMASK_TXC_BL_ARB_FAIL_VN0_NCS           0x08
UMASK_TXC_BL_ARB_FAIL_VN1_RSP           0x10
UMASK_TXC_BL_ARB_FAIL_VN1_WB            0x20
UMASK_TXC_BL_ARB_FAIL_VN1_NCB           0x40
UMASK_TXC_BL_ARB_FAIL_VN1_NCS           0x80

EVENT_TXC_BL_FLQ_CYCLES_NE                   0x28 RBOX
UMASK_TXC_BL_FLQ_CYCLES_NE_VN0_REQ           0x01
UMASK_TXC_BL_FLQ_CYCLES_NE_VN0_SNP           0x02
UMASK_TXC_BL_FLQ_CYCLES_NE_VN0_RSP           0x04
UMASK_TXC_BL_FLQ_CYCLES_NE_VN0_WB            0x08
UMASK_TXC_BL_FLQ_CYCLES_NE_VN1_REQ           0x10
UMASK_TXC_BL_FLQ_CYCLES_NE_VN1_SNP           0x20
UMASK_TXC_BL_FLQ_CYCLES_NE_VN1_RSP           0x40
UMASK_TXC_BL_FLQ_CYCLES_NE_VN1_WB            0x80

EVENT_TXC_BL_FLQ_INSERTS                   0x2E RBOX
UMASK_TXC_BL_FLQ_INSERTS_VN0_NCB           0x01
UMASK_TXC_BL_FLQ_INSERTS_VN0_NCS           0x02
UMASK_TXC_BL_FLQ_INSERTS_VN0_WB            0x04
UMASK_TXC_BL_FLQ_INSERTS_VN0_RSP           0x08
UMASK_TXC_BL_FLQ_INSERTS_VN1_NCB           0x10
UMASK_TXC_BL_FLQ_INSERTS_VN1_NCS           0x20
UMASK_TXC_BL_FLQ_INSERTS_VN1_WB            0x40
UMASK_TXC_BL_FLQ_INSERTS_VN1_RSP           0x80

EVENT_TXC_BL_FLQ_OCCUPANCY                   0x1D RBOX0C0|RBOX1C0|RBOX2C0|RBOX3C0
UMASK_TXC_BL_FLQ_OCCUPANCY_VN0_RSP           0x01
UMASK_TXC_BL_FLQ_OCCUPANCY_VN0_WB            0x02
UMASK_TXC_BL_FLQ_OCCUPANCY_VN0_NCB           0x04
UMASK_TXC_BL_FLQ_OCCUPANCY_VN0_NCS           0x08
UMASK_TXC_BL_FLQ_OCCUPANCY_VN1_RSP           0x10
UMASK_TXC_BL_FLQ_OCCUPANCY_VN1_WB            0x20
UMASK_TXC_BL_FLQ_OCCUPANCY_VN1_NCB           0x40
UMASK_TXC_BL_FLQ_OCCUPANCY_VN1_NCS           0x80

EVENT_TXC_BL_SPEC_ARB_NEW_MSG               0x38 RBOX
UMASK_TXC_BL_SPEC_ARB_NEW_MSG_VN0_WB        0x01
UMASK_TXC_BL_SPEC_ARB_NEW_MSG_VN0_NCB       0x02
UMASK_TXC_BL_SPEC_ARB_NEW_MSG_VN0_NCS       0x08
UMASK_TXC_BL_SPEC_ARB_NEW_MSG_VN1_WB        0x10
UMASK_TXC_BL_SPEC_ARB_NEW_MSG_VN1_NCB       0x20
UMASK_TXC_BL_SPEC_ARB_NEW_MSG_VN1_NCS       0x80

EVENT_TXC_BL_SPEC_ARB_NO_OTHER_PEND         0x37 RBOX
UMASK_TXC_BL_SPEC_ARB_NO_OTHER_PEND_VN0_RSP 0x01
UMASK_TXC_BL_SPEC_ARB_NO_OTHER_PEND_VN0_WB  0x02
UMASK_TXC_BL_SPEC_ARB_NO_OTHER_PEND_VN0_NCB 0x04
UMASK_TXC_BL_SPEC_ARB_NO_OTHER_PEND_VN0_NCS 0x08
UMASK_TXC_BL_SPEC_ARB_NO_OTHER_PEND_VN1_RSP 0x10
UMASK_TXC_BL_SPEC_ARB_NO_OTHER_PEND_VN1_WB  0x20
UMASK_TXC_BL_SPEC_ARB_NO_OTHER_PEND_VN1_NCB 0x40
UMASK_TXC_BL_SPEC_ARB_NO_OTHER_PEND_VN1_NCS 0x80

EVENT_UPI_PEER_AD_CREDITS_EMPTY             0x20 RBOX
UMASK_UPI_PEER_AD_CREDITS_EMPTY_VNA         0x01
UMASK_UPI_PEER_AD_CREDITS_EMPTY_VN0_REQ     0x02
UMASK_UPI_PEER_AD_CREDITS_EMPTY_VN0_SNP     0x04
UMASK_UPI_PEER_AD_CREDITS_EMPTY_VN0_RSP     0x08
UMASK_UPI_PEER_AD_CREDITS_EMPTY_VN1_REQ     0x10
UMASK_UPI_PEER_AD_CREDITS_EMPTY_VN1_SNP     0x20
UMASK_UPI_PEER_AD_CREDITS_EMPTY_VN1_RSP     0x40

EVENT_UPI_PEER_BL_CREDITS_EMPTY             0x21 RBOX
UMASK_UPI_PEER_BL_CREDITS_EMPTY_VNA         0x01
UMASK_UPI_PEER_BL_CREDITS_EMPTY_VN0_RSP     0x02
UMASK_UPI_PEER_BL_CREDITS_EMPTY_VN0_NCS_NCB 0x04
UMASK_UPI_PEER_BL_CREDITS_EMPTY_VN0_WB      0x08
UMASK_UPI_PEER_BL_CREDITS_EMPTY_VN1_RSP     0x10
UMASK_UPI_PEER_BL_CREDITS_EMPTY_VN1_NCS_NCB 0x20
UMASK_UPI_PEER_BL_CREDITS_EMPTY_VN1_WB      0x40

EVENT_UPI_PREFETCH_SPAWN                0x29 RBOX
UMASK_UPI_PREFETCH_SPAWN                0x00

EVENT_VN0_CREDITS_USED                  0x5C RBOX
UMASK_VN0_CREDITS_USED_REQ              0x01
UMASK_VN0_CREDITS_USED_SNP              0x02
UMASK_VN0_CREDITS_USED_RSP              0x04
UMASK_VN0_CREDITS_USED_WB               0x08
UMASK_VN0_CREDITS_USED_NCB              0x10
UMASK_VN0_CREDITS_USED_NCS              0x20

EVENT_VN1_CREDITS_USED                  0x5D RBOX
UMASK_VN1_CREDITS_USED_REQ              0x01
UMASK_VN1_CREDITS_USED_SNP              0x02
UMASK_VN1_CREDITS_USED_RSP              0x04
UMASK_VN1_CREDITS_USED_WB               0x08
UMASK_VN1_CREDITS_USED_NCB              0x10
UMASK_VN1_CREDITS_USED_NCS              0x20

EVENT_VN0_NO_CREDITS                  0x5E RBOX
UMASK_VN0_NO_CREDITS_REQ              0x01
UMASK_VN0_NO_CREDITS_SNP              0x02
UMASK_VN0_NO_CREDITS_RSP              0x04
UMASK_VN0_NO_CREDITS_WB               0x08
UMASK_VN0_NO_CREDITS_NCB              0x10
UMASK_VN0_NO_CREDITS_NCS              0x20

EVENT_VN1_NO_CREDITS                  0x5F RBOX
UMASK_VN1_NO_CREDITS_REQ              0x01
UMASK_VN1_NO_CREDITS_SNP              0x02
UMASK_VN1_NO_CREDITS_RSP              0x04
UMASK_VN1_NO_CREDITS_WB               0x08
UMASK_VN1_NO_CREDITS_NCB              0x10
UMASK_VN1_NO_CREDITS_NCS              0x20

EVENT_IBOX_CLOCKTICKS               0x01 IBOX
UMASK_IBOX_CLOCKTICKS               0x00

EVENT_COMP_BUF_INSERTS              0xC2 IBOX
UMASK_COMP_BUF_INSERTS_PORT0        0x04 0x07 0x01
UMASK_COMP_BUF_INSERTS_PORT1        0x04 0x07 0x02
UMASK_COMP_BUF_INSERTS_PORT2        0x04 0x07 0x04
UMASK_COMP_BUF_INSERTS_PORT3        0x04 0x07 0x08

EVENT_COMP_BUF_OCCUPANCY            0xD5 IBOX
UMASK_COMP_BUF_OCCUPANCY            0x00

EVENT_DATA_REQ_BY_CPU                    0xC0 IBOX
UMASK_DATA_REQ_BY_CPU_MEM_READ_PART0     0x04 0x03 0x01
UMASK_DATA_REQ_BY_CPU_MEM_READ_PART1     0x04 0x03 0x02
UMASK_DATA_REQ_BY_CPU_MEM_READ_PART2     0x04 0x03 0x04
UMASK_DATA_REQ_BY_CPU_MEM_READ_PART3     0x04 0x03 0x08
UMASK_DATA_REQ_BY_CPU_MEM_READ_VTD0      0x04 0x03 0x10
UMASK_DATA_REQ_BY_CPU_MEM_READ_VTD1      0x04 0x03 0x20
UMASK_DATA_REQ_BY_CPU_MEM_WRITE_PART0    0x01 0x03 0x01
UMASK_DATA_REQ_BY_CPU_MEM_WRITE_PART1    0x01 0x03 0x02
UMASK_DATA_REQ_BY_CPU_MEM_WRITE_PART2    0x01 0x03 0x04
UMASK_DATA_REQ_BY_CPU_MEM_WRITE_PART3    0x01 0x03 0x08
UMASK_DATA_REQ_BY_CPU_MEM_WRITE_VTD0     0x01 0x03 0x10
UMASK_DATA_REQ_BY_CPU_MEM_WRITE_VTD1     0x01 0x03 0x20
UMASK_DATA_REQ_BY_CPU_PEER_READ_PART0    0x08 0x03 0x01
UMASK_DATA_REQ_BY_CPU_PEER_READ_PART1    0x08 0x03 0x02
UMASK_DATA_REQ_BY_CPU_PEER_READ_PART2    0x08 0x03 0x04
UMASK_DATA_REQ_BY_CPU_PEER_READ_PART3    0x08 0x03 0x08
UMASK_DATA_REQ_BY_CPU_PEER_READ_VTD0     0x08 0x03 0x10
UMASK_DATA_REQ_BY_CPU_PEER_READ_VTD1     0x08 0x03 0x20
UMASK_DATA_REQ_BY_CPU_PEER_WRITE_PART0   0x02 0x03 0x01
UMASK_DATA_REQ_BY_CPU_PEER_WRITE_PART1   0x02 0x03 0x02
UMASK_DATA_REQ_BY_CPU_PEER_WRITE_PART2   0x02 0x03 0x04
UMASK_DATA_REQ_BY_CPU_PEER_WRITE_PART3   0x02 0x03 0x08
UMASK_DATA_REQ_BY_CPU_PEER_WRITE_VTD0    0x02 0x03 0x10
UMASK_DATA_REQ_BY_CPU_PEER_WRITE_VTD1    0x02 0x03 0x20
UMASK_DATA_REQ_BY_CPU_CFG_READ_PART0     0x40 0x03 0x01
UMASK_DATA_REQ_BY_CPU_CFG_READ_PART1     0x40 0x03 0x02
UMASK_DATA_REQ_BY_CPU_CFG_READ_PART2     0x40 0x03 0x04
UMASK_DATA_REQ_BY_CPU_CFG_READ_PART3     0x40 0x03 0x08
UMASK_DATA_REQ_BY_CPU_CFG_READ_VTD0      0x40 0x03 0x10
UMASK_DATA_REQ_BY_CPU_CFG_READ_VTD1      0x40 0x03 0x20
UMASK_DATA_REQ_BY_CPU_CFG_WRITE_PART0    0x10 0x03 0x01
UMASK_DATA_REQ_BY_CPU_CFG_WRITE_PART1    0x10 0x03 0x02
UMASK_DATA_REQ_BY_CPU_CFG_WRITE_PART2    0x10 0x03 0x04
UMASK_DATA_REQ_BY_CPU_CFG_WRITE_PART3    0x10 0x03 0x08
UMASK_DATA_REQ_BY_CPU_CFG_WRITE_VTD0     0x10 0x03 0x10
UMASK_DATA_REQ_BY_CPU_CFG_WRITE_VTD1     0x10 0x03 0x20
UMASK_DATA_REQ_BY_CPU_IO_READ_PART0      0x80 0x03 0x01
UMASK_DATA_REQ_BY_CPU_IO_READ_PART1      0x80 0x03 0x02
UMASK_DATA_REQ_BY_CPU_IO_READ_PART2      0x80 0x03 0x04
UMASK_DATA_REQ_BY_CPU_IO_READ_PART3      0x80 0x03 0x08
UMASK_DATA_REQ_BY_CPU_IO_READ_VTD0       0x80 0x03 0x10
UMASK_DATA_REQ_BY_CPU_IO_READ_VTD1       0x80 0x03 0x20
UMASK_DATA_REQ_BY_CPU_IO_WRITE_PART0      0x20 0x03 0x01
UMASK_DATA_REQ_BY_CPU_IO_WRITE_PART1     0x20 0x03 0x02
UMASK_DATA_REQ_BY_CPU_IO_WRITE_PART2     0x20 0x03 0x04
UMASK_DATA_REQ_BY_CPU_IO_WRITE_PART3     0x20 0x03 0x08
UMASK_DATA_REQ_BY_CPU_IO_WRITE_VTD0      0x20 0x03 0x10
UMASK_DATA_REQ_BY_CPU_IO_WRITE_VTD1      0x20 0x03 0x20


EVENT_DATA_REQ_OF_CPU                    0x83 IBOX
UMASK_DATA_REQ_OF_CPU_MEM_READ_PART0     0x04 0x03 0x01
UMASK_DATA_REQ_OF_CPU_MEM_READ_PART1     0x04 0x03 0x02
UMASK_DATA_REQ_OF_CPU_MEM_READ_PART2     0x04 0x03 0x04
UMASK_DATA_REQ_OF_CPU_MEM_READ_PART3     0x04 0x03 0x08
UMASK_DATA_REQ_OF_CPU_MEM_READ_VTD0      0x04 0x03 0x10
UMASK_DATA_REQ_OF_CPU_MEM_READ_VTD1      0x04 0x03 0x20
UMASK_DATA_REQ_OF_CPU_MEM_WRITE_PART0    0x01 0x03 0x01
UMASK_DATA_REQ_OF_CPU_MEM_WRITE_PART1    0x01 0x03 0x02
UMASK_DATA_REQ_OF_CPU_MEM_WRITE_PART2    0x01 0x03 0x04
UMASK_DATA_REQ_OF_CPU_MEM_WRITE_PART3    0x01 0x03 0x08
UMASK_DATA_REQ_OF_CPU_MEM_WRITE_VTD0     0x01 0x03 0x10
UMASK_DATA_REQ_OF_CPU_MEM_WRITE_VTD1     0x01 0x03 0x20
UMASK_DATA_REQ_OF_CPU_PEER_READ_PART0    0x08 0x03 0x01
UMASK_DATA_REQ_OF_CPU_PEER_READ_PART1    0x08 0x03 0x02
UMASK_DATA_REQ_OF_CPU_PEER_READ_PART2    0x08 0x03 0x04
UMASK_DATA_REQ_OF_CPU_PEER_READ_PART3    0x08 0x03 0x08
UMASK_DATA_REQ_OF_CPU_PEER_READ_VTD0     0x08 0x03 0x10
UMASK_DATA_REQ_OF_CPU_PEER_READ_VTD1     0x08 0x03 0x20
UMASK_DATA_REQ_OF_CPU_PEER_WRITE_PART0   0x02 0x03 0x01
UMASK_DATA_REQ_OF_CPU_PEER_WRITE_PART1   0x02 0x03 0x02
UMASK_DATA_REQ_OF_CPU_PEER_WRITE_PART2   0x02 0x03 0x04
UMASK_DATA_REQ_OF_CPU_PEER_WRITE_PART3   0x02 0x03 0x08
UMASK_DATA_REQ_OF_CPU_PEER_WRITE_VTD0    0x02 0x03 0x10
UMASK_DATA_REQ_OF_CPU_PEER_WRITE_VTD1    0x02 0x03 0x20
UMASK_DATA_REQ_OF_CPU_ATOMIC_PART0       0x10 0x03 0x01
UMASK_DATA_REQ_OF_CPU_ATOMIC_PART1       0x10 0x03 0x02
UMASK_DATA_REQ_OF_CPU_ATOMIC_PART2       0x10 0x03 0x04
UMASK_DATA_REQ_OF_CPU_ATOMIC_PART3       0x10 0x03 0x08
UMASK_DATA_REQ_OF_CPU_ATOMIC_VTD0        0x10 0x03 0x10
UMASK_DATA_REQ_OF_CPU_ATOMIC_VTD1        0x10 0x03 0x20
UMASK_DATA_REQ_OF_CPU_ATOMICCMP_PART0    0x20 0x03 0x01
UMASK_DATA_REQ_OF_CPU_ATOMICCMP_PART1    0x20 0x03 0x02
UMASK_DATA_REQ_OF_CPU_ATOMICCMP_PART2    0x20 0x03 0x04
UMASK_DATA_REQ_OF_CPU_ATOMICCMP_PART3    0x20 0x03 0x08
UMASK_DATA_REQ_OF_CPU_ATOMICCMP_VTD0     0x20 0x03 0x10
UMASK_DATA_REQ_OF_CPU_ATOMICCMP_VTD1     0x20 0x03 0x20
UMASK_DATA_REQ_OF_CPU_MSG_PART0          0x40 0x03 0x01
UMASK_DATA_REQ_OF_CPU_MSG_PART1          0x40 0x03 0x02
UMASK_DATA_REQ_OF_CPU_MSG_PART2          0x40 0x03 0x04
UMASK_DATA_REQ_OF_CPU_MSG_PART3          0x40 0x03 0x08
UMASK_DATA_REQ_OF_CPU_MSG_VTD0           0x40 0x03 0x10
UMASK_DATA_REQ_OF_CPU_MSG_VTD1           0x40 0x03 0x20

EVENT_LINK_NUM_CORR_ERR             0x0F IBOX
UMASK_LINK_NUM_CORR_ERR             0x00

EVENT_LINK_NUM_RETRIES              0x0E IBOX
UMASK_LINK_NUM_RETRIES              0x00

EVENT_MASK_MATCH                    0x21 IBOX
UMASK_MASK_MATCH                    0x00

EVENT_MASK_MATCH_AND                0x02 IBOX
UMASK_MASK_MATCH_AND_BUS0           0x01
UMASK_MASK_MATCH_AND_BUS1           0x02
UMASK_MASK_MATCH_AND_BUS0_NOT_BUS1  0x04
UMASK_MASK_MATCH_AND_BUS0_BUS1      0x08
UMASK_MASK_MATCH_AND_NOT_BUS0_BUS1  0x10
UMASK_MASK_MATCH_AND_NOT_BUS0_NOT_BUS1 0x20

EVENT_MASK_MATCH_OR                0x03 IBOX
UMASK_MASK_MATCH_OR_BUS0           0x01
UMASK_MASK_MATCH_OR_BUS1           0x02
UMASK_MASK_MATCH_OR_BUS0_NOT_BUS1  0x04
UMASK_MASK_MATCH_OR_BUS0_BUS1      0x08
UMASK_MASK_MATCH_OR_NOT_BUS0_BUS1  0x10
UMASK_MASK_MATCH_OR_NOT_BUS0_NOT_BUS1 0x20

EVENT_NOTHING                       0x00 IBOX
UMASK_NOTHING                       0x00

EVENT_SYMBOL_TIMES                  0x82 IBOX
UMASK_SYMBOL_TIMES                  0x00


EVENT_TXN_REQ_BY_CPU                    0xC1 IBOX
UMASK_TXN_REQ_BY_CPU_MEM_READ_PART0     0x04 0x03 0x01
UMASK_TXN_REQ_BY_CPU_MEM_READ_PART1     0x04 0x03 0x02
UMASK_TXN_REQ_BY_CPU_MEM_READ_PART2     0x04 0x03 0x04
UMASK_TXN_REQ_BY_CPU_MEM_READ_PART3     0x04 0x03 0x08
UMASK_TXN_REQ_BY_CPU_MEM_READ_VTD0      0x04 0x03 0x10
UMASK_TXN_REQ_BY_CPU_MEM_READ_VTD1      0x04 0x03 0x20
UMASK_TXN_REQ_BY_CPU_MEM_WRITE_PART0    0x01 0x03 0x01
UMASK_TXN_REQ_BY_CPU_MEM_WRITE_PART1    0x01 0x03 0x02
UMASK_TXN_REQ_BY_CPU_MEM_WRITE_PART2    0x01 0x03 0x04
UMASK_TXN_REQ_BY_CPU_MEM_WRITE_PART3    0x01 0x03 0x08
UMASK_TXN_REQ_BY_CPU_MEM_WRITE_VTD0     0x01 0x03 0x10
UMASK_TXN_REQ_BY_CPU_MEM_WRITE_VTD1     0x01 0x03 0x20
UMASK_TXN_REQ_BY_CPU_PEER_READ_PART0    0x08 0x03 0x01
UMASK_TXN_REQ_BY_CPU_PEER_READ_PART1    0x08 0x03 0x02
UMASK_TXN_REQ_BY_CPU_PEER_READ_PART2    0x08 0x03 0x04
UMASK_TXN_REQ_BY_CPU_PEER_READ_PART3    0x08 0x03 0x08
UMASK_TXN_REQ_BY_CPU_PEER_READ_VTD0     0x08 0x03 0x10
UMASK_TXN_REQ_BY_CPU_PEER_READ_VTD1     0x08 0x03 0x20
UMASK_TXN_REQ_BY_CPU_PEER_WRITE_PART0   0x02 0x03 0x01
UMASK_TXN_REQ_BY_CPU_PEER_WRITE_PART1   0x02 0x03 0x02
UMASK_TXN_REQ_BY_CPU_PEER_WRITE_PART2   0x02 0x03 0x04
UMASK_TXN_REQ_BY_CPU_PEER_WRITE_PART3   0x02 0x03 0x08
UMASK_TXN_REQ_BY_CPU_PEER_WRITE_VTD0    0x02 0x03 0x10
UMASK_TXN_REQ_BY_CPU_PEER_WRITE_VTD1    0x02 0x03 0x20
UMASK_TXN_REQ_BY_CPU_CFG_READ_PART0     0x40 0x03 0x01
UMASK_TXN_REQ_BY_CPU_CFG_READ_PART1     0x40 0x03 0x02
UMASK_TXN_REQ_BY_CPU_CFG_READ_PART2     0x40 0x03 0x04
UMASK_TXN_REQ_BY_CPU_CFG_READ_PART3     0x40 0x03 0x08
UMASK_TXN_REQ_BY_CPU_CFG_READ_VTD0      0x40 0x03 0x10
UMASK_TXN_REQ_BY_CPU_CFG_READ_VTD1      0x40 0x03 0x20
UMASK_TXN_REQ_BY_CPU_CFG_WRITE_PART0    0x10 0x03 0x01
UMASK_TXN_REQ_BY_CPU_CFG_WRITE_PART1    0x10 0x03 0x02
UMASK_TXN_REQ_BY_CPU_CFG_WRITE_PART2    0x10 0x03 0x04
UMASK_TXN_REQ_BY_CPU_CFG_WRITE_PART3    0x10 0x03 0x08
UMASK_TXN_REQ_BY_CPU_CFG_WRITE_VTD0     0x10 0x03 0x10
UMASK_TXN_REQ_BY_CPU_CFG_WRITE_VTD1     0x10 0x03 0x20
UMASK_TXN_REQ_BY_CPU_IO_READ_PART0      0x80 0x03 0x01
UMASK_TXN_REQ_BY_CPU_IO_READ_PART1      0x80 0x03 0x02
UMASK_TXN_REQ_BY_CPU_IO_READ_PART2      0x80 0x03 0x04
UMASK_TXN_REQ_BY_CPU_IO_READ_PART3      0x80 0x03 0x08
UMASK_TXN_REQ_BY_CPU_IO_READ_VTD0       0x80 0x03 0x10
UMASK_TXN_REQ_BY_CPU_IO_READ_VTD1       0x80 0x03 0x20
UMASK_TXN_REQ_BY_CPU_IO_WRITE_PART0     0x20 0x03 0x01
UMASK_TXN_REQ_BY_CPU_IO_WRITE_PART1     0x20 0x03 0x02
UMASK_TXN_REQ_BY_CPU_IO_WRITE_PART2     0x20 0x03 0x04
UMASK_TXN_REQ_BY_CPU_IO_WRITE_PART3     0x20 0x03 0x08
UMASK_TXN_REQ_BY_CPU_IO_WRITE_VTD0      0x20 0x03 0x10
UMASK_TXN_REQ_BY_CPU_IO_WRITE_VTD1      0x20 0x03 0x20

EVENT_TXN_REQ_OF_CPU                    0x84 IBOX
UMASK_TXN_REQ_OF_CPU_MEM_READ_PART0     0x04 0x03 0x01
UMASK_TXN_REQ_OF_CPU_MEM_READ_PART1     0x04 0x03 0x02
UMASK_TXN_REQ_OF_CPU_MEM_READ_PART2     0x04 0x03 0x04
UMASK_TXN_REQ_OF_CPU_MEM_READ_PART3     0x04 0x03 0x08
UMASK_TXN_REQ_OF_CPU_MEM_READ_VTD0      0x04 0x03 0x10
UMASK_TXN_REQ_OF_CPU_MEM_READ_VTD1      0x04 0x03 0x20
UMASK_TXN_REQ_OF_CPU_MEM_WRITE_PART0    0x01 0x03 0x01
UMASK_TXN_REQ_OF_CPU_MEM_WRITE_PART1    0x01 0x03 0x02
UMASK_TXN_REQ_OF_CPU_MEM_WRITE_PART2    0x01 0x03 0x04
UMASK_TXN_REQ_OF_CPU_MEM_WRITE_PART3    0x01 0x03 0x08
UMASK_TXN_REQ_OF_CPU_MEM_WRITE_VTD0     0x01 0x03 0x10
UMASK_TXN_REQ_OF_CPU_MEM_WRITE_VTD1     0x01 0x03 0x20
UMASK_TXN_REQ_OF_CPU_PEER_READ_PART0    0x08 0x03 0x01
UMASK_TXN_REQ_OF_CPU_PEER_READ_PART1    0x08 0x03 0x02
UMASK_TXN_REQ_OF_CPU_PEER_READ_PART2    0x08 0x03 0x04
UMASK_TXN_REQ_OF_CPU_PEER_READ_PART3    0x08 0x03 0x08
UMASK_TXN_REQ_OF_CPU_PEER_READ_VTD0     0x08 0x03 0x10
UMASK_TXN_REQ_OF_CPU_PEER_READ_VTD1     0x08 0x03 0x20
UMASK_TXN_REQ_OF_CPU_PEER_WRITE_PART0   0x02 0x03 0x01
UMASK_TXN_REQ_OF_CPU_PEER_WRITE_PART1   0x02 0x03 0x02
UMASK_TXN_REQ_OF_CPU_PEER_WRITE_PART2   0x02 0x03 0x04
UMASK_TXN_REQ_OF_CPU_PEER_WRITE_PART3   0x02 0x03 0x08
UMASK_TXN_REQ_OF_CPU_PEER_WRITE_VTD0    0x02 0x03 0x10
UMASK_TXN_REQ_OF_CPU_PEER_WRITE_VTD1    0x02 0x03 0x20
UMASK_TXN_REQ_OF_CPU_ATOMIC_PART0       0x10 0x03 0x01
UMASK_TXN_REQ_OF_CPU_ATOMIC_PART1       0x10 0x03 0x02
UMASK_TXN_REQ_OF_CPU_ATOMIC_PART2       0x10 0x03 0x04
UMASK_TXN_REQ_OF_CPU_ATOMIC_PART3       0x10 0x03 0x08
UMASK_TXN_REQ_OF_CPU_ATOMIC_VTD0        0x10 0x03 0x10
UMASK_TXN_REQ_OF_CPU_ATOMIC_VTD1        0x10 0x03 0x20
UMASK_TXN_REQ_OF_CPU_ATOMICCMP_PART0    0x20 0x03 0x01
UMASK_TXN_REQ_OF_CPU_ATOMICCMP_PART1    0x20 0x03 0x02
UMASK_TXN_REQ_OF_CPU_ATOMICCMP_PART2    0x20 0x03 0x04
UMASK_TXN_REQ_OF_CPU_ATOMICCMP_PART3    0x20 0x03 0x08
UMASK_TXN_REQ_OF_CPU_ATOMICCMP_VTD0     0x20 0x03 0x10
UMASK_TXN_REQ_OF_CPU_ATOMICCMP_VTD1     0x20 0x03 0x20
UMASK_TXN_REQ_OF_CPU_MSG_PART0          0x40 0x03 0x01
UMASK_TXN_REQ_OF_CPU_MSG_PART1          0x40 0x03 0x02
UMASK_TXN_REQ_OF_CPU_MSG_PART2          0x40 0x03 0x04
UMASK_TXN_REQ_OF_CPU_MSG_PART3          0x40 0x03 0x08
UMASK_TXN_REQ_OF_CPU_MSG_VTD0           0x40 0x03 0x10
UMASK_TXN_REQ_OF_CPU_MSG_VTD1           0x40 0x03 0x20

EVENT_VTD_ACCESS                        0x41 IBOX
UMASK_VTD_ACCESS_L4_PAGE_HIT            0x01
UMASK_VTD_ACCESS_CTXT_MISS              0x02
UMASK_VTD_ACCESS_L1_MISS                0x04
UMASK_VTD_ACCESS_L2_MISS                0x08
UMASK_VTD_ACCESS_L3_MISS                0x10
UMASK_VTD_ACCESS_TLB_MISS               0x20
UMASK_VTD_ACCESS_TLB_FULL               0x40
UMASK_VTD_ACCESS_TLB1_MISS              0x80

EVENT_VTD_OCCUPANCY                 0x40 IBOX
UMASK_VTD_OCCUPANCY                 0x00

EVENT_BANDWIDTH_PORT0_IN      0x00 IBAND0PI0|IBAND1PI0|IBAND2PI0|IBAND3PI0|IBAND4PI0|IBAND5PI0
UMASK_BANDWIDTH_PORT0_IN      0x00

EVENT_BANDWIDTH_PORT1_IN      0x00 IBAND0PI1|IBAND1PI1|IBAND2PI1|IBAND3PI1|IBAND4PI1|IBAND5PI1
UMASK_BANDWIDTH_PORT1_IN      0x00

EVENT_BANDWIDTH_PORT2_IN      0x00 IBAND0PI2|IBAND1PI2|IBAND2PI2|IBAND3PI2|IBAND4PI2|IBAND5PI2
UMASK_BANDWIDTH_PORT2_IN      0x00

EVENT_BANDWIDTH_PORT3_IN      0x00 IBAND0PI3|IBAND1PI3|IBAND2PI3|IBAND3PI3|IBAND4PI3|IBAND5PI3
UMASK_BANDWIDTH_PORT3_IN      0x00

EVENT_BANDWIDTH_PORT0_OUT      0x00 IBAND0PO0|IBAND1PO0|IBAND2PO0|IBAND3PO0|IBAND4PO0|IBAND5PO0
UMASK_BANDWIDTH_PORT0_OUT      0x00

EVENT_BANDWIDTH_PORT1_OUT      0x00 IBAND0PO1|IBAND1PO1|IBAND2PO1|IBAND3PO1|IBAND4PO1|IBAND5PO1
UMASK_BANDWIDTH_PORT1_OUT      0x00

EVENT_BANDWIDTH_PORT2_OUT      0x00 IBAND0PO2|IBAND1PO2|IBAND2PO2|IBAND3PO2|IBAND4PO2|IBAND5PO2
UMASK_BANDWIDTH_PORT2_OUT      0x00

EVENT_BANDWIDTH_PORT3_OUT      0x00 IBAND0PO3|IBAND1PO3|IBAND2PO3|IBAND3PO3|IBAND4PO3|IBAND5PO3
UMASK_BANDWIDTH_PORT3_OUT      0x00

EVENT_IUNIT_CLOCKTICKS          0x00 IBOX0CLK|IBOX1CLK|IBOX2CLK|IBOX3CLK|IBOX4CLK|IBOX5CLK
UMASK_IUNIT_CLOCKTICKS          0x00

EVENT_UTLILIZATION_PORT0_IN      0x00 IUTIL0PI0|IUTIL1PI0|IUTIL2PI0|IUTIL3PI0|IUTIL4PI0|IUTIL5PI0
UMASK_UTLILIZATION_PORT0_IN      0x00

EVENT_UTLILIZATION_PORT1_IN      0x00 IUTIL0PI1|IUTIL1PI1|IUTIL2PI1|IUTIL3PI1|IUTIL4PI1|IUTIL5PI1
UMASK_UTLILIZATION_PORT1_IN      0x00

EVENT_UTLILIZATION_PORT2_IN      0x00 IUTIL0PI2|IUTIL1PI2|IUTIL2PI2|IUTIL3PI2|IUTIL4PI2|IUTIL5PI2
UMASK_UTLILIZATION_PORT2_IN      0x00

EVENT_UTLILIZATION_PORT3_IN      0x00 IUTIL0PI3|IUTIL1PI3|IUTIL2PI3|IUTIL3PI3|IUTIL4PI3|IUTIL5PI3
UMASK_UTLILIZATION_PORT3_IN      0x00

EVENT_UTLILIZATION_PORT0_OUT      0x00 IUTIL0PO0|IUTIL1PO0|IUTIL2PO0|IUTIL3PO0|IUTIL4PO0|IUTIL5PO0
UMASK_UTLILIZATION_PORT0_OUT      0x00

EVENT_UTLILIZATION_PORT1_OUT      0x00 IUTIL0PO1|IUTIL1PO1|IUTIL2PO1|IUTIL3PO1|IUTIL4PO1|IUTIL5PO1
UMASK_UTLILIZATION_PORT1_OUT      0x00

EVENT_UTLILIZATION_PORT2_OUT      0x00 IUTIL0PO2|IUTIL1PO2|IUTIL2PO2|IUTIL3PO2|IUTIL4PO2|IUTIL5PO2
UMASK_UTLILIZATION_PORT2_OUT      0x00

EVENT_UTLILIZATION_PORT3_OUT      0x00 IUTIL0PO3|IUTIL1PO3|IUTIL2PO3|IUTIL3PO3|IUTIL4PO3|IUTIL5PO3
UMASK_UTLILIZATION_PORT3_OUT      0x00

EVENT_IRP_CLOCKTICKS            0x01 IRP
UMASK_IRP_CLOCKTICKS            0x00

EVENT_CACHE_TOTAL_OCCUPANCY         0x0F IRP
UMASK_CACHE_TOTAL_OCCUPANCY_ANY     0x01
UMASK_CACHE_TOTAL_OCCUPANCY_IV_Q    0x02
UMASK_CACHE_TOTAL_OCCUPANCY_MEM     0x04

EVENT_COHERENT_OPS              0x10 IRP
UMASK_COHERENT_OPS_PCIRDCUR     0x01
UMASK_COHERENT_OPS_CRD          0x02
UMASK_COHERENT_OPS_DRD          0x04
UMASK_COHERENT_OPS_RFO          0x08
UMASK_COHERENT_OPS_PCITOM       0x10
UMASK_COHERENT_OPS_PCIDCAHINT   0x20
UMASK_COHERENT_OPS_WBMTOI       0x40
UMASK_COHERENT_OPS_CLFLUSH      0x80

EVENT_FAF_FULL                  0x17 IRP
UMASK_FAF_FULL                  0x00

EVENT_FAF_INSERTS               0x18 IRP
UMASK_FAF_INSERTS               0x00

EVENT_FAF_OCCUPANCY             0x19 IRP
UMASK_FAF_OCCUPANCY             0x00

EVENT_FAF_TRANSACTIONS          0x16 IRP
UMASK_FAF_TRANSACTIONS          0x00

EVENT_IRP_ALL                   0x1E IRP
UMASK_IRP_ALL_INBOUND_INSERTS   0x01
UMASK_IRP_ALL_OUTBOUND_INSERTS  0x02

EVENT_MISC0                     0x1C IRP
UMASK_MISC0_FAST_REQ            0x01
UMASK_MISC0_FAST_REJ            0x02
UMASK_MISC0_FAST_2ND_RD_INSERT  0x04
UMASK_MISC0_FAST_2ND_WR_INSERT  0x08
UMASK_MISC0_FAST_2ND_ATOMIC_INSERT 0x10
UMASK_MISC0_FAST_FAST_XFER      0x20
UMASK_MISC0_FAST_PF_ACK_HINT    0x40
UMASK_MISC0_FAST_UNKNOWN        0x80

EVENT_MISC1                     0x1D IRP
UMASK_MISC1_SLOW_I              0x01
UMASK_MISC1_SLOW_S              0x02
UMASK_MISC1_SLOW_E              0x04
UMASK_MISC1_SLOW_M              0x08
UMASK_MISC1_LOST_FWD            0x10
UMASK_MISC1_SEC_RCVD_INVLD      0x20
UMASK_MISC1_SEC_RCVD_VLD        0x40

EVENT_P2P_INSERTS               0x14 IRP
UMASK_P2P_INSERTS               0x00

EVENT_P2P_OCCUPANCY             0x15 IRP
UMASK_P2P_OCCUPANCY             0x00

EVENT_P2P_TRANSACTIONS          0x13 IRP
UMASK_P2P_TRANSACTIONS_RD       0x01
UMASK_P2P_TRANSACTIONS_WR       0x02
UMASK_P2P_TRANSACTIONS_MSG      0x04
UMASK_P2P_TRANSACTIONS_CMPL     0x08
UMASK_P2P_TRANSACTIONS_REM      0x10
UMASK_P2P_TRANSACTIONS_REM_AND_TGT_MATCH       0x20
UMASK_P2P_TRANSACTIONS_LOC      0x40
UMASK_P2P_TRANSACTIONS_LOC_AND_TGT_MATCH       0x80

EVENT_SNOOP_RESP                0x12 IRP
UMASK_SNOOP_RESP_MISS_SNPCODE   0x11
UMASK_SNOOP_RESP_MISS_SNPDATA   0x21
UMASK_SNOOP_RESP_MISS_SNPINV    0x41
UMASK_SNOOP_RESP_MISS_SNPALL    0x71
UMASK_SNOOP_RESP_HIT_I_SNPCODE   0x12
UMASK_SNOOP_RESP_HIT_I_SNPDATA   0x22
UMASK_SNOOP_RESP_HIT_I_SNPINV    0x42
UMASK_SNOOP_RESP_HIT_I_SNPALL    0x72
UMASK_SNOOP_RESP_HIT_ES_SNPCODE   0x14
UMASK_SNOOP_RESP_HIT_ES_SNPDATA   0x24
UMASK_SNOOP_RESP_HIT_ES_SNPINV    0x44
UMASK_SNOOP_RESP_HIT_ES_SNPALL    0x74
UMASK_SNOOP_RESP_HIT_M_SNPCODE   0x18
UMASK_SNOOP_RESP_HIT_M_SNPDATA   0x28
UMASK_SNOOP_RESP_HIT_M_SNPINV    0x48
UMASK_SNOOP_RESP_HIT_M_SNPALL    0x78
UMASK_SNOOP_RESP_HIT_ESM_SNPCODE   0x1C
UMASK_SNOOP_RESP_HIT_ESM_SNPDATA   0x2C
UMASK_SNOOP_RESP_HIT_ESM_SNPINV    0x4C
UMASK_SNOOP_RESP_HIT_ESM_SNPALL    0x7C

EVENT_TRANSACTIONS              0x11 IRP
UMASK_TRANSACTIONS_READS        0x01
UMASK_TRANSACTIONS_WRITES       0x02
UMASK_TRANSACTIONS_RD_PREF      0x04
UMASK_TRANSACTIONS_WR_PREF      0x08
UMASK_TRANSACTIONS_ATOMIC       0x10
UMASK_TRANSACTIONS_OTHER        0x20
UMASK_TRANSACTIONS_ORDERINGQ    0x40

EVENT_TXC_AK_INSERTS            0x0B IRP
UMASK_TXC_AK_INSERTS            0x00

EVENT_TXC_BL_DRS_CYCLES_FULL    0x05 IRP
UMASK_TXC_BL_DRS_CYCLES_FULL    0x00

EVENT_TXC_BL_DRS_INSERTS        0x02 IRP
UMASK_TXC_BL_DRS_INSERTS        0x00

EVENT_TXC_BL_DRS_OCCUPANCY      0x08 IRP
UMASK_TXC_BL_DRS_OCCUPANCY      0x00

EVENT_TXC_BL_NCB_CYCLES_FULL    0x06 IRP
UMASK_TXC_BL_NCB_CYCLES_FULL    0x00

EVENT_TXC_BL_NCB_INSERTS        0x03 IRP
UMASK_TXC_BL_NCB_INSERTS        0x00

EVENT_TXC_BL_NCB_OCCUPANCY      0x09 IRP
UMASK_TXC_BL_NCB_OCCUPANCY      0x00

EVENT_TXC_BL_NCS_CYCLES_FULL    0x07 IRP
UMASK_TXC_BL_NCS_CYCLES_FULL    0x00

EVENT_TXC_BL_NCS_INSERTS        0x04 IRP
UMASK_TXC_BL_NCS_INSERTS        0x00

EVENT_TXC_BL_NCS_OCCUPANCY      0x0A IRP
UMASK_TXC_BL_NCS_OCCUPANCY      0x00

EVENT_TXR2_AD_STALL_CREDIT_CYCLES   0x1A IRP
UMASK_TXR2_AD_STALL_CREDIT_CYCLES   0x00

EVENT_TXR2_BL_STALL_CREDIT_CYCLES   0x1B IRP
UMASK_TXR2_BL_STALL_CREDIT_CYCLES   0x00

EVENT_TXS_DATA_INSERTS_NCB      0x0D IRP
UMASK_TXS_DATA_INSERTS_NCB      0x00

EVENT_TXS_DATA_INSERTS_NCS      0x0E IRP
UMASK_TXS_DATA_INSERTS_NCS      0x00

EVENT_TXS_REQUEST_OCCUPANCY     0x0C IRP
UMASK_TXS_REQUEST_OCCUPANCY     0x00


EVENT_AG0_AD_CRD_ACQUIRED       0x80 CBOX|M2M|RBOX|PBOX
UMASK_AG0_AD_CRD_ACQUIRED_TGR0  0x01
UMASK_AG0_AD_CRD_ACQUIRED_TGR1  0x02
UMASK_AG0_AD_CRD_ACQUIRED_TGR2  0x04
UMASK_AG0_AD_CRD_ACQUIRED_TGR3  0x08
UMASK_AG0_AD_CRD_ACQUIRED_TGR4  0x10
UMASK_AG0_AD_CRD_ACQUIRED_TGR5  0x20

EVENT_AG0_AD_CRD_OCCUPANCY       0x82 CBOX|M2M|RBOX|PBOX
UMASK_AG0_AD_CRD_OCCUPANCY_TGR0  0x01
UMASK_AG0_AD_CRD_OCCUPANCY_TGR1  0x02
UMASK_AG0_AD_CRD_OCCUPANCY_TGR2  0x04
UMASK_AG0_AD_CRD_OCCUPANCY_TGR3  0x08
UMASK_AG0_AD_CRD_OCCUPANCY_TGR4  0x10
UMASK_AG0_AD_CRD_OCCUPANCY_TGR5  0x20

EVENT_AG1_AD_CRD_ACQUIRED       0x84 CBOX|M2M|RBOX|PBOX
UMASK_AG1_AD_CRD_ACQUIRED_TGR0  0x01
UMASK_AG1_AD_CRD_ACQUIRED_TGR1  0x02
UMASK_AG1_AD_CRD_ACQUIRED_TGR2  0x04
UMASK_AG1_AD_CRD_ACQUIRED_TGR3  0x08
UMASK_AG1_AD_CRD_ACQUIRED_TGR4  0x10
UMASK_AG1_AD_CRD_ACQUIRED_TGR5  0x20

EVENT_AG1_AD_CRD_OCCUPANCY       0x86 CBOX|M2M|RBOX|PBOX
UMASK_AG1_AD_CRD_OCCUPANCY_TGR0  0x01
UMASK_AG1_AD_CRD_OCCUPANCY_TGR1  0x02
UMASK_AG1_AD_CRD_OCCUPANCY_TGR2  0x04
UMASK_AG1_AD_CRD_OCCUPANCY_TGR3  0x08
UMASK_AG1_AD_CRD_OCCUPANCY_TGR4  0x10
UMASK_AG1_AD_CRD_OCCUPANCY_TGR5  0x20

EVENT_AG0_BL_CRD_ACQUIRED       0x88 CBOX|M2M|RBOX|PBOX
UMASK_AG0_BL_CRD_ACQUIRED_TGR0  0x01
UMASK_AG0_BL_CRD_ACQUIRED_TGR1  0x02
UMASK_AG0_BL_CRD_ACQUIRED_TGR2  0x04
UMASK_AG0_BL_CRD_ACQUIRED_TGR3  0x08
UMASK_AG0_BL_CRD_ACQUIRED_TGR4  0x10
UMASK_AG0_BL_CRD_ACQUIRED_TGR5  0x20

EVENT_AG0_BL_CRD_OCCUPANCY       0x8A CBOX|M2M|RBOX|PBOX
UMASK_AG0_BL_CRD_OCCUPANCY_TGR0  0x01
UMASK_AG0_BL_CRD_OCCUPANCY_TGR1  0x02
UMASK_AG0_BL_CRD_OCCUPANCY_TGR2  0x04
UMASK_AG0_BL_CRD_OCCUPANCY_TGR3  0x08
UMASK_AG0_BL_CRD_OCCUPANCY_TGR4  0x10
UMASK_AG0_BL_CRD_OCCUPANCY_TGR5  0x20

EVENT_AG1_BL_CRD_ACQUIRED       0x8C CBOX|M2M|RBOX|PBOX
UMASK_AG1_BL_CRD_ACQUIRED_TGR0  0x01
UMASK_AG1_BL_CRD_ACQUIRED_TGR1  0x02
UMASK_AG1_BL_CRD_ACQUIRED_TGR2  0x04
UMASK_AG1_BL_CRD_ACQUIRED_TGR3  0x08
UMASK_AG1_BL_CRD_ACQUIRED_TGR4  0x10
UMASK_AG1_BL_CRD_ACQUIRED_TGR5  0x20

EVENT_AG1_BL_CRD_OCCUPANCY       0x8E CBOX|M2M|RBOX|PBOX
UMASK_AG1_BL_CRD_OCCUPANCY_TGR0  0x01
UMASK_AG1_BL_CRD_OCCUPANCY_TGR1  0x02
UMASK_AG1_BL_CRD_OCCUPANCY_TGR2  0x04
UMASK_AG1_BL_CRD_OCCUPANCY_TGR3  0x08
UMASK_AG1_BL_CRD_OCCUPANCY_TGR4  0x10
UMASK_AG1_BL_CRD_OCCUPANCY_TGR5  0x20

EVENT_CMS_CLOCKTICKS            0xC0 CBOX|M2M|RBOX|PBOX
UMASK_CMS_CLOCKTICKS            0x00

EVENT_EGRESS_ORDERING               0xAE CBOX|M2M|RBOX|PBOX
UMASK_EGRESS_ORDERING_IV_SNOOPGO_UP 0x01
UMASK_EGRESS_ORDERING_IV_SNOOPGO_DN 0x04

EVENT_FAST_ASSERTED             0xA5 CBOX|M2M|RBOX|PBOX
UMASK_FAST_ASSERTED_VERT        0x01
UMASK_FAST_ASSERTED_HORZ        0x02

EVENT_HORZ_RING_AD_IN_USE               0xA7 CBOX|M2M|RBOX|PBOX
UMASK_HORZ_RING_AD_IN_USE_LEFT_EVEN     0x01
UMASK_HORZ_RING_AD_IN_USE_LEFT_ODD      0x02
UMASK_HORZ_RING_AD_IN_USE_RIGHT_EVEN    0x04
UMASK_HORZ_RING_AD_IN_USE_RIGHT_ODD     0x08

EVENT_HORZ_RING_AK_IN_USE               0xA9 CBOX|M2M|RBOX|PBOX
UMASK_HORZ_RING_AK_IN_USE_LEFT_EVEN     0x01
UMASK_HORZ_RING_AK_IN_USE_LEFT_ODD      0x02
UMASK_HORZ_RING_AK_IN_USE_RIGHT_EVEN    0x04
UMASK_HORZ_RING_AK_IN_USE_RIGHT_ODD     0x08

EVENT_HORZ_RING_BL_IN_USE               0xAB CBOX|M2M|RBOX|PBOX
UMASK_HORZ_RING_BL_IN_USE_LEFT_EVEN     0x01
UMASK_HORZ_RING_BL_IN_USE_LEFT_ODD      0x02
UMASK_HORZ_RING_BL_IN_USE_RIGHT_EVEN    0x04
UMASK_HORZ_RING_BL_IN_USE_RIGHT_ODD     0x08

EVENT_HORZ_RING_IV_IN_USE               0xAB CBOX|M2M|RBOX|PBOX
UMASK_HORZ_RING_IV_IN_USE_LEFT          0x01
UMASK_HORZ_RING_IV_IN_USE_RIGHT         0x04

EVENT_RING_BOUNCES_HORZ                 0xA1 CBOX|M2M|RBOX|PBOX
UMASK_RING_BOUNCES_HORZ_AD              0x01
UMASK_RING_BOUNCES_HORZ_AK              0x02
UMASK_RING_BOUNCES_HORZ_BL              0x04
UMASK_RING_BOUNCES_HORZ_IV              0x08

EVENT_RING_BOUNCES_VERT                 0xA0 CBOX|M2M|RBOX|PBOX
UMASK_RING_BOUNCES_VERT_AD              0x01
UMASK_RING_BOUNCES_VERT_AK              0x02
UMASK_RING_BOUNCES_VERT_BL              0x04
UMASK_RING_BOUNCES_VERT_IV              0x08

EVENT_RING_SINK_STARVED_HORZ            0xA3 CBOX|M2M|RBOX|PBOX
UMASK_RING_SINK_STARVED_HORZ_AD         0x01
UMASK_RING_SINK_STARVED_HORZ_AK         0x02
UMASK_RING_SINK_STARVED_HORZ_BL         0x04
UMASK_RING_SINK_STARVED_HORZ_IV         0x08
UMASK_RING_SINK_STARVED_HORZ_AK_AG1     0x20

EVENT_RING_SINK_STARVED_VERT            0xA2 CBOX|M2M|RBOX|PBOX
UMASK_RING_SINK_STARVED_VERT_AD         0x01
UMASK_RING_SINK_STARVED_VERT_AK         0x02
UMASK_RING_SINK_STARVED_VERT_BL         0x04
UMASK_RING_SINK_STARVED_VERT_IV         0x08

EVENT_RING_SRC_THRTL                    0xA4 CBOX|M2M|RBOX|PBOX
UMASK_RING_SRC_THRTL                    0x00

EVENT_RXR_BUSY_STARVED                  0xB4 CBOX|M2M|RBOX|PBOX
UMASK_RXR_BUSY_STARVED_AD_BNC           0x01
UMASK_RXR_BUSY_STARVED_BL_BNC           0x04
UMASK_RXR_BUSY_STARVED_AD_CRD           0x10
UMASK_RXR_BUSY_STARVED_BL_CRD           0x40
UMASK_RXR_BUSY_STARVED_AD               0x11
UMASK_RXR_BUSY_STARVED_BL               0x44

EVENT_RXR_BYPASS                        0xB2 CBOX|M2M|RBOX|PBOX
UMASK_RXR_BYPASS_AD_BNC                 0x01
UMASK_RXR_BYPASS_AK_BNC                 0x02
UMASK_RXR_BYPASS_BL_BNC                 0x04
UMASK_RXR_BYPASS_IV_BNC                 0x08
UMASK_RXR_BYPASS_AD_CRD                 0x10
UMASK_RXR_BYPASS_BL_CRD                 0x40
UMASK_RXR_BYPASS_AD                     0x11
UMASK_RXR_BYPASS_BL                     0x44

EVENT_RXR_CRD_STARVED                   0xB3 CBOX|M2M|RBOX|PBOX
UMASK_RXR_CRD_STARVED_AD_BNC            0x01
UMASK_RXR_CRD_STARVED_AK_BNC            0x02
UMASK_RXR_CRD_STARVED_BL_BNC            0x04
UMASK_RXR_CRD_STARVED_IV_BNC            0x08
UMASK_RXR_CRD_STARVED_AD_CRD            0x10
UMASK_RXR_CRD_STARVED_BL_CRD            0x40
UMASK_RXR_CRD_STARVED_IFV               0x80
UMASK_RXR_CRD_STARVED_AD                0x11
UMASK_RXR_CRD_STARVED_BL                0x44

EVENT_RXR_INSERTS                        0xB1 CBOX|M2M|RBOX|PBOX
UMASK_RXR_INSERTS_AD_BNC                 0x01
UMASK_RXR_INSERTS_AK_BNC                 0x02
UMASK_RXR_INSERTS_BL_BNC                 0x04
UMASK_RXR_INSERTS_IV_BNC                 0x08
UMASK_RXR_INSERTS_AD_CRD                 0x10
UMASK_RXR_INSERTS_BL_CRD                 0x40
UMASK_RXR_INSERTS_AD                     0x11
UMASK_RXR_INSERTS_BL                     0x44

EVENT_RXR_OCCUPANCY                        0xB0 CBOX|M2M|RBOX|PBOX
UMASK_RXR_OCCUPANCY_AD_BNC                 0x01
UMASK_RXR_OCCUPANCY_AK_BNC                 0x02
UMASK_RXR_OCCUPANCY_BL_BNC                 0x04
UMASK_RXR_OCCUPANCY_IV_BNC                 0x08
UMASK_RXR_OCCUPANCY_AD_CRD                 0x10
UMASK_RXR_OCCUPANCY_BL_CRD                 0x40
UMASK_RXR_OCCUPANCY_AD                     0x11
UMASK_RXR_OCCUPANCY_BL                     0x44

EVENT_STALL_NO_TxR_HORZ_CRD_AD_AG0          0xD0 CBOX|M2M|RBOX|PBOX
UMASK_STALL_NO_TxR_HORZ_CRD_AD_AG0_TGR0     0x01
UMASK_STALL_NO_TxR_HORZ_CRD_AD_AG0_TGR1     0x02
UMASK_STALL_NO_TxR_HORZ_CRD_AD_AG0_TGR2     0x04
UMASK_STALL_NO_TxR_HORZ_CRD_AD_AG0_TGR3     0x08
UMASK_STALL_NO_TxR_HORZ_CRD_AD_AG0_TGR4     0x10
UMASK_STALL_NO_TxR_HORZ_CRD_AD_AG0_TGR5     0x20

EVENT_STALL_NO_TxR_HORZ_CRD_AD_AG1          0xD2 CBOX|M2M|RBOX|PBOX
UMASK_STALL_NO_TxR_HORZ_CRD_AD_AG1_TGR0     0x01
UMASK_STALL_NO_TxR_HORZ_CRD_AD_AG1_TGR1     0x02
UMASK_STALL_NO_TxR_HORZ_CRD_AD_AG1_TGR2     0x04
UMASK_STALL_NO_TxR_HORZ_CRD_AD_AG1_TGR3     0x08
UMASK_STALL_NO_TxR_HORZ_CRD_AD_AG1_TGR4     0x10
UMASK_STALL_NO_TxR_HORZ_CRD_AD_AG1_TGR5     0x20

EVENT_STALL_NO_TxR_HORZ_CRD_BL_AG0          0xD4 CBOX|M2M|RBOX|PBOX
UMASK_STALL_NO_TxR_HORZ_CRD_BL_AG0_TGR0     0x01
UMASK_STALL_NO_TxR_HORZ_CRD_BL_AG0_TGR1     0x02
UMASK_STALL_NO_TxR_HORZ_CRD_BL_AG0_TGR2     0x04
UMASK_STALL_NO_TxR_HORZ_CRD_BL_AG0_TGR3     0x08
UMASK_STALL_NO_TxR_HORZ_CRD_BL_AG0_TGR4     0x10
UMASK_STALL_NO_TxR_HORZ_CRD_BL_AG0_TGR5     0x20

EVENT_STALL_NO_TxR_HORZ_CRD_BL_AG1          0xD6 CBOX|M2M|RBOX|PBOX
UMASK_STALL_NO_TxR_HORZ_CRD_BL_AG1_TGR0     0x01
UMASK_STALL_NO_TxR_HORZ_CRD_BL_AG1_TGR1     0x02
UMASK_STALL_NO_TxR_HORZ_CRD_BL_AG1_TGR2     0x04
UMASK_STALL_NO_TxR_HORZ_CRD_BL_AG1_TGR3     0x08
UMASK_STALL_NO_TxR_HORZ_CRD_BL_AG1_TGR4     0x10
UMASK_STALL_NO_TxR_HORZ_CRD_BL_AG1_TGR5     0x20

EVENT_TxR_HORZ_ADS_USED                 0x9D CBOX|M2M|RBOX|PBOX
UMASK_TxR_HORZ_ADS_USED_AD_BNC          0x01
UMASK_TxR_HORZ_ADS_USED_AK_BNC          0x02
UMASK_TxR_HORZ_ADS_USED_BL_BNC          0x04
UMASK_TxR_HORZ_ADS_USED_AD_CRD          0x10
UMASK_TxR_HORZ_ADS_USED_BL_CRD          0x40
UMASK_TxR_HORZ_ADS_USED_AD              0x11
UMASK_TxR_HORZ_ADS_USED_BL              0x44

EVENT_TxR_HORZ_BYPASS                   0x9F CBOX|M2M|RBOX|PBOX
UMASK_TxR_HORZ_BYPASS_AD_BNC            0x01
UMASK_TxR_HORZ_BYPASS_AK_BNC            0x02
UMASK_TxR_HORZ_BYPASS_BL_BNC            0x04
UMASK_TxR_HORZ_BYPASS_IV_BNC            0x08
UMASK_TxR_HORZ_BYPASS_AD_CRD            0x10
UMASK_TxR_HORZ_BYPASS_BL_CRD            0x40
UMASK_TxR_HORZ_BYPASS_AD                0x11
UMASK_TxR_HORZ_BYPASS_BL                0x44

EVENT_TxR_HORZ_CYCLES_FULL                   0x96 CBOX|M2M|RBOX|PBOX
UMASK_TxR_HORZ_CYCLES_FULL_AD_BNC            0x01
UMASK_TxR_HORZ_CYCLES_FULL_AK_BNC            0x02
UMASK_TxR_HORZ_CYCLES_FULL_BL_BNC            0x04
UMASK_TxR_HORZ_CYCLES_FULL_IV_BNC            0x08
UMASK_TxR_HORZ_CYCLES_FULL_AD_CRD            0x10
UMASK_TxR_HORZ_CYCLES_FULL_BL_CRD            0x40
UMASK_TxR_HORZ_CYCLES_FULL_AD                0x11
UMASK_TxR_HORZ_CYCLES_FULL_BL                0x44

EVENT_TxR_HORZ_CYCLES_NE                   0x97 CBOX|M2M|RBOX|PBOX
UMASK_TxR_HORZ_CYCLES_NE_AD_BNC            0x01
UMASK_TxR_HORZ_CYCLES_NE_AK_BNC            0x02
UMASK_TxR_HORZ_CYCLES_NE_BL_BNC            0x04
UMASK_TxR_HORZ_CYCLES_NE_IV_BNC            0x08
UMASK_TxR_HORZ_CYCLES_NE_AD_CRD            0x10
UMASK_TxR_HORZ_CYCLES_NE_BL_CRD            0x40
UMASK_TxR_HORZ_CYCLES_NE_AD                0x11
UMASK_TxR_HORZ_CYCLES_NE_BL                0x44

EVENT_TxR_HORZ_INSERTS                   0x95 CBOX|M2M|RBOX|PBOX
UMASK_TxR_HORZ_INSERTS_AD_BNC            0x01
UMASK_TxR_HORZ_INSERTS_AK_BNC            0x02
UMASK_TxR_HORZ_INSERTS_BL_BNC            0x04
UMASK_TxR_HORZ_INSERTS_IV_BNC            0x08
UMASK_TxR_HORZ_INSERTS_AD_CRD            0x10
UMASK_TxR_HORZ_INSERTS_BL_CRD            0x40
UMASK_TxR_HORZ_INSERTS_AD                0x11
UMASK_TxR_HORZ_INSERTS_BL                0x44

EVENT_TxR_HORZ_NACK                   0x99 CBOX|M2M|RBOX|PBOX
UMASK_TxR_HORZ_NACK_AD_BNC            0x01
UMASK_TxR_HORZ_NACK_AK_BNC            0x02
UMASK_TxR_HORZ_NACK_BL_BNC            0x04
UMASK_TxR_HORZ_NACK_IV_BNC            0x08
UMASK_TxR_HORZ_NACK_AD_CRD            0x10
UMASK_TxR_HORZ_NACK_BL_CRD            0x40
UMASK_TxR_HORZ_NACK_AD                0x11
UMASK_TxR_HORZ_NACK_BL                0x44

EVENT_TxR_HORZ_OCCUPANCY                   0x94 CBOX|M2M|RBOX|PBOX
UMASK_TxR_HORZ_OCCUPANCY_AD_BNC            0x01
UMASK_TxR_HORZ_OCCUPANCY_AK_BNC            0x02
UMASK_TxR_HORZ_OCCUPANCY_BL_BNC            0x04
UMASK_TxR_HORZ_OCCUPANCY_IV_BNC            0x08
UMASK_TxR_HORZ_OCCUPANCY_AD_CRD            0x10
UMASK_TxR_HORZ_OCCUPANCY_BL_CRD            0x40
UMASK_TxR_HORZ_OCCUPANCY_AD                0x11
UMASK_TxR_HORZ_OCCUPANCY_BL                0x44

EVENT_TxR_HORZ_STARVED                   0x9B CBOX|M2M|RBOX|PBOX
UMASK_TxR_HORZ_STARVED_AD_BNC            0x01
UMASK_TxR_HORZ_STARVED_AK_BNC            0x02
UMASK_TxR_HORZ_STARVED_BL_BNC            0x04
UMASK_TxR_HORZ_STARVED_IV_BNC            0x08

EVENT_TxR_VERT_ADS_USED                 0x9C CBOX|M2M|RBOX|PBOX
UMASK_TxR_VERT_ADS_USED_AD_AG0          0x01
UMASK_TxR_VERT_ADS_USED_AK_AG0          0x02
UMASK_TxR_VERT_ADS_USED_BL_AG0          0x04
UMASK_TxR_VERT_ADS_USED_AD_AG1          0x10
UMASK_TxR_VERT_ADS_USED_AK_AG1          0x20
UMASK_TxR_VERT_ADS_USED_BL_AG1          0x40
UMASK_TxR_VERT_ADS_USED_AD              0x11
UMASK_TxR_VERT_ADS_USED_AK              0x22
UMASK_TxR_VERT_ADS_USED_BL              0x44

EVENT_TxR_VERT_BYPASS                 0x9E CBOX|M2M|RBOX|PBOX
UMASK_TxR_VERT_BYPASS_AD_AG0          0x01
UMASK_TxR_VERT_BYPASS_AK_AG0          0x02
UMASK_TxR_VERT_BYPASS_BL_AG0          0x04
UMASK_TxR_VERT_BYPASS_IV_AG1          0x08
UMASK_TxR_VERT_BYPASS_AD_AG1          0x10
UMASK_TxR_VERT_BYPASS_AK_AG1          0x20
UMASK_TxR_VERT_BYPASS_BL_AG1          0x40
UMASK_TxR_VERT_BYPASS_AD              0x11
UMASK_TxR_VERT_BYPASS_AK              0x22
UMASK_TxR_VERT_BYPASS_BL              0x44

EVENT_TxR_VERT_CYCLES_FULL                   0x92 CBOX|M2M|RBOX|PBOX
UMASK_TxR_VERT_CYCLES_FULL_AD_AG0            0x01
UMASK_TxR_VERT_CYCLES_FULL_AK_AG0            0x02
UMASK_TxR_VERT_CYCLES_FULL_BL_AG0            0x04
UMASK_TxR_VERT_CYCLES_FULL_IV_AG0            0x08
UMASK_TxR_VERT_CYCLES_FULL_AD_AG1            0x10
UMASK_TxR_VERT_CYCLES_FULL_AK_AG1            0x20
UMASK_TxR_VERT_CYCLES_FULL_BL_AG1            0x40
UMASK_TxR_VERT_CYCLES_FULL_AD                0x11
UMASK_TxR_VERT_CYCLES_FULL_AK                0x22
UMASK_TxR_VERT_CYCLES_FULL_BL                0x44

EVENT_TxR_VERT_CYCLES_NE                   0x93 CBOX|M2M|RBOX|PBOX
UMASK_TxR_VERT_CYCLES_NE_AD_AG0            0x01
UMASK_TxR_VERT_CYCLES_NE_AK_AG0            0x02
UMASK_TxR_VERT_CYCLES_NE_BL_AG0            0x04
UMASK_TxR_VERT_CYCLES_NE_IV_AG0            0x08
UMASK_TxR_VERT_CYCLES_NE_AD_AG1            0x10
UMASK_TxR_VERT_CYCLES_NE_AK_AG1            0x20
UMASK_TxR_VERT_CYCLES_NE_BL_AG1            0x40
UMASK_TxR_VERT_CYCLES_NE_AD                0x11
UMASK_TxR_VERT_CYCLES_NE_AK                0x22
UMASK_TxR_VERT_CYCLES_NE_BL                0x44

EVENT_TxR_VERT_INSERTS                      0x91 CBOX|M2M|RBOX|PBOX
UMASK_TxR_VERT_INSERTS_AD_AG0               0x01
UMASK_TxR_VERT_INSERTS_AK_AG0               0x02
UMASK_TxR_VERT_INSERTS_BL_AG0               0x04
UMASK_TxR_VERT_INSERTS_IV_AG0               0x08
UMASK_TxR_VERT_INSERTS_AD_AG1               0x10
UMASK_TxR_VERT_INSERTS_AK_AG1               0x20
UMASK_TxR_VERT_INSERTS_BL_AG1               0x40
UMASK_TxR_VERT_INSERTS_AD                   0x11
UMASK_TxR_VERT_INSERTS_AK                   0x22
UMASK_TxR_VERT_INSERTS_BL                   0x44

EVENT_TxR_VERT_NACK                      0x98 CBOX|M2M|RBOX|PBOX
UMASK_TxR_VERT_NACK_AD_AG0               0x01
UMASK_TxR_VERT_NACK_AK_AG0               0x02
UMASK_TxR_VERT_NACK_BL_AG0               0x04
UMASK_TxR_VERT_NACK_IV_AG0               0x08
UMASK_TxR_VERT_NACK_AD_AG1               0x10
UMASK_TxR_VERT_NACK_AK_AG1               0x20
UMASK_TxR_VERT_NACK_BL_AG1               0x40
UMASK_TxR_VERT_NACK_AD                   0x11
UMASK_TxR_VERT_NACK_AK                   0x22
UMASK_TxR_VERT_NACK_BL                   0x44

EVENT_TxR_VERT_OCCUPANCY                      0x90 CBOX|M2M|RBOX|PBOX
UMASK_TxR_VERT_OCCUPANCY_AD_AG0               0x01
UMASK_TxR_VERT_OCCUPANCY_AK_AG0               0x02
UMASK_TxR_VERT_OCCUPANCY_BL_AG0               0x04
UMASK_TxR_VERT_OCCUPANCY_IV_AG0               0x08
UMASK_TxR_VERT_OCCUPANCY_AD_AG1               0x10
UMASK_TxR_VERT_OCCUPANCY_AK_AG1               0x20
UMASK_TxR_VERT_OCCUPANCY_BL_AG1               0x40
UMASK_TxR_VERT_OCCUPANCY_AD                   0x11
UMASK_TxR_VERT_OCCUPANCY_AK                   0x22
UMASK_TxR_VERT_OCCUPANCY_BL                   0x44

EVENT_TxR_VERT_STARVED                      0x9A CBOX|M2M|RBOX|PBOX
UMASK_TxR_VERT_STARVED_AD_AG0               0x01
UMASK_TxR_VERT_STARVED_AK_AG0               0x02
UMASK_TxR_VERT_STARVED_BL_AG0               0x04
UMASK_TxR_VERT_STARVED_IV_AG0               0x08
UMASK_TxR_VERT_STARVED_AD_AG1               0x10
UMASK_TxR_VERT_STARVED_AK_AG1               0x20
UMASK_TxR_VERT_STARVED_BL_AG1               0x40
UMASK_TxR_VERT_STARVED_AD                   0x11
UMASK_TxR_VERT_STARVED_AK                   0x22
UMASK_TxR_VERT_STARVED_BL                   0x44

EVENT_VERT_RING_AD_IN_USE               0xA6 CBOX|M2M|RBOX|PBOX
UMASK_VERT_RING_AD_IN_USE_UP_EVEN       0x01
UMASK_VERT_RING_AD_IN_USE_UP_ODD        0x02
UMASK_VERT_RING_AD_IN_USE_DN_EVEN       0x04
UMASK_VERT_RING_AD_IN_USE_DN_ODD        0x08

EVENT_VERT_RING_AK_IN_USE               0xA8 CBOX|M2M|RBOX|PBOX
UMASK_VERT_RING_AK_IN_USE_UP_EVEN       0x01
UMASK_VERT_RING_AK_IN_USE_UP_ODD        0x02
UMASK_VERT_RING_AK_IN_USE_DN_EVEN       0x04
UMASK_VERT_RING_AK_IN_USE_DN_ODD        0x08

EVENT_VERT_RING_BL_IN_USE               0xAA CBOX|M2M|RBOX|PBOX
UMASK_VERT_RING_BL_IN_USE_UP_EVEN       0x01
UMASK_VERT_RING_BL_IN_USE_UP_ODD        0x02
UMASK_VERT_RING_BL_IN_USE_DN_EVEN       0x04
UMASK_VERT_RING_BL_IN_USE_DN_ODD        0x08

EVENT_VERT_RING_IV_IN_USE               0xAC CBOX|M2M|RBOX|PBOX
UMASK_VERT_RING_IV_IN_USE_UP            0x01
UMASK_VERT_RING_IV_IN_USE_DN            0x04





