# =======================================================================================
#
#      Filename:  perfmon_icelakeX_events.txt
#
#      Description:  Event list for Intel Icelake X
#
#      Version:   <VERSION>
#      Released:  <DATE>
#
#      Author:   Thomas Gruber (tr), thomas.roehl@googlemail.com
#      Project:  likwid
#
#      Copyright (C) 2015 RRZE, University Erlangen-Nuremberg
#
#      This program is free software: you can redistribute it and/or modify it under
#      the terms of the GNU General Public License as published by the Free Software
#      Foundation, either version 3 of the License, or (at your option) any later
#      version.
#
#      This program is distributed in the hope that it will be useful, but WITHOUT ANY
#      WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
#      PARTICULAR PURPOSE.  See the GNU General Public License for more details.
#
#      You should have received a copy of the GNU General Public License along with
#      this program.  If not, see <http://www.gnu.org/licenses/>.
#
# =======================================================================================

EVENT_TEMP_CORE          0x00   TMP0
UMASK_TEMP_CORE          0x00

EVENT_PWR_PKG_ENERGY          0x02   PWR0
UMASK_PWR_PKG_ENERGY          0x00

EVENT_PWR_PP0_ENERGY          0x01   PWR1
UMASK_PWR_PP0_ENERGY          0x00

EVENT_PWR_PP1_ENERGY          0x04   PWR2
UMASK_PWR_PP1_ENERGY          0x00

EVENT_PWR_DRAM_ENERGY          0x03   PWR3
UMASK_PWR_DRAM_ENERGY          0x00

EVENT_PWR_PLATFORM_ENERGY          0x05   PWR4
UMASK_PWR_PLATFORM_ENERGY          0x00

EVENT_VOLTAGE_CORE          0x00   VTG0
UMASK_VOLTAGE_CORE          0x00

EVENT_INSTR_RETIRED              0x00   FIXC0
UMASK_INSTR_RETIRED_ANY          0x00

EVENT_CPU_CLK_UNHALTED           0x00   FIXC1
UMASK_CPU_CLK_UNHALTED_CORE      0x00

EVENT_CPU_CLK_UNHALTED           0x00   FIXC2
UMASK_CPU_CLK_UNHALTED_REF       0x00

EVENT_TOPDOWN_SLOTS                0x00   FIXC3
UMASK_TOPDOWN_SLOTS                0x00

EVENT_RETIRING                 0x00 TMA0
UMASK_RETIRING                 0x00

EVENT_BAD_SPECULATION          0x00 TMA1
UMASK_BAD_SPECULATION          0x00

EVENT_FRONTEND_BOUND           0x00 TMA2
UMASK_FRONTEND_BOUND           0x00

EVENT_BACKEND_BOUND            0x00 TMA3
UMASK_BACKEND_BOUND            0x00

EVENT_LD_BLOCKS                         0x03 PMC
UMASK_LD_BLOCKS_STORE_FORWARD           0x02
UMASK_LD_BLOCKS_NO_SR                   0x08

EVENT_LD_BLOCKS_PARTIAL_ADDRESS_ALIAS   0x07 PMC
UMASK_LD_BLOCKS_PARTIAL_ADDRESS_ALIAS   0x01

EVENT_DTLB_LOAD_MISSES                      0x08 PMC
# Not documented for Icelake but available for Skylake and counting
UMASK_DTLB_LOAD_MISSES_CAUSES_A_WALK        0x01
UMASK_DTLB_LOAD_MISSES_WALK_PENDING         0x10
UMASK_DTLB_LOAD_MISSES_STLB_HIT             0x20
UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED       0x0E
UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED_4K    0x02
UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED_2M_4M 0x04
#UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED_1G    0x08
DEFAULT_OPTIONS_DTLB_LOAD_MISSES_WALK_ACTIVE EVENT_OPTION_THRESHOLD=0x1
UMASK_DTLB_LOAD_MISSES_WALK_ACTIVE          0x10

EVENT_DTLB_STORE_MISSES                      0x49 PMC
# Not documented for Icelake but available for Skylake and counting
UMASK_DTLB_STORE_MISSES_CAUSES_A_WALK        0x01
UMASK_DTLB_STORE_MISSES_WALK_PENDING         0x10
UMASK_DTLB_STORE_MISSES_STLB_HIT             0x20
UMASK_DTLB_STORE_MISSES_WALK_COMPLETED       0x0E
UMASK_DTLB_STORE_MISSES_WALK_COMPLETED_4K    0x02
UMASK_DTLB_STORE_MISSES_WALK_COMPLETED_2M_4M 0x04
#UMASK_DTLB_STORE_MISSES_WALK_COMPLETED_1G    0x08
DEFAULT_OPTIONS_DTLB_STORE_MISSES_WALK_ACTIVE EVENT_OPTION_THRESHOLD=0x1
UMASK_DTLB_STORE_MISSES_WALK_ACTIVE          0x10

EVENT_INT_MISC                          0x0D PMC
UMASK_INT_MISC_RECOVERY_CYCLES          0x01
DEFAULT_OPTIONS_INT_MISC_ALL_RECOVERY_CYCLES EVENT_OPTION_THRESHOLD=0x1
UMASK_INT_MISC_ALL_RECOVERY_CYCLES      0x03
UMASK_INT_MISC_UOP_DROPPING             0x10
UMASK_INT_MISC_CLEAR_RESTEER_CYCLES     0x80

EVENT_UOPS_ISSUED                       0x0E  PMC
UMASK_UOPS_ISSUED_ANY                   0x01
DEFAULT_OPTIONS_UOPS_ISSUED_STALL_CYCLES EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=1
UMASK_UOPS_ISSUED_STALL_CYCLES          0x01
UMASK_UOPS_ISSUED_VECTOR_WIDTH_MISMATCH 0x02

EVENT_ARITH_DIVIDER                     0x14 PMC
DEFAULT_OPTIONS_ARITH_DIVIDER_ACTIVE    EVENT_OPTION_THRESHOLD=0x1
UMASK_ARITH_DIVIDER_ACTIVE              0x01
# Added by Thomas Gruber
DEFAULT_OPTIONS_ARITH_DIVIDER_COUNT     EVENT_OPTION_EDGE=0x1,EVENT_OPTION_THRESHOLD=0x1
UMASK_ARITH_DIVIDER_COUNT               0x01

EVENT_L2_RQSTS                          0x24 PMC
UMASK_L2_RQSTS_DEMAND_DATA_RD_MISS      0x21
UMASK_L2_RQSTS_RFO_MISS                 0x22
UMASK_L2_RQSTS_CODE_RD_MISS             0x24
UMASK_L2_RQSTS_ALL_DEMAND_MISS          0x27
UMASK_L2_RQSTS_SWPF_MISS                0x28
UMASK_L2_RQSTS_DEMAND_DATA_RD_HIT       0xC1
UMASK_L2_RQSTS_RFO_HIT                  0xC2
UMASK_L2_RQSTS_CODE_RD_HIT              0xC4
UMASK_L2_RQSTS_SWPF_HIT                 0xC8
UMASK_L2_RQSTS_ALL_DEMAND_DATA_RD       0xE1
UMASK_L2_RQSTS_ALL_RFO                  0xE2
UMASK_L2_RQSTS_ALL_CODE_RD              0xE4
UMASK_L2_RQSTS_ALL_DEMAND_REFERENCES    0xE7
UMASK_L2_RQSTS_MISS                     0x2F
UMASK_L2_RQSTS_REFERENCES               0xEF

EVENT_CORE_POWER                        0x28 PMC
UMASK_CORE_POWER_LVL0_TURBO_LICENSE     0x07
UMASK_CORE_POWER_LVL1_TURBO_LICENSE     0x18
UMASK_CORE_POWER_LVL2_TURBO_LICENSE     0x20

EVENT_LONGEST_LAT_CACHE                 0x2E PMC
UMASK_LONGEST_LAT_CACHE_MISS            0x01

EVENT_SW_PREFETCH_ACCESS            0x32 PMC
UMASK_SW_PREFETCH_ACCESS_NTA        0x01
UMASK_SW_PREFETCH_ACCESS_T0         0x02
UMASK_SW_PREFETCH_ACCESS_T1_T2      0x04
UMASK_SW_PREFETCH_ACCESS_PREFETCHW  0x08

EVENT_CPU_CLOCK_UNHALTED                    0x3C   PMC
UMASK_CPU_CLOCK_UNHALTED_THREAD_P           0x00
UMASK_CPU_CLOCK_UNHALTED_REF_XCLK           0x01
UMASK_CPU_CLOCK_UNHALTED_ONE_THREAD_ACTIVE  0x02
UMASK_CPU_CLOCK_UNHALTED_REF_DISTRIBUTED    0x08
# Added by Thomas Gruber: Idea is to count also in halted state
DEFAULT_OPTIONS_CPU_CLOCK_UNHALTED_TOTAL_CYCLES EVENT_OPTION_THRESHOLD=0xA,EVENT_OPTION_INVERT=1
UMASK_CPU_CLOCK_UNHALTED_TOTAL_CYCLES       0x00

EVENT_L1D_PEND_MISS                     0x48 PMC
UMASK_L1D_PEND_MISS_PENDING             0x01
UMASK_L1D_PEND_MISS_FB_FULL             0x02
DEFAULT_OPTIONS_L1D_PEND_MISS_PENDING_CYCLES EVENT_OPTION_THRESHOLD=0x1
UMASK_L1D_PEND_MISS_PENDING_CYCLES      0x01
DEFAULT_OPTIONS_L1D_PEND_MISS_FB_FULL_PERIODS EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_EDGE=1
UMASK_L1D_PEND_MISS_FB_FULL_PERIODS     0x02
UMASK_L1D_PEND_MISS_L2_STALL            0x04

EVENT_LOAD_HIT_PREFETCH                 0x4C PMC
UMASK_LOAD_HIT_PREFETCH_SWPF            0x01

EVENT_L1D                               0x51 PMC
UMASK_L1D_REPLACEMENT                   0x01
# Didn't test the L1D_M_EVICT event yet but highly likely to work
#UMASK_L1D_M_EVICT                       0x04

EVENT_TX_MEM                                                0x54 PMC
UMASK_TX_MEM_ABORT_CONFLICT                                 0x01
UMASK_TX_MEM_ABORT_CAPACITY_WRITE                           0x02
UMASK_TX_MEM_ABORT_CAPACITY_READ                            0x80
UMASK_TX_MEM_ABORT_HLE_STORE_TO_ELIDED_LOCK                 0x04
UMASK_TX_MEM_ABORT_HLE_ELISION_BUFFER_NOT_EMPTY             0x08
UMASK_TX_MEM_ABORT_HLE_ELISION_BUFFER_MISMATCH              0x10
UMASK_TX_MEM_ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT 0x20
UMASK_TX_MEM_ABORT_HLE_ELISION_BUFFER_FULL                  0x40

EVENT_TX_EXEC                           0x5D PMC
UMASK_TX_EXEC_MISC2                     0x02
UMASK_TX_EXEC_MISC3                     0x04

EVENT_RS_EVENTS_EMPTY                   0x5E PMC
UMASK_RS_EVENTS_EMPTY_CYCLES            0x01
DEFAULT_OPTIONS_RS_EVENTS_EMPTY_END     EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=0x1,EVENT_OPTION_EDGE=0x1
UMASK_RS_EVENTS_EMPTY_END               0x01

EVENT_OFFCORE_REQUESTS_OUTSTANDING                                          0x60 PMC
UMASK_OFFCORE_REQUESTS_OUTSTANDING_DEMAND_DATA_RD                           0x01
#DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_DATA_RD EVENT_OPTION_THRESHOLD=0x1
#UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_DATA_RD               0x01
#DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_DATA_RD_GE_6 EVENT_OPTION_THRESHOLD=0x6
#UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_DATA_RD_GE_6          0x01
#UMASK_OFFCORE_REQUESTS_OUTSTANDING_DEMAND_CODE_RD                           0x02
#DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_CODE_RD EVENT_OPTION_THRESHOLD=0x1
#UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_CODE_RD               0x02
UMASK_OFFCORE_REQUESTS_OUTSTANDING_DEMAND_RFO                               0x04
DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_RFO EVENT_OPTION_THRESHOLD=0x1
UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_RFO                   0x04
UMASK_OFFCORE_REQUESTS_OUTSTANDING_ALL_DATA_RD                              0x08
DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DATA_RD EVENT_OPTION_THRESHOLD=0x1
UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DATA_RD                      0x08
DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_L3_MISS_DEMAND_DATA_RD EVENT_OPTION_THRESHOLD=0x1
UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_L3_MISS_DEMAND_DATA_RD       0x10

EVENT_IDQ                               0x79 PMC
UMASK_IDQ_MITE_UOPS                     0x04
DEFAULT_OPTIONS_IDQ_MITE_CYCLES_OK EVENT_OPTION_THRESHOLD=0x5
UMASK_IDQ_MITE_CYCLES_OK                0x04
DEFAULT_OPTIONS_IDQ_MITE_CYCLES_ANY EVENT_OPTION_THRESHOLD=0x1 # Should this also be 1 for Tigerlake?
UMASK_IDQ_MITE_CYCLES_ANY               0x04
UMASK_IDQ_DSB_UOPS                      0x08
DEFAULT_OPTIONS_IDQ_DSB_CYCLES_OK EVENT_OPTION_THRESHOLD=0x5
UMASK_IDQ_DSB_CYCLES_OK                 0x08
DEFAULT_OPTIONS_IDQ_DSB_CYCLES_ANY EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_DSB_CYCLES_ANY                0x08
UMASK_IDQ_MS_UOPS                       0x30
DEFAULT_OPTIONS_IDQ_MS_SWITCHES EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_EDGE=1
UMASK_IDQ_MS_SWITCHES                   0x30
DEFAULT_OPTIONS_IDQ_MITE_CYCLES_ANY EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_MS_CYCLES_ANY                 0x30

EVENT_ICACHE_16B_IFDATA_STALL    0x80 PMC
UMASK_ICACHE_16B_IFDATA_STALL    0x04

EVENT_ICACHE_64B_IFTAG           0x83 PMC
UMASK_ICACHE_64B_IFTAG_HIT       0x01
UMASK_ICACHE_64B_IFTAG_MISS      0x02
# Added by Thomas Gruber to cover HIT & MISS
UMASK_ICACHE_64B_IFTAG_ALL       0x03
UMASK_ICACHE_64B_IFTAG_STALL     0x04

EVENT_ITLB_MISSES                       0x85 PMC
# Not documented for Icelake but available for Skylake and counting
UMASK_ITLB_MISSES_CAUSES_A_WALK         0x01
UMASK_ITLB_MISSES_WALK_PENDING          0x10
UMASK_ITLB_MISSES_STLB_HIT              0x20
UMASK_ITLB_MISSES_WALK_COMPLETED        0x0E
UMASK_ITLB_MISSES_WALK_COMPLETED_4K     0x02
UMASK_ITLB_MISSES_WALK_COMPLETED_2M_4M  0x04
#UMASK_ITLB_MISSES_WALK_COMPLETED_1G     0x08
DEFAULT_OPTIONS_ITLB_MISSES_WALK_ACTIVE EVENT_OPTION_THRESHOLD=0x1
UMASK_ITLB_MISSES_WALK_ACTIVE           0x10

EVENT_ILD_STALL_LCP                 0x87 PMC
UMASK_ILD_STALL_LCP                 0x01

EVENT_IDQ_UOPS_NOT_DELIVERED            0x9C PMC
UMASK_IDQ_UOPS_NOT_DELIVERED_CORE       0x01
DEFAULT_OPTIONS_IDQ_UOPS_NOT_DELIVERED_CYCLES_0_UOPS_DELIV_CORE EVENT_OPTION_THRESHOLD=0x5
UMASK_IDQ_UOPS_NOT_DELIVERED_CYCLES_0_UOPS_DELIV_CORE 0x01
DEFAULT_OPTIONS_IDQ_UOPS_NOT_DELIVERED_CYCLES_FE_WAS_OK EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=0x1
UMASK_IDQ_UOPS_NOT_DELIVERED_CYCLES_FE_WAS_OK 0x01

EVENT_UOPS_DISPATCHED_PORT              0xA1 PMC
UMASK_UOPS_DISPATCHED_PORT_PORT_0       0x01
UMASK_UOPS_DISPATCHED_PORT_PORT_1       0x02
UMASK_UOPS_DISPATCHED_PORT_PORT_2_3     0x04
UMASK_UOPS_DISPATCHED_PORT_PORT_4_9     0x10
UMASK_UOPS_DISPATCHED_PORT_PORT_5       0x20
UMASK_UOPS_DISPATCHED_PORT_PORT_6       0x40
UMASK_UOPS_DISPATCHED_PORT_PORT_7_8     0x80

EVENT_RESOURCE_STALLS                   0xA2 PMC
# Not in offcial event list but available for SKX with same event and umask
UMASK_RESOURCE_STALLS_ANY               0x01
UMASK_RESOURCE_STALLS_SCOREBOARD        0x02
UMASK_RESOURCE_STALLS_SB                0x08

EVENT_CYCLE_ACTIVITY                    0xA3 PMC
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_L1D_MISS EVENT_OPTION_THRESHOLD=0x8
UMASK_CYCLE_ACTIVITY_CYCLES_L1D_MISS    0x08
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_L2_MISS EVENT_OPTION_THRESHOLD=0x1
UMASK_CYCLE_ACTIVITY_CYCLES_L2_MISS     0x01
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_L3_MISS EVENT_OPTION_THRESHOLD=0x2
UMASK_CYCLE_ACTIVITY_CYCLES_L3_MISS     0x02
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_MEM_ANY EVENT_OPTION_THRESHOLD=0x10
UMASK_CYCLE_ACTIVITY_CYCLES_MEM_ANY     0x10
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_NO_EXECUTE EVENT_OPTION_THRESHOLD=0x04
UMASK_CYCLE_ACTIVITY_CYCLES_NO_EXECUTE  0x04
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_TOTAL EVENT_OPTION_THRESHOLD=0x4
UMASK_CYCLE_ACTIVITY_STALLS_TOTAL       0x04
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_L1D_MISS EVENT_OPTION_THRESHOLD=0xC
UMASK_CYCLE_ACTIVITY_STALLS_L1D_MISS    0x0C
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_L2_MISS EVENT_OPTION_THRESHOLD=0x5
UMASK_CYCLE_ACTIVITY_STALLS_L2_MISS     0x05
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_L3_MISS EVENT_OPTION_THRESHOLD=0x6
UMASK_CYCLE_ACTIVITY_STALLS_L3_MISS     0x06
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_MEM_ANY EVENT_OPTION_THRESHOLD=0x14
UMASK_CYCLE_ACTIVITY_STALLS_MEM_ANY     0x14

EVENT_TOPDOWN                           0xA4 PMC
UMASK_TOPDOWN_SLOTS_P                   0x01
UMASK_TOPDOWN_BACKEND_BOUND_SLOTS       0x02
UMASK_TOPDOWN_BR_MISPREDICT_SLOTS       0x08

EVENT_EXE_ACTIVITY                      0xA6 PMC
UMASK_EXE_ACTIVITY_1_PORTS_UTIL         0x02
UMASK_EXE_ACTIVITY_2_PORTS_UTIL         0x04
UMASK_EXE_ACTIVITY_3_PORTS_UTIL         0x08
UMASK_EXE_ACTIVITY_4_PORTS_UTIL         0x10
#UMASK_EXE_ACTIVITY_BOUND_ON_LOADS       0x21
UMASK_EXE_ACTIVITY_BOUND_ON_STORES      0x40
UMASK_EXE_ACTIVITY_EXE_BOUND_0_PORTS    0x80

EVENT_LSD_UOPS                          0xA8   PMC
UMASK_LSD_UOPS                          0x01
DEFAULT_OPTIONS_LSD_UOPS_CYCLES_ACTIVE EVENT_OPTION_THRESHOLD=0x01
UMASK_LSD_UOPS_CYCLES_ACTIVE            0x01
DEFAULT_OPTIONS_LSD_UOPS_CYCLES_OK EVENT_OPTION_THRESHOLD=0x05
UMASK_LSD_UOPS_CYCLES_OK                0x01

EVENT_DSB2MITE_SWITCHES_PENALTY_CYCLES 0xAB PMC
UMASK_DSB2MITE_SWITCHES_PENALTY_CYCLES 0x02
DEFAULT_OPTIONS_DSB2MITE_SWITCHES_PENALTY_COUNT EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_EDGE=1
UMASK_DSB2MITE_SWITCHES_PENALTY_COUNT  0x02

EVENT_OFFCORE_REQUESTS                          0xB0 PMC
UMASK_OFFCORE_REQUESTS_DEMAND_DATA_RD           0x01
UMASK_OFFCORE_REQUESTS_DEMAND_RFO               0x04
UMASK_OFFCORE_REQUESTS_ALL_DATA_RD              0x08
UMASK_OFFCORE_REQUESTS_L3_MISS_DEMAND_DATA_RD   0x10
UMASK_OFFCORE_REQUESTS_ALL_REQUESTS             0x80

EVENT_UOPS_EXECUTED                         0xB1   PMC
UMASK_UOPS_EXECUTED_THREAD                  0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_STALL_CYCLES EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=1
UMASK_UOPS_EXECUTED_STALL_CYCLES            0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_1 EVENT_OPTION_THRESHOLD=0x1
UMASK_UOPS_EXECUTED_CYCLES_GE_1             0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_2 EVENT_OPTION_THRESHOLD=0x2
UMASK_UOPS_EXECUTED_CYCLES_GE_2             0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_3 EVENT_OPTION_THRESHOLD=0x3
UMASK_UOPS_EXECUTED_CYCLES_GE_3             0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_4 EVENT_OPTION_THRESHOLD=0x4
UMASK_UOPS_EXECUTED_CYCLES_GE_4             0x01
UMASK_UOPS_EXECUTED_CORE                    0x02
#DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_STALL_CYCLES EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=1
#UMASK_UOPS_EXECUTED_CORE_STALL_CYCLES      0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_1 EVENT_OPTION_THRESHOLD=0x1
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_1        0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_2 EVENT_OPTION_THRESHOLD=0x2
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_2        0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_3 EVENT_OPTION_THRESHOLD=0x3
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_3        0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_4 EVENT_OPTION_THRESHOLD=0x4
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_4        0x02
UMASK_UOPS_EXECUTED_X87                     0x10

EVENT_TLB_FLUSH                         0xBD PMC
UMASK_TLB_FLUSH_DTLB_THREAD             0x01
UMASK_TLB_FLUSH_STLB_ANY                0x20

EVENT_INST_RETIRED                      0xC0 PMC
UMASK_INST_RETIRED_ANY                  0x00
UMASK_INST_RETIRED_ANY_P                0x00
UMASK_INST_RETIRED_STALL_CYCLES         0x01
UMASK_INST_RETIRED_NOP                  0x02

EVENT_ASSISTS                           0xC1 PMC
UMASK_ASSISTS_FP                        0x02
UMASK_ASSISTS_ANY                       0x07

EVENT_UOPS_RETIRED                       0xC2  PMC
UMASK_UOPS_RETIRED_SLOTS                 0x02
DEFAULT_OPTIONS_RETIRED_STALL_CYCLES EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=1
UMASK_UOPS_RETIRED_STALL_CYCLES          0x02
DEFAULT_OPTIONS_RETIRED_TOTAL_CYCLES EVENT_OPTION_THRESHOLD=0xA,EVENT_OPTION_INVERT=1
UMASK_UOPS_RETIRED_TOTAL_CYCLES          0x02

EVENT_MACHINE_CLEARS                    0xC3 PMC
DEFAULT_OPTIONS_MACHINE_CLEARS_COUNT    EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_EDGE=0x1
UMASK_MACHINE_CLEARS_COUNT              0x01
UMASK_MACHINE_CLEARS_MEMORY_ORDERING    0x02
UMASK_MACHINE_CLEARS_SMC                0x04

EVENT_BR_INST_RETIRED                   0xC4 PMC
UMASK_BR_INST_RETIRED_ALL_BRANCHES      0x00
UMASK_BR_INST_RETIRED_COND_TAKEN        0x01
UMASK_BR_INST_RETIRED_NEAR_CALL         0x02
UMASK_BR_INST_RETIRED_NEAR_RETURN       0x08
UMASK_BR_INST_RETIRED_COND_NTAKEN       0x10
UMASK_BR_INST_RETIRED_COND              0x11
UMASK_BR_INST_RETIRED_NEAR_TAKEN        0x20
UMASK_BR_INST_RETIRED_FAR_BRANCH        0x40
UMASK_BR_INST_RETIRED_INDIRECT          0x80

EVENT_BR_MISP_RETIRED                   0xC5 PMC
UMASK_BR_MISP_RETIRED_ALL_BRANCHES      0x00
UMASK_BR_MISP_RETIRED_COND_TAKEN        0x01
UMASK_BR_MISP_RETIRED_INDIRECT_CALL     0x02
UMASK_BR_MISP_RETIRED_COND_NTAKEN       0x10
UMASK_BR_MISP_RETIRED_COND              0x11
UMASK_BR_MISP_RETIRED_NEAR_TAKEN        0x20
UMASK_BR_MISP_RETIRED_INDIRECT          0x80

# No FRONTEND_RETIRED events as they require programming the load latency register

EVENT_FP_ARITH_INST_RETIRED                     0xC7 PMC
UMASK_FP_ARITH_INST_RETIRED_SCALAR_DOUBLE       0x01
UMASK_FP_ARITH_INST_RETIRED_SCALAR_SINGLE       0x02
UMASK_FP_ARITH_INST_RETIRED_128B_PACKED_DOUBLE  0x04
UMASK_FP_ARITH_INST_RETIRED_128B_PACKED_SINGLE  0x08
UMASK_FP_ARITH_INST_RETIRED_256B_PACKED_DOUBLE  0x10
UMASK_FP_ARITH_INST_RETIRED_256B_PACKED_SINGLE  0x20
UMASK_FP_ARITH_INST_RETIRED_512B_PACKED_DOUBLE  0x40
UMASK_FP_ARITH_INST_RETIRED_512B_PACKED_SINGLE  0x80

EVENT_HLE_RETIRED                       0xC8 PMC
UMASK_HLE_RETIRED_START                 0x01
UMASK_HLE_RETIRED_COMMIT                0x02
UMASK_HLE_RETIRED_ABORTED               0x04
UMASK_HLE_RETIRED_ABORTED_MEM           0x08
#UMASK_HLE_RETIRED_ABORTED_TIMER         0x10
UMASK_HLE_RETIRED_ABORTED_UNFRIENDLY    0x20
#UMASK_HLE_RETIRED_ABORTED_MEMTYPE       0x40
UMASK_HLE_RETIRED_ABORTED_EVENTS        0x80

EVENT_RTM_RETIRED                       0xC9 PMC
UMASK_RTM_RETIRED_START                 0x01
UMASK_RTM_RETIRED_COMMIT                0x02
UMASK_RTM_RETIRED_ABORTED               0x04
UMASK_RTM_RETIRED_ABORTED_MEM           0x08
UMASK_RTM_RETIRED_ABORTED_TIMER         0x10
UMASK_RTM_RETIRED_ABORTED_UNFRIENDLY    0x20
UMASK_RTM_RETIRED_ABORTED_MEMTYPE       0x40
UMASK_RTM_RETIRED_ABORTED_EVENTS        0x80

EVENT_MISC_RETIRED                      0xCC PMC
UMASK_MISC_RETIRED_LBR_INSERTS          0x20
UMASK_MISC_RETIRED_PAUSE_INST           0x40

# No MEM_TRANS_RETIRED events  as they require programming of a special register (0x3F6)

EVENT_MEM_INST_RETIRED                  0xD0 PMC
UMASK_MEM_INST_RETIRED_STLB_MISS_LOADS  0x11
UMASK_MEM_INST_RETIRED_STLB_MISS_STORES 0x12
UMASK_MEM_INST_RETIRED_LOCK_LOADS       0x21
UMASK_MEM_INST_RETIRED_SPLIT_LOADS      0x41
UMASK_MEM_INST_RETIRED_SPLIT_STORES     0x42
UMASK_MEM_INST_RETIRED_ALL_LOADS        0x81
UMASK_MEM_INST_RETIRED_ALL_STORES       0x82
UMASK_MEM_INST_RETIRED_ALL              0x83

# Not sure if they work properly as they normally require to use the Data Linear Address facility
EVENT_MEM_LOAD_RETIRED                  0xD1 PMC
UMASK_MEM_LOAD_RETIRED_L1_HIT           0x01
UMASK_MEM_LOAD_RETIRED_L2_HIT           0x02
UMASK_MEM_LOAD_RETIRED_L3_HIT           0x04
UMASK_MEM_LOAD_RETIRED_L1_MISS          0x08
UMASK_MEM_LOAD_RETIRED_L2_MISS          0x10
UMASK_MEM_LOAD_RETIRED_L3_MISS          0x20
UMASK_MEM_LOAD_RETIRED_FB_HIT           0x40
UMASK_MEM_LOAD_RETIRED_LOCAL_PMM        0x80
UMASK_MEM_LOAD_RETIRED_L1_ALL           0x09
UMASK_MEM_LOAD_RETIRED_L2_ALL           0x12
UMASK_MEM_LOAD_RETIRED_L3_ALL           0x24

# Not sure if they work properly as they normally require to use the Data Linear Address facility
EVENT_MEM_LOAD_L3_HIT_RETIRED               0xD2 PMC
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_MISS     0x01
# Deprecated event name, use XSNP_NO_FWD instead
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_HIT      0x02
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_NO_FWD   0x02
# Deprecated event name, use XSNP_FWD instead
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_HITM     0x04
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_FWD     0x04
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_NONE     0x08

# Not sure if they work properly as they normally require to use the Data Linear Address facility
EVENT_MEM_LOAD_L3_MISS_RETIRED              0xD3 PMC
UMASK_MEM_LOAD_L3_MISS_RETIRED_LOCAL_DRAM   0x01
UMASK_MEM_LOAD_L3_MISS_RETIRED_REMOTE_DRAM  0x02
UMASK_MEM_LOAD_L3_MISS_RETIRED_REMOTE_HITM  0x04
UMASK_MEM_LOAD_L3_MISS_RETIRED_REMOTE_FWD   0x08
UMASK_MEM_LOAD_L3_MISS_RETIRED_REMOTE_PMM   0x10

EVENT_BACLEARS                      0xE6 PMC
UMASK_BACLEARS_ANY                  0x01

EVENT_CPU_CLOCK_UNHALTED_DISTRIBUTED    0xEC PMC
UMASK_CPU_CLOCK_UNHALTED_DISTRIBUTED    0x02

# The only officially released event is L2_TRANS_L2_WB
# All others count something but no guarantees, taken from Haswell micro-architecture (https://perfmon-events.intel.com/haswell.html#)
EVENT_L2_TRANS                0xF0  PMC
UMASK_L2_TRANS_DEMAND_DATA_RD 0x01
UMASK_L2_TRANS_RFO            0x02
UMASK_L2_TRANS_CODE_RD        0x04
UMASK_L2_TRANS_ALL_PF         0x08
UMASK_L2_TRANS_L1D_WB         0x10
UMASK_L2_TRANS_L2_FILL        0x20
UMASK_L2_TRANS_L2_WB          0x40
UMASK_L2_TRANS_ALL_REQUESTS   0x80

EVENT_L2_LINES_IN                       0xF1 PMC
#UMASK_L2_LINES_IN_I                     0x01
#UMASK_L2_LINES_IN_S                     0x02
#UMASK_L2_LINES_IN_E                     0x04
UMASK_L2_LINES_IN_ALL                   0x1F

EVENT_L2_LINES_OUT                      0xF2 PMC
UMASK_L2_LINES_OUT_SILENT               0x01
UMASK_L2_LINES_OUT_NON_SILENT           0x02
UMASK_L2_LINES_OUT_USELESS_HWPF         0x04

EVENT_SQ_MISC                       0xF4 PMC
UMASK_SQ_MISC                       0x04

# Added by T. Gruber. Not documented for ICX but
# working and in line with measurements done
# on SKX and CLX
EVENT_IDI_MISC                          0xFE PMC
UMASK_IDI_MISC_WB_UPGRADE               0x02
UMASK_IDI_MISC_WB_DOWNGRADE             0x04

EVENT_OFFCORE_RESPONSE_0                            0xB7 PMC
OPTIONS_OFFCORE_RESPONSE_0_OPTIONS                  EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_MATCH1_MASK
UMASK_OFFCORE_RESPONSE_0_OPTIONS                    0x01 0xFF 0xFF

EVENT_OFFCORE_RESPONSE_1                            0xBB PMC
OPTIONS_OFFCORE_RESPONSE_1_OPTIONS                  EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_MATCH1_MASK
UMASK_OFFCORE_RESPONSE_1_OPTIONS                    0x01 0xFF 0xFF



EVENT_CBOX_CLOCKTICKS                   0x00 CBOX
UMASK_CBOX_CLOCKTICKS                   0x00

EVENT_DIR_LOOKUP                        0x53 CBOX
UMASK_DIR_LOOKUP_SNP                    0x01
UMASK_DIR_LOOKUP_NO_SNP                 0x02

EVENT_DIR_UPDATE                        0x54 CBOX
UMASK_DIR_UPDATE_HA                     0x01
UMASK_DIR_UPDATE_TOR                    0x02

EVENT_HITME_HIT                         0x5F CBOX
UMASK_HITME_HIT_EX_RDS                  0x01
UMASK_HITME_HIT_SHARED_OWNREQ           0x04
UMASK_HITME_HIT_WBMTOE                  0x08
UMASK_HITME_HIT_WBMTOI_OR_S             0x10

EVENT_HITME_LOOKUP                      0x5E CBOX
UMASK_HITME_LOOKUP_READ                 0x01
UMASK_HITME_LOOKUP_WRITE                0x02

EVENT_HITME_MISS                        0x60 CBOX
UMASK_HITME_MISS_SHARED_RDINVOWN        0x20
UMASK_HITME_MISS_NOTSHARED_RDINVOWN     0x40
UMASK_HITME_MISS_READ_OR_INV            0x80

EVENT_HITME_UPDATE                          0x61 CBOX
UMASK_HITME_UPDATE_DEALLOCATE_RSPFWDI_LOC   0x01
UMASK_HITME_UPDATE_RSPFWDI_REM              0x02
UMASK_HITME_UPDATE_SHARED                   0x04
UMASK_HITME_UPDATE_RDINVOWN                 0x08
UMASK_HITME_UPDATE_DEALLOCATE               0x10

EVENT_LLC_VICTIMS                       0x37 CBOX
OPTIONS_LLC_VICTIMS                     EVENT_OPTION_MATCH0_MASK
UMASK_LLC_VICTIMS_M_STATE               0x01
UMASK_LLC_VICTIMS_E_STATE               0x02
UMASK_LLC_VICTIMS_S_STATE               0x04
UMASK_LLC_VICTIMS_F_STATE               0x08
UMASK_LLC_VICTIMS_ALL                   0x0F
DEFAULT_OPTIONS_LLC_VICTIMS_LOCAL_ALL   EVENT_OPTION_MATCH0=0x20
UMASK_LLC_VICTIMS_LOCAL_ALL             0x0F
DEFAULT_OPTIONS_LLC_VICTIMS_REMOTE_ALL  EVENT_OPTION_MATCH0=0x80
UMASK_LLC_VICTIMS_REMOTE_ALL            0x0F
DEFAULT_OPTIONS_LLC_VICTIMS_LOCAL_M     EVENT_OPTION_MATCH0=0x20
UMASK_LLC_VICTIMS_LOCAL_M               0x01
DEFAULT_OPTIONS_LLC_VICTIMS_LOCAL_E     EVENT_OPTION_MATCH0=0x20
UMASK_LLC_VICTIMS_LOCAL_E               0x02
DEFAULT_OPTIONS_LLC_VICTIMS_LOCAL_S     EVENT_OPTION_MATCH0=0x20
UMASK_LLC_VICTIMS_LOCAL_S               0x04
DEFAULT_OPTIONS_LLC_VICTIMS_LOCAL_F     EVENT_OPTION_MATCH0=0x20
UMASK_LLC_VICTIMS_LOCAL_F               0x08
DEFAULT_OPTIONS_LLC_VICTIMS_REMOTE_M    EVENT_OPTION_MATCH0=0x80
UMASK_LLC_VICTIMS_REMOTE_M              0x01
DEFAULT_OPTIONS_LLC_VICTIMS_REMOTE_E    EVENT_OPTION_MATCH0=0x80
UMASK_LLC_VICTIMS_REMOTE_E              0x02
DEFAULT_OPTIONS_LLC_VICTIMS_REMOTE_S    EVENT_OPTION_MATCH0=0x80
UMASK_LLC_VICTIMS_REMOTE_S              0x04
DEFAULT_OPTIONS_LLC_VICTIMS_REMOTE_F    EVENT_OPTION_MATCH0=0x80
UMASK_LLC_VICTIMS_REMOTE_F              0x08

EVENT_REQUESTS                      0x50 CBOX
UMASK_REQUESTS_READS_LOCAL          0x01
UMASK_REQUESTS_READS_REMOTE         0x02
UMASK_REQUESTS_READS                0x03
UMASK_REQUESTS_WRITES_LOCAL         0x04
UMASK_REQUESTS_WRITES_REMOTE        0x08
UMASK_REQUESTS_WRITES               0x0C
UMASK_REQUESTS_INVITOE              0x30

EVENT_COUNTER0_OCCUPANCY            0x1F CBOX0C1|CBOX1C1|CBOX2C1|CBOX3C1|CBOX4C1|CBOX5C1|CBOX6C1|CBOX7C1|CBOX8C1|CBOX9C1|CBOX10C1|CBOX11C1|CBOX12C1|CBOX13C1|CBOX14C1|CBOX15C1|CBOX16C1|CBOX17C1|CBOX18C1|CBOX19C1|CBOX20C1|CBOX21C1|CBOX22C1|CBOX23C1|CBOX24C1|CBOX25C1|CBOX26C1|CBOX27C1|CBOX28C1|CBOX29C1|CBOX30C1|CBOX31C1|CBOX32C1|CBOX33C1|CBOX34C1|CBOX35C1|CBOX36C1|CBOX37C1|CBOX38C1|CBOX39C1|CBOX0C2|CBOX1C2|CBOX2C2|CBOX3C2|CBOX4C2|CBOX5C2|CBOX6C2|CBOX7C2|CBOX8C2|CBOX9C2|CBOX10C2|CBOX11C2|CBOX12C2|CBOX13C2|CBOX14C2|CBOX15C2|CBOX16C2|CBOX17C2|CBOX18C2|CBOX19C2|CBOX20C2|CBOX21C2|CBOX22C2|CBOX23C2|CBOX24C2|CBOX25C2|CBOX26C2|CBOX27C2|CBOX28C2|CBOX29C2|CBOX30C2|CBOX31C2|CBOX32C2|CBOX33C2|CBOX34C2|CBOX35C2|CBOX36C2|CBOX37C2|CBOX38C2|CBOX39C2|CBOX0C3|CBOX1C3|CBOX2C3|CBOX3C3|CBOX4C3|CBOX5C3|CBOX6C3|CBOX7C3|CBOX8C3|CBOX9C3|CBOX10C3|CBOX11C3|CBOX12C3|CBOX13C3|CBOX14C3|CBOX15C3|CBOX16C3|CBOX17C3|CBOX18C3|CBOX19C3|CBOX20C3|CBOX21C3|CBOX22C3|CBOX23C3|CBOX24C3|CBOX25C3|CBOX26C3|CBOX27C3|CBOX28C3|CBOX29C3|CBOX30C3|CBOX31C3|CBOX32C3|CBOX33C3|CBOX34C3|CBOX35C3|CBOX36C3|CBOX37C3|CBOX38C3|CBOX39C3
UMASK_COUNTER0_OCCUPANCY            0x00

EVENT_MISC                          0x39 CBOX
UMASK_MISC_RFO_HIT_S                0x08
UMASK_MISC_RSPI_WAS_FSE             0x01
UMASK_MISC_WC_ALIASING              0x02
UMASK_MISC_CV0_PREF_VIC             0x10
UMASK_MISC_CV0_PREF_MISS            0x20
UMASK_MISC_DRNG_HIT                 0x40
UMASK_MISC_DRNG_MISS                0x80

EVENT_MISC2                         0x6A CBOX
UMASK_MISC2_GOTRK_INSERT            0x01
UMASK_MISC2_GOTRCK_IN               0x02
UMASK_MISC2_RMW_LATE_SF_INSERT      0x04
UMASK_MISC2_RMW_SF_LATE_CV          0x08
UMASK_MISC2_RMW_LLC_LATE_CV         0x10
UMASK_MISC2_GT_ONE_AKC_CRD          0x20

EVENT_SNOOP_RESP                        0x5C CBOX
UMASK_SNOOP_RESP_RSPI                   0x01
UMASK_SNOOP_RESP_RSPS                   0x02
UMASK_SNOOP_RESP_RSPIFWD                0x04
UMASK_SNOOP_RESP_RSPSFWD                0x08

EVENT_PMM_MEMMODE_NM_INVITOX                0x65 CBOX
UMASK_PMM_MEMMODE_NM_INVITOX_LOCAL          0x01
UMASK_PMM_MEMMODE_NM_INVITOX_REMOTE         0x02
UMASK_PMM_MEMMODE_NM_INVITOX_SETCONFLICT    0x04

EVENT_PMM_MEMMODE_NM_SETCONFLICTS       0x64 CBOX
UMASK_PMM_MEMMODE_NM_SETCONFLICTS_SF    0x01
UMASK_PMM_MEMMODE_NM_SETCONFLICTS_LLC   0x02
UMASK_PMM_MEMMODE_NM_SETCONFLICTS_TOR   0x04

EVENT_PMM_MEMMODE_NM_SETCONFLICTS2          0x70 CBOX
UMASK_PMM_MEMMODE_NM_SETCONFLICTS2_MEMWR    0x02
UMASK_PMM_MEMMODE_NM_SETCONFLICTS2_MEMWRNI  0x04

EVENT_BYPASS_CHA_IMC                    0x57 CBOX
UMASK_BYPASS_CHA_IMC_TAKEN              0x01
UMASK_BYPASS_CHA_IMC_INTERMEDIATE       0x02
UMASK_BYPASS_CHA_IMC_NOT_TAKEN          0x04

EVENT_CORE_SNP                      0x33 CBOX
UMASK_CORE_SNP_REMOTE_ONE           0x11
UMASK_CORE_SNP_EXT_ONE              0x21
UMASK_CORE_SNP_CORE_ONE             0x41
UMASK_CORE_SNP_EVICT_ONE            0x81
UMASK_CORE_SNP_ANY_ONE              0xF1
UMASK_CORE_SNP_REMOTE_GTONE         0x12
UMASK_CORE_SNP_EXT_GTONE            0x22
UMASK_CORE_SNP_CORE_GTONE           0x42
UMASK_CORE_SNP_EVICT_GTONE          0x81
UMASK_CORE_SNP_ANY_GTONE            0xF1

EVENT_DIRECT_GO                         0x6E CBOX
UMASK_DIRECT_GO_HA_TOR_DEALLOC          0x01
UMASK_DIRECT_GO_HA_SUPPRESS_NO_D2C      0x02
UMASK_DIRECT_GO_HA_SUPPRESS_DRD         0x04

EVENT_DIRECT_GO_OPC                     0x6D CBOX
UMASK_DIRECT_GO_OPC_EXTCMP              0x01
UMASK_DIRECT_GO_OPC_PULL                0x02
UMASK_DIRECT_GO_OPC_GO                  0x04
UMASK_DIRECT_GO_OPC_GO_PULL             0x08
UMASK_DIRECT_GO_OPC_FAST_GO             0x10
UMASK_DIRECT_GO_OPC_FAST_GO_PULL        0x20
UMASK_DIRECT_GO_OPC_NOP                 0x40
UMASK_DIRECT_GO_OPC_IDLE_DUE_SUPPRESS   0x80

EVENT_IMC_READS_COUNT_PRIORITY          0x59 CBOX
UMASK_IMC_READS_COUNT_PRIORITY          0x02

EVENT_IMC_WRITES_COUNT_PARTIAL          0x5B CBOX
UMASK_IMC_WRITES_COUNT_PARTIAL          0x02
UMASK_IMC_WRITES_COUNT_FULL_PRIORITY    0x04
UMASK_IMC_WRITES_COUNT_PARTIAL_PRIORITY 0x08

EVENT_LLC_REPAIR                        0x4A CBOX
UMASK_LLC_REPAIR_BITCAM                 0x01
UMASK_LLC_REPAIR_COLCAM                 0x02
UMASK_LLC_REPAIR_ROWCAM                 0x04

EVENT_OSB                           0x55 CBOX
UMASK_OSB_LOCAL_INVITOE             0x01
UMASK_OSB_LOCAL_READ                0x02
UMASK_OSB_REMOTE_READ               0x04
UMASK_OSB_REMOTE_READINVITOE        0x08
UMASK_OSB_RFO_HITS_SNP_BCAST        0x10
UMASK_OSB_OFF_PWRHEURISTIC          0x20

EVENT_READ_NO_CREDITS                   0x58 CBOX
OPTIONS_READ_NO_CREDITS                 EVENT_OPTION_MATCH0_MASK
UMASK_READ_NO_CREDITS_MC0               0x01
UMASK_READ_NO_CREDITS_MC1               0x02
UMASK_READ_NO_CREDITS_MC2               0x04
UMASK_READ_NO_CREDITS_MC3               0x08
UMASK_READ_NO_CREDITS_MC4               0x10
UMASK_READ_NO_CREDITS_MC5               0x20
UMASK_READ_NO_CREDITS_MC6               0x40
UMASK_READ_NO_CREDITS_MC7               0x80
DEFAULT_OPTIONS_READ_NO_CREDITS_MC8     EVENT_OPTION_MATCH0=0x01
UMASK_READ_NO_CREDITS_MC8               0x00
DEFAULT_OPTIONS_READ_NO_CREDITS_MC9     EVENT_OPTION_MATCH0=0x02
UMASK_READ_NO_CREDITS_MC9               0x00
DEFAULT_OPTIONS_READ_NO_CREDITS_MC10    EVENT_OPTION_MATCH0=0x04
UMASK_READ_NO_CREDITS_MC10              0x00
DEFAULT_OPTIONS_READ_NO_CREDITS_MC11    EVENT_OPTION_MATCH0=0x08
UMASK_READ_NO_CREDITS_MC11              0x00
DEFAULT_OPTIONS_READ_NO_CREDITS_MC12    EVENT_OPTION_MATCH0=0x10
UMASK_READ_NO_CREDITS_MC12              0x00
DEFAULT_OPTIONS_READ_NO_CREDITS_MC13    EVENT_OPTION_MATCH0=0x20
UMASK_READ_NO_CREDITS_MC13              0x00
#Added by Thomas Gruber
DEFAULT_OPTIONS_READ_NO_CREDITS_ANY     EVENT_OPTION_MATCH0=0x3F
UMASK_READ_NO_CREDITS_ANY               0xFF

EVENT_WRITE_NO_CREDITS                  0x5A CBOX
OPTIONS_WRITE_NO_CREDITS                EVENT_OPTION_MATCH0_MASK
UMASK_WRITE_NO_CREDITS_MC0              0x01
UMASK_WRITE_NO_CREDITS_MC1              0x02
UMASK_WRITE_NO_CREDITS_MC2              0x04
UMASK_WRITE_NO_CREDITS_MC3              0x08
UMASK_WRITE_NO_CREDITS_MC4              0x10
UMASK_WRITE_NO_CREDITS_MC5              0x20
UMASK_WRITE_NO_CREDITS_MC6              0x40
UMASK_WRITE_NO_CREDITS_MC7              0x80
DEFAULT_OPTIONS_WRITE_NO_CREDITS_MC8    EVENT_OPTION_MATCH0=0x01
UMASK_WRITE_NO_CREDITS_MC8              0x00
DEFAULT_OPTIONS_WRITE_NO_CREDITS_MC9    EVENT_OPTION_MATCH0=0x02
UMASK_WRITE_NO_CREDITS_MC9              0x00
DEFAULT_OPTIONS_WRITE_NO_CREDITS_MC10   EVENT_OPTION_MATCH0=0x04
UMASK_WRITE_NO_CREDITS_MC10             0x00
DEFAULT_OPTIONS_WRITE_NO_CREDITS_MC11   EVENT_OPTION_MATCH0=0x08
UMASK_WRITE_NO_CREDITS_MC11             0x00
DEFAULT_OPTIONS_WRITE_NO_CREDITS_MC12   EVENT_OPTION_MATCH0=0x10
UMASK_WRITE_NO_CREDITS_MC12             0x00
DEFAULT_OPTIONS_WRITE_NO_CREDITS_MC12   EVENT_OPTION_MATCH0=0x20
UMASK_WRITE_NO_CREDITS_MC13             0x00
#Added by Thomas Gruber
DEFAULT_OPTIONS_WRITE_NO_CREDITS_ANY    EVENT_OPTION_MATCH0=0x3F
UMASK_WRITE_NO_CREDITS_ANY              0xFF

EVENT_RXC_INSERTS                   0x13 CBOX
UMASK_RXC_INSERTS_IRQ               0x01
UMASK_RXC_INSERTS_IRQ_REJ           0x02
UMASK_RXC_INSERTS_IPQ               0x04
UMASK_RXC_INSERTS_PRQ               0x10
UMASK_RXC_INSERTS_PRQ_REJ           0x20
UMASK_RXC_INSERTS_RRQ               0x20
UMASK_RXC_INSERTS_WBQ               0x40

EVENT_RXC_IPQ0_REJECT               0x22 CBOX
UMASK_RXC_IPQ0_REJECT_AD_REQ_VN0    0x01
UMASK_RXC_IPQ0_REJECT_AD_RSP_VN0    0x02
UMASK_RXC_IPQ0_REJECT_BL_RSP_VN0    0x04
UMASK_RXC_IPQ0_REJECT_BL_WB_VN0     0x08
UMASK_RXC_IPQ0_REJECT_BL_NCB_VN0    0x10
UMASK_RXC_IPQ0_REJECT_BL_NCS_VN0    0x20
UMASK_RXC_IPQ0_REJECT_AK_NON_UPI    0x40
UMASK_RXC_IPQ0_REJECT_IV_NON_UPI    0x80

EVENT_RXC_IPQ1_REJECT               0x23 CBOX
UMASK_RXC_IPQ1_REJECT_ANY0          0x01
UMASK_RXC_IPQ1_REJECT_HA            0x02
UMASK_RXC_IPQ1_REJECT_LLC_VICTIM    0x04
UMASK_RXC_IPQ1_REJECT_SF_VICTIM     0x08
UMASK_RXC_IPQ1_REJECT_VICTIM        0x10
UMASK_RXC_IPQ1_REJECT_LLC_OR_SF_WAY 0x20
UMASK_RXC_IPQ1_REJECT_ALLOW_SNP     0x40
UMASK_RXC_IPQ1_REJECT_PA_MATCH      0x80

EVENT_RXC_IRQ0_REJECT               0x18 CBOX
UMASK_RXC_IRQ0_REJECT_AD_REQ_VN0    0x01
UMASK_RXC_IRQ0_REJECT_AD_RSP_VN0    0x02
UMASK_RXC_IRQ0_REJECT_BL_RSP_VN0    0x04
UMASK_RXC_IRQ0_REJECT_BL_WB_VN0     0x08
UMASK_RXC_IRQ0_REJECT_BL_NCB_VN0    0x10
UMASK_RXC_IRQ0_REJECT_BL_NCS_VN0    0x20
UMASK_RXC_IRQ0_REJECT_AK_NON_UPI    0x40
UMASK_RXC_IRQ0_REJECT_IV_NON_UPI    0x80

EVENT_RXC_IRQ1_REJECT               0x19 CBOX
UMASK_RXC_IRQ1_REJECT_ANY0          0x01
UMASK_RXC_IRQ1_REJECT_HA            0x02
UMASK_RXC_IRQ1_REJECT_LLC_VICTIM    0x04
UMASK_RXC_IRQ1_REJECT_SF_VICTIM     0x08
UMASK_RXC_IRQ1_REJECT_VICTIM        0x10
UMASK_RXC_IRQ1_REJECT_LLC_OR_SF_WAY 0x20
UMASK_RXC_IRQ1_REJECT_ALLOW_SNP     0x40
UMASK_RXC_IRQ1_REJECT_PA_MATCH      0x80

EVENT_RXC_ISMQ0_REJECT               0x24 CBOX
UMASK_RXC_ISMQ0_REJECT_AD_REQ_VN0    0x01
UMASK_RXC_ISMQ0_REJECT_AD_RSP_VN0    0x02
UMASK_RXC_ISMQ0_REJECT_BL_RSP_VN0    0x04
UMASK_RXC_ISMQ0_REJECT_BL_WB_VN0     0x08
UMASK_RXC_ISMQ0_REJECT_BL_NCB_VN0    0x10
UMASK_RXC_ISMQ0_REJECT_BL_NCS_VN0    0x20
UMASK_RXC_ISMQ0_REJECT_AK_NON_UPI    0x40
UMASK_RXC_ISMQ0_REJECT_IV_NON_UPI    0x80

EVENT_RXC_ISMQ1_REJECT               0x25 CBOX
UMASK_RXC_ISMQ1_REJECT_ANY0          0x01
UMASK_RXC_ISMQ1_REJECT_HA            0x02

EVENT_RXC_ISMQ0_RETRY               0x2C CBOX
UMASK_RXC_ISMQ0_RETRY_AD_REQ_VN0    0x01
UMASK_RXC_ISMQ0_RETRY_AD_RSP_VN0    0x02
UMASK_RXC_ISMQ0_RETRY_BL_RSP_VN0    0x04
UMASK_RXC_ISMQ0_RETRY_BL_WB_VN0     0x08
UMASK_RXC_ISMQ0_RETRY_BL_NCB_VN0    0x10
UMASK_RXC_ISMQ0_RETRY_BL_NCS_VN0    0x20
UMASK_RXC_ISMQ0_RETRY_AK_NON_UPI    0x40
UMASK_RXC_ISMQ0_RETRY_IV_NON_UPI    0x80

EVENT_RXC_ISMQ1_RETRY               0x2D CBOX
UMASK_RXC_ISMQ1_RETRY_ANY0          0x01
UMASK_RXC_ISMQ1_RETRY_HA            0x02

EVENT_RXC_OCCUPANCY                 0x11 CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0|CBOX24C0|CBOX25C0|CBOX26C0|CBOX27C0|CBOX28C0|CBOX29C0|CBOX30C0|CBOX31C0|CBOX32C0|CBOX33C0|CBOX34C0|CBOX35C0|CBOX36C0|CBOX37C0|CBOX38C0|CBOX39C0
UMASK_RXC_OCCUPANCY_IRQ             0x01
UMASK_RXC_OCCUPANCY_IPQ             0x04
UMASK_RXC_OCCUPANCY_RRQ             0x40
UMASK_RXC_OCCUPANCY_WBQ             0x80

EVENT_RXC_OTHER0_RETRY              0x2E CBOX
UMASK_RXC_OTHER0_RETRY_AD_REQ_VN0   0x01
UMASK_RXC_OTHER0_RETRY_AD_RSP_VN0   0x02
UMASK_RXC_OTHER0_RETRY_BL_RSP_VN0   0x04
UMASK_RXC_OTHER0_RETRY_BL_WB_VN0    0x08
UMASK_RXC_OTHER0_RETRY_BL_NCB_VN0   0x10
UMASK_RXC_OTHER0_RETRY_BL_NCS_VN0   0x20
UMASK_RXC_OTHER0_RETRY_AK_NON_UPI   0x40
UMASK_RXC_OTHER0_RETRY_IV_NON_UPI   0x80

EVENT_RXC_OTHER1_REJECT               0x2F CBOX
UMASK_RXC_OTHER1_REJECT_ANY0          0x01
UMASK_RXC_OTHER1_REJECT_HA            0x02
UMASK_RXC_OTHER1_REJECT_LLC_VICTIM    0x04
UMASK_RXC_OTHER1_REJECT_SF_VICTIM     0x08
UMASK_RXC_OTHER1_REJECT_VICTIM        0x10
UMASK_RXC_OTHER1_REJECT_LLC_OR_SF_WAY 0x20
UMASK_RXC_OTHER1_REJECT_ALLOW_SNP     0x40
UMASK_RXC_OTHER1_REJECT_PA_MATCH      0x80

EVENT_RXC_PRQ0_REJECT               0x20 CBOX
UMASK_RXC_PRQ0_REJECT_AD_REQ_VN0    0x01
UMASK_RXC_PRQ0_REJECT_AD_RSP_VN0    0x02
UMASK_RXC_PRQ0_REJECT_BL_RSP_VN0    0x04
UMASK_RXC_PRQ0_REJECT_BL_WB_VN0     0x08
UMASK_RXC_PRQ0_REJECT_BL_NCB_VN0    0x10
UMASK_RXC_PRQ0_REJECT_BL_NCS_VN0    0x20
UMASK_RXC_PRQ0_REJECT_AK_NON_UPI    0x40
UMASK_RXC_PRQ0_REJECT_IV_NON_UPI    0x80

EVENT_RXC_PRQ1_REJECT               0x21 CBOX
UMASK_RXC_PRQ1_REJECT_ANY0          0x01
UMASK_RXC_PRQ1_REJECT_HA            0x02
UMASK_RXC_PRQ1_REJECT_LLC_VICTIM    0x04
UMASK_RXC_PRQ1_REJECT_SF_VICTIM     0x08
UMASK_RXC_PRQ1_REJECT_VICTIM        0x10
UMASK_RXC_PRQ1_REJECT_LLC_OR_SF_WAY 0x20
UMASK_RXC_PRQ1_REJECT_ALLOW_SNP     0x40
UMASK_RXC_PRQ1_REJECT_PA_MATCH      0x80

EVENT_RXC_REQ_Q0_RETRY              0x2A CBOX
UMASK_RXC_REQ_Q0_RETRY_AD_REQ_VN0   0x01
UMASK_RXC_REQ_Q0_RETRY_AD_RSP_VN0   0x02
UMASK_RXC_REQ_Q0_RETRY_BL_RSP_VN0   0x04
UMASK_RXC_REQ_Q0_RETRY_BL_WB_VN0    0x08
UMASK_RXC_REQ_Q0_RETRY_BL_NCB_VN0   0x10
UMASK_RXC_REQ_Q0_RETRY_BL_NCS_VN0   0x20
UMASK_RXC_REQ_Q0_RETRY_AK_NON_UPI   0x40
UMASK_RXC_REQ_Q0_RETRY_IV_NON_UPI   0x80

EVENT_RXC_REQ_Q1_RETRY               0x2B CBOX
UMASK_RXC_REQ_Q1_RETRY_ANY0          0x01
UMASK_RXC_REQ_Q1_RETRY_HA            0x02
UMASK_RXC_REQ_Q1_RETRY_LLC_VICTIM    0x04
UMASK_RXC_REQ_Q1_RETRY_SF_VICTIM     0x08
UMASK_RXC_REQ_Q1_RETRY_VICTIM        0x10
UMASK_RXC_REQ_Q1_RETRY_LLC_OR_SF_WAY 0x20
UMASK_RXC_REQ_Q1_RETRY_ALLOW_SNP     0x40
UMASK_RXC_REQ_Q1_RETRY_PA_MATCH      0x80

EVENT_RXC_RRQ0_REJECT               0x26 CBOX
UMASK_RXC_RRQ0_REJECT_AD_REQ_VN0    0x01
UMASK_RXC_RRQ0_REJECT_AD_RSP_VN0    0x02
UMASK_RXC_RRQ0_REJECT_BL_RSP_VN0    0x04
UMASK_RXC_RRQ0_REJECT_BL_WB_VN0     0x08
UMASK_RXC_RRQ0_REJECT_BL_NCB_VN0    0x10
UMASK_RXC_RRQ0_REJECT_BL_NCS_VN0    0x20
UMASK_RXC_RRQ0_REJECT_AK_NON_UPI    0x40
UMASK_RXC_RRQ0_REJECT_IV_NON_UPI    0x80

EVENT_RXC_RRQ1_REJECT               0x27 CBOX
UMASK_RXC_RRQ1_REJECT_ANY0          0x01
UMASK_RXC_RRQ1_REJECT_HA            0x02
UMASK_RXC_RRQ1_REJECT_LLC_VICTIM    0x04
UMASK_RXC_RRQ1_REJECT_SF_VICTIM     0x08
UMASK_RXC_RRQ1_REJECT_VICTIM        0x10
UMASK_RXC_RRQ1_REJECT_LLC_OR_SF_WAY 0x20
UMASK_RXC_RRQ1_REJECT_ALLOW_SNP     0x40
UMASK_RXC_RRQ1_REJECT_PA_MATCH      0x80

EVENT_RXC_WBQ0_REJECT               0x28 CBOX
UMASK_RXC_WBQ0_REJECT_AD_REQ_VN0    0x01
UMASK_RXC_WBQ0_REJECT_AD_RSP_VN0    0x02
UMASK_RXC_WBQ0_REJECT_BL_RSP_VN0    0x04
UMASK_RXC_WBQ0_REJECT_BL_WB_VN0     0x08
UMASK_RXC_WBQ0_REJECT_BL_NCB_VN0    0x10
UMASK_RXC_WBQ0_REJECT_BL_NCS_VN0    0x20
UMASK_RXC_WBQ0_REJECT_AK_NON_UPI    0x40
UMASK_RXC_WBQ0_REJECT_IV_NON_UPI    0x80

EVENT_RXC_WBQ1_REJECT               0x29 CBOX
UMASK_RXC_WBQ1_REJECT_ANY0          0x01
UMASK_RXC_WBQ1_REJECT_HA            0x02
UMASK_RXC_WBQ1_REJECT_LLC_VICTIM    0x04
UMASK_RXC_WBQ1_REJECT_SF_VICTIM     0x08
UMASK_RXC_WBQ1_REJECT_VICTIM        0x10
UMASK_RXC_WBQ1_REJECT_LLC_OR_SF_WAY 0x20
UMASK_RXC_WBQ1_REJECT_ALLOW_SNP     0x40
UMASK_RXC_WBQ1_REJECT_PA_MATCH      0x80

EVENT_SNOOPS_SENT                   0x51 CBOX
UMASK_SNOOPS_SENT_ALL               0x01
UMASK_SNOOPS_SENT_LOCAL             0x04
UMASK_SNOOPS_SENT_REMOTE            0x08
UMASK_SNOOPS_SENT_BCST_LOCAL        0x10
UMASK_SNOOPS_SENT_BCST_REMOTE       0x20
UMASK_SNOOPS_SENT_DIRECT_LOCAL      0x40
UMASK_SNOOPS_SENT_DIRECT_REMOTE     0x80

EVENT_SNOOP_RESP                   0x5C CBOX
UMASK_SNOOP_RESP_RSP_WB            0x10
UMASK_SNOOP_RESP_RSP_FWD_WB        0x20
UMASK_SNOOP_RESP_RSP_CNFLCTS       0x40
UMASK_SNOOP_RESP_RSP_FWD           0x80

EVENT_SNOOP_RESP_LOCAL                   0x5D CBOX
UMASK_SNOOP_RESP_LOCAL_RSPI              0x01
UMASK_SNOOP_RESP_LOCAL_RSPS              0x02
UMASK_SNOOP_RESP_LOCAL_RSPI_FWD          0x04
UMASK_SNOOP_RESP_LOCAL_RSPS_FWD          0x08
UMASK_SNOOP_RESP_LOCAL_RSP_WB            0x10
UMASK_SNOOP_RESP_LOCAL_RSP_FWD_WB        0x20
UMASK_SNOOP_RESP_LOCAL_RSP_CNFLCTS       0x40
UMASK_SNOOP_RESP_LOCAL_RSP_FWD           0x80

EVENT_SNOOP_RSP_MISC                    0x6B CBOX
UMASK_SNOOP_RSP_MISC_MTOI_RSPIFWDM      0x01
UMASK_SNOOP_RSP_MISC_MTOI_RSPDATAM      0x02
UMASK_SNOOP_RSP_MISC_RSPIFWDMPTL_HITSF  0x04
UMASK_SNOOP_RSP_MISC_RSPIFWDMPTL_HITLLC 0x08
UMASK_SNOOP_RSP_MISC_PULLDATAPTL_HITSF  0x10
UMASK_SNOOP_RSP_MISC_PULLDATAPTL_HITLLC 0x20

EVENT_WB_PUSH_MTOI                  0x56 CBOX
UMASK_WB_PUSH_MTOI_LLC              0x01
UMASK_WB_PUSH_MTOI_MEM              0x02

EVENT_XPT_PREF                      0x6F CBOX
UMASK_XPT_PREF_SENT0                0x01
UMASK_XPT_PREF_DROP0_NOCRD          0x04
UMASK_XPT_PREF_DROP0_CONFLICT       0x08
UMASK_XPT_PREF_SENT1                0x10
UMASK_XPT_PREF_DROP1_NOCRD          0x40
UMASK_XPT_PREF_DROP1_CONFLICT       0x80

# EVENT_OPTION_STATE
EVENT_LLC_LOOKUP                    0x34 CBOX
OPTIONS_LLC_LOOKUP                  EVENT_OPTION_STATE_MASK|EVENT_OPTION_MATCH0_MASK
UMASK_LLC_LOOKUP_I                  0x01
UMASK_LLC_LOOKUP_SF_S               0x02
UMASK_LLC_LOOKUP_SF_E               0x04
UMASK_LLC_LOOKUP_SF_H               0x08
UMASK_LLC_LOOKUP_S                  0x10
UMASK_LLC_LOOKUP_E                  0x20
UMASK_LLC_LOOKUP_M                  0x40
UMASK_LLC_LOOKUP_F                  0x80
DEFAULT_OPTIONS_LLC_LOOKUP_ALL              EVENT_OPTION_MATCH0=0x1FFF
UMASK_LLC_LOOKUP_ALL                        0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_ALL_REMOTE       EVENT_OPTION_MATCH0=0x1E20
UMASK_LLC_LOOKUP_ALL_REMOTE                 0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_DATA_READ        EVENT_OPTION_MATCH0=0x1BC1
UMASK_LLC_LOOKUP_DATA_READ                  0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_DATA_READ_LOCAL  EVENT_OPTION_MATCH0=0x19C1
UMASK_LLC_LOOKUP_DATA_READ_LOCAL            0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_DATA_READ_REMOTE EVENT_OPTION_MATCH0=0x1A01
UMASK_LLC_LOOKUP_DATA_READ_REMOTE           0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_CODE_READ        EVENT_OPTION_MATCH0=0x1BD0
UMASK_LLC_LOOKUP_CODE_READ                  0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_CODE_READ_LOCAL  EVENT_OPTION_MATCH0=0x19D0
UMASK_LLC_LOOKUP_CODE_READ_LOCAL            0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_CODE_READ_REMOTE EVENT_OPTION_MATCH0=0x1A10
UMASK_LLC_LOOKUP_CODE_READ_REMOTE           0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_RFO              EVENT_OPTION_MATCH0=0x1BC8
UMASK_LLC_LOOKUP_RFO                        0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_RFO_LOCAL        EVENT_OPTION_MATCH0=0x19C8
UMASK_LLC_LOOKUP_RFO_LOCAL                  0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_RFO_REMOTE       EVENT_OPTION_MATCH0=0x1A08
UMASK_LLC_LOOKUP_RFO_REMOTE                 0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_FLUSH_INV        EVENT_OPTION_MATCH0=0x1BC1
UMASK_LLC_LOOKUP_FLUSH_INV                  0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_FLUSH_INV_LOCAL  EVENT_OPTION_MATCH0=0x1844
UMASK_LLC_LOOKUP_FLUSH_INV_LOCAL            0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_FLUSH_INV_REMOTE EVENT_OPTION_MATCH0=0x1A04
UMASK_LLC_LOOKUP_FLUSH_INV_REMOTE           0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_LOC_HOM          EVENT_OPTION_MATCH0=0x0BDF
UMASK_LLC_LOOKUP_LOC_HOM                    0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_REM_HOM          EVENT_OPTION_MATCH0=0x15DF
UMASK_LLC_LOOKUP_REM_HOM                    0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_REMOTE_SNP       EVENT_OPTION_MATCH0=0x1C19
UMASK_LLC_LOOKUP_REMOTE_SNP                 0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_LLC_PF_LOCAL     EVENT_OPTION_MATCH0=0x189D
UMASK_LLC_LOOKUP_LLC_PF_LOCAL               0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_LLCPREF_LOCAL    EVENT_OPTION_MATCH0=0x189D
UMASK_LLC_LOOKUP_LLCPREF_LOCAL              0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_DATA_READ_ALL    EVENT_OPTION_MATCH0=0x1FC1
UMASK_LLC_LOOKUP_DATA_READ_ALL              0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_DATA_READ_MISS   EVENT_OPTION_MATCH0=0x1BC1
UMASK_LLC_LOOKUP_DATA_READ_MISS             0x01
DEFAULT_OPTIONS_LLC_LOOKUP_WRITE_REMOTE     EVENT_OPTION_MATCH0=0x17C2
UMASK_LLC_LOOKUP_WRITE_REMOTE               0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_MISS_ALL         EVENT_OPTION_MATCH0=0x1FE0
UMASK_LLC_LOOKUP_MISS_ALL                   0x01
DEFAULT_OPTIONS_LLC_LOOKUP_CODE_READ_MISS   EVENT_OPTION_MATCH0=0x1BD0
UMASK_LLC_LOOKUP_CODE_READ_MISS             0x01
DEFAULT_OPTIONS_LLC_LOOKUP_RFO_MISS         EVENT_OPTION_MATCH0=0x1BC8
UMASK_LLC_LOOKUP_RFO_MISS                   0x01
DEFAULT_OPTIONS_LLC_LOOKUP_READ             EVENT_OPTION_MATCH0=0x1BD9
UMASK_LLC_LOOKUP_READ                       0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_READ_MISS        EVENT_OPTION_MATCH0=0x1BD9
UMASK_LLC_LOOKUP_READ_MISS                  0x01
DEFAULT_OPTIONS_LLC_LOOKUP_READ_MISS_LOC_HOM    EVENT_OPTION_MATCH0=0x0BD9
UMASK_LLC_LOOKUP_READ_MISS_LOC_HOM              0x01
DEFAULT_OPTIONS_LLC_LOOKUP_READ_MISS_REM_HOM    EVENT_OPTION_MATCH0=0x13D9
UMASK_LLC_LOOKUP_READ_MISS_REM_HOM              0x01
DEFAULT_OPTIONS_LLC_LOOKUP_READ_LOCAL_LOC_HOM   EVENT_OPTION_MATCH0=0x09D9
UMASK_LLC_LOOKUP_READ_LOCAL_LOC_HOM             0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_READ_REMOTE_LOC_HOM  EVENT_OPTION_MATCH0=0x0A19
UMASK_LLC_LOOKUP_READ_REMOTE_LOC_HOM            0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_READ_LOCAL_REM_HOM   EVENT_OPTION_MATCH0=0x11D9
UMASK_LLC_LOOKUP_READ_LOCAL_REM_HOM             0xFF
DEFAULT_OPTIONS_LLC_LOOKUP_READ_SF_HIT          EVENT_OPTION_MATCH0=0x1BD9
UMASK_LLC_LOOKUP_READ_SF_HIT                    0x0E
DEFAULT_OPTIONS_LLC_LOOKUP_READ_OR_SNOOP_REMOTE_MISS_REM_HOM    EVENT_OPTION_MATCH0=0x1619
UMASK_LLC_LOOKUP_READ_OR_SNOOP_REMOTE_MISS_REM_HOM              0x01
DEFAULT_OPTIONS_LLC_LOOKUP_WRITES_AND_OTHER     EVENT_OPTION_MATCH0=0x1A42
UMASK_LLC_LOOKUP_WRITES_AND_OTHER               0xFF


EVENT_TOR_INSERTS                   0x35 CBOX
OPTIONS_TOR_INSERTS                 EVENT_OPTION_MATCH0_MASK
UMASK_TOR_INSERTS_IRQ_IA            0x01
UMASK_TOR_INSERTS_EVICT             0x02
UMASK_TOR_INSERTS_PRQ_IOSF          0x04
UMASK_TOR_INSERTS_IPQ               0x08
UMASK_TOR_INSERTS_IRQ_NON_IA        0x10
UMASK_TOR_INSERTS_PRQ_NON_IOSF      0x20
UMASK_TOR_INSERTS_RRQ               0x40
UMASK_TOR_INSERTS_WBQ               0x80
DEFAULT_OPTIONS_TOR_INSERTS_ALL                                 EVENT_OPTION_MATCH0=0xC001FF
UMASK_TOR_INSERTS_ALL                                           0xFF
DEFAULT_OPTIONS_TOR_INSERTS_IA_LOCAL_ALL                        EVENT_OPTION_MATCH0=0xC000FF
UMASK_TOR_INSERTS_IA_LOCAL_ALL                                  0x01
DEFAULT_OPTIONS_TOR_INSERTS_LOC_ALL                             EVENT_OPTION_MATCH0=0xC000FF
UMASK_TOR_INSERTS_ALL_LOCAL_ALL                                 0x05
DEFAULT_OPTIONS_TOR_INSERTS_IA_HIT_DRD_OPT                      EVENT_OPTION_MATCH0=0xC827FD
UMASK_TOR_INSERTS_IA_HIT_DRD_OPT                                0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_HIT_DRD_OPT_PREF                 EVENT_OPTION_MATCH0=0xC8A7FD
UMASK_TOR_INSERTS_IA_HIT_DRD_OPT_PREF                           0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_DRD_OPT                     EVENT_OPTION_MATCH0=0xC827FE
UMASK_TOR_INSERTS_IA_MISS_DRD_OPT                               0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_DRD_OPT_PREF                EVENT_OPTION_MATCH0=0xC8A7FE
UMASK_TOR_INSERTS_IA_MISS_DRD_OPT_PREF                          0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_DRD                              EVENT_OPTION_MATCH0=0xC817FF
UMASK_TOR_INSERTS_IA_DRD                                        0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_DRD_OPT                          EVENT_OPTION_MATCH0=0xC827FF
UMASK_TOR_INSERTS_IA_DRD_OPT                                    0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_DRD_OPT_PREF                     EVENT_OPTION_MATCH0=0xC8A7FF
UMASK_TOR_INSERTS_IA_DRD_OPT_PREF                               0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_CRD_PREF                         EVENT_OPTION_MATCH0=0xC88FFF
UMASK_TOR_INSERTS_IA_CRD_PREF                                   0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_CLFLUSHOPT                       EVENT_OPTION_MATCH0=0xC8D7FF
UMASK_TOR_INSERTS_IA_CLFLUSHOPT                                 0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_ITOM                             EVENT_OPTION_MATCH0=0xCC47FF
UMASK_TOR_INSERTS_IA_ITOM                                       0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_SPECITOM                         EVENT_OPTION_MATCH0=0xCC57FF
UMASK_TOR_INSERTS_IA_SPECITOM                                   0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_WBMTOI                           EVENT_OPTION_MATCH0=0xCC27FF
UMASK_TOR_INSERTS_IA_WBMTOI                                     0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_DRD_PREF_PMM                EVENT_OPTION_MATCH0=0xC8978A
UMASK_TOR_INSERTS_IA_MISS_DRD_PREF_PMM                          0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_DRD_PREF_LOCAL_PMM          EVENT_OPTION_MATCH0=0xC8968A
UMASK_TOR_INSERTS_IA_MISS_DRD_PREF_LOCAL_PMM                    0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_DRD_PREF_REMOTE_PMM         EVENT_OPTION_MATCH0=0xC8970A
UMASK_TOR_INSERTS_IA_MISS_DRD_PREF_REMOTE_PMM                   0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_FULL_STREAMING_WR_DRAM      EVENT_OPTION_MATCH0=0xC86786
UMASK_TOR_INSERTS_IA_MISS_FULL_STREAMING_WR_DRAM                0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_FULL_STREAMING_WR_LOCAL_DRAM EVENT_OPTION_MATCH0=0xC86686
UMASK_TOR_INSERTS_IA_MISS_FULL_STREAMING_WR_LOCAL_DRAM          0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_FULL_STREAMING_WR_REMOTE_DRAM   EVENT_OPTION_MATCH0=0xC86706
UMASK_TOR_INSERTS_IA_MISS_FULL_STREAMING_WR_REMOTE_DRAM         0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_FULL_STREAMING_WR_DDR       EVENT_OPTION_MATCH0=0xC86786
UMASK_TOR_INSERTS_IA_MISS_FULL_STREAMING_WR_DDR                 0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_FULL_STREAMING_WR_LOCAL_DDR EVENT_OPTION_MATCH0=0xC86686
UMASK_TOR_INSERTS_IA_MISS_FULL_STREAMING_WR_LOCAL_DDR           0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_FULL_STREAMING_WR_REMOTE_DDR EVENT_OPTION_MATCH0=0xC86706
UMASK_TOR_INSERTS_IA_MISS_FULL_STREAMING_WR_REMOTE_DDR          0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_FULL_STREAMING_WR_PMM       EVENT_OPTION_MATCH0=0xC8678A
UMASK_TOR_INSERTS_IA_MISS_FULL_STREAMING_WR_PMM                 0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_FULL_STREAMING_WR_LOCAL_PMM EVENT_OPTION_MATCH0=0xC8668A
UMASK_TOR_INSERTS_IA_MISS_FULL_STREAMING_WR_LOCAL_PMM           0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_FULL_STREAMING_WR_REMOTE_PMM EVENT_OPTION_MATCH0=0xC8670A
UMASK_TOR_INSERTS_IA_MISS_FULL_STREAMING_WR_REMOTE_PMM          0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_PARTIAL_STREAMING_WR_DDR    EVENT_OPTION_MATCH0=0xC86F86
UMASK_TOR_INSERTS_IA_MISS_PARTIAL_STREAMING_WR_DDR              0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR  EVENT_OPTION_MATCH0=0xC86E86
UMASK_TOR_INSERTS_IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR            0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR EVENT_OPTION_MATCH0=0xC86F06
UMASK_TOR_INSERTS_IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR           0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_PARTIAL_STREAMING_WR_DRAM       EVENT_OPTION_MATCH0=0xC86F86
UMASK_TOR_INSERTS_IA_MISS_PARTIAL_STREAMING_WR_DRAM                 0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DRAM EVENT_OPTION_MATCH0=0xC86E86
UMASK_TOR_INSERTS_IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DRAM           0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DRAM EVENT_OPTION_MATCH0=0xC86F06
UMASK_TOR_INSERTS_IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DRAM          0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_PARTIAL_STREAMING_WR_PMM        EVENT_OPTION_MATCH0=0xC86F8A
UMASK_TOR_INSERTS_IA_MISS_PARTIAL_STREAMING_WR_PMM                  0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM  EVENT_OPTION_MATCH0=0xC86E8A
UMASK_TOR_INSERTS_IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM            0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM EVENT_OPTION_MATCH0=0xC86F0A
UMASK_TOR_INSERTS_IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM           0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_WCIL                        EVENT_OPTION_MATCH0=0xC86FFE
UMASK_TOR_INSERTS_IA_MISS_WCIL                                  0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_WCILF                            EVENT_OPTION_MATCH0=0xC867FF
UMASK_TOR_INSERTS_IA_WCILF                                      0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_WCIL                             EVENT_OPTION_MATCH0=0xC86FFF
UMASK_TOR_INSERTS_IA_WCIL                                       0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_WIL                         EVENT_OPTION_MATCH0=0xC87FDE
UMASK_TOR_INSERTS_IA_MISS_WIL                                   0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_CRD_LOCAL                   EVENT_OPTION_MATCH0=0xC80EFE
UMASK_TOR_INSERTS_IA_MISS_CRD_LOCAL                             0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_CRD_REMOTE                  EVENT_OPTION_MATCH0=0xC80F7E
UMASK_TOR_INSERTS_IA_MISS_CRD_REMOTE                            0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_CRD_PREF_LOCAL              EVENT_OPTION_MATCH0=0xC88EFE
UMASK_TOR_INSERTS_IA_MISS_CRD_PREF_LOCAL                        0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_CRD_PREF_REMOTE             EVENT_OPTION_MATCH0=0xC88F7E
UMASK_TOR_INSERTS_IA_MISS_CRD_PREF_REMOTE                       0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_ITOMCACHENEAR                    EVENT_OPTION_MATCH0=0xCD47FF
UMASK_TOR_INSERTS_IA_ITOMCACHENEAR                              0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_HIT_ITOM                         EVENT_OPTION_MATCH0=0xCC47FD
UMASK_TOR_INSERTS_IA_HIT_ITOM                                   0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_ITOM                        EVENT_OPTION_MATCH0=0xCC47FE
UMASK_TOR_INSERTS_IA_MISS_ITOM                                  0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_UCRDF                       EVENT_OPTION_MATCH0=0xC877DE
UMASK_TOR_INSERTS_IA_MISS_UCRDF                                 0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_LLCPREFCODE                      EVENT_OPTION_MATCH0=0xCCCFFF
UMASK_TOR_INSERTS_IA_LLCPREFCODE                                0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_HIT_LLCPREFCODE                  EVENT_OPTION_MATCH0=0xCCCFFD
UMASK_TOR_INSERTS_IA_HIT_LLCPREFCODE                            0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_HIT_LLCPREFDATA                  EVENT_OPTION_MATCH0=0xCCD7FD
UMASK_TOR_INSERTS_IA_HIT_LLCPREFDATA                            0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_LLCPREFCODE                 EVENT_OPTION_MATCH0=0xCCCFFE
UMASK_TOR_INSERTS_IA_MISS_LLCPREFCODE                           0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_WCILF_PMM                   EVENT_OPTION_MATCH0=0xC8678A
UMASK_TOR_INSERTS_IA_MISS_WCILF_PMM                             0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_LOCAL_WCILF_PMM             EVENT_OPTION_MATCH0=0xC8668A
UMASK_TOR_INSERTS_IA_MISS_LOCAL_WCILF_PMM                       0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_REMOTE_WCILF_PMM            EVENT_OPTION_MATCH0=0xC8670A
UMASK_TOR_INSERTS_IA_MISS_REMOTE_WCILF_PMM                      0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_WCIL_PMM                    EVENT_OPTION_MATCH0=0xC86F8A
UMASK_TOR_INSERTS_IA_MISS_WCIL_PMM                              0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_LOCAL_WCIL_PMM              EVENT_OPTION_MATCH0=0xC86E8A
UMASK_TOR_INSERTS_IA_MISS_LOCAL_WCIL_PMM                        0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_REMOTE_WCIL_PMM             EVENT_OPTION_MATCH0=0xC86F0A
UMASK_TOR_INSERTS_IA_MISS_REMOTE_WCIL_PMM                       0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_DRD_PREF_DDR                EVENT_OPTION_MATCH0=0xC89786
UMASK_TOR_INSERTS_IA_MISS_DRD_PREF_DDR                          0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_DRD_PREF_LOCAL_DDR          EVENT_OPTION_MATCH0=0xC89686
UMASK_TOR_INSERTS_IA_MISS_DRD_PREF_LOCAL_DDR                    0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_DRD_PREF_REMOTE_DDR         EVENT_OPTION_MATCH0=0xC89706
UMASK_TOR_INSERTS_IA_MISS_DRD_PREF_REMOTE_DDR                   0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_WCILF_DDR                   EVENT_OPTION_MATCH0=0xC86786
UMASK_TOR_INSERTS_IA_MISS_WCILF_DDR                             0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_LOCAL_WCILF_DDR             EVENT_OPTION_MATCH0=0xC86686
UMASK_TOR_INSERTS_IA_MISS_LOCAL_WCILF_DDR                       0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_REMOTE_WCILF_DDR            EVENT_OPTION_MATCH0=0xC86706
UMASK_TOR_INSERTS_IA_MISS_REMOTE_WCILF_DDR                      0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_WCIL_DDR                    EVENT_OPTION_MATCH0=0xC86F86
UMASK_TOR_INSERTS_IA_MISS_WCIL_DDR                              0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_LOCAL_WCIL_DDR              EVENT_OPTION_MATCH0=0xC86E86
UMASK_TOR_INSERTS_IA_MISS_LOCAL_WCIL_DDR                        0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_REMOTE_WCIL_DDR             EVENT_OPTION_MATCH0=0xC86F06
UMASK_TOR_INSERTS_IA_MISS_REMOTE_WCIL_DDR                       0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_WCILF                       EVENT_OPTION_MATCH0=0xC867FE
UMASK_TOR_INSERTS_IA_MISS_WCILF                                 0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_WBEFTOE                          EVENT_OPTION_MATCH0=0xCC3FFF
UMASK_TOR_INSERTS_IA_WBEFTOE                                    0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_SPECITOM                    EVENT_OPTION_MATCH0=0xCC57FE
UMASK_TOR_INSERTS_IA_MISS_SPECITOM                              0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_MISS_DRDPTE                      EVENT_OPTION_MATCH0=0xC837FE
UMASK_TOR_INSERTS_IA_MISS_DRDPTE                                0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_HIT_DRDPTE                       EVENT_OPTION_MATCH0=0xC837FD
UMASK_TOR_INSERTS_IA_HIT_DRDPTE                                 0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_DRDPTE                           EVENT_OPTION_MATCH0=0xC837FF
UMASK_TOR_INSERTS_IA_DRDPTE                                     0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_HIT_SPECITOM                     EVENT_OPTION_MATCH0=0xCC57FD
UMASK_TOR_INSERTS_IA_HIT_SPECITOM                               0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_WBSTOI                           EVENT_OPTION_MATCH0=0xCC67FF
UMASK_TOR_INSERTS_IA_WBSTOI                                     0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_WBEFTOI                          EVENT_OPTION_MATCH0=0xCC37FF
UMASK_TOR_INSERTS_IA_WBEFTOI                                    0x01
DEFAULT_OPTIONS_TOR_INSERTS_IA_WBMTOE                           EVENT_OPTION_MATCH0=0xCC2FFF
UMASK_TOR_INSERTS_IA_WBMTOE                                     0x01
DEFAULT_OPTIONS_TOR_INSERTS_IO                                  EVENT_OPTION_MATCH0=0xC001FF
UMASK_TOR_INSERTS_IO                                            0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_HIT                              EVENT_OPTION_MATCH0=0xC001FD
UMASK_TOR_INSERTS_IO_HIT                                        0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_MISS                             EVENT_OPTION_MATCH0=0xC001FE
UMASK_TOR_INSERTS_IO_MISS                                       0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_MISS_RFO                         EVENT_OPTION_MATCH0=0xC803FE
UMASK_TOR_INSERTS_IO_MISS_RFO                                   0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_LOCAL_ALL                        EVENT_OPTION_MATCH0=0xC000FF
UMASK_TOR_INSERTS_IO_LOCAL_ALL                                  0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_HIT_RFO                          EVENT_OPTION_MATCH0=0xC803FD
UMASK_TOR_INSERTS_IO_HIT_RFO                                    0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_RFO                              EVENT_OPTION_MATCH0=0xC803FF
UMASK_TOR_INSERTS_IO_RFO                                        0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_WBMTOI                           EVENT_OPTION_MATCH0=0xCC23FF
UMASK_TOR_INSERTS_IO_WBMTOI                                     0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_CLFLUSH                          EVENT_OPTION_MATCH0=0xC8C3FF
UMASK_TOR_INSERTS_IO_CLFLUSH                                    0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_MISS_ITOM                        EVENT_OPTION_MATCH0=0xCC43FE
UMASK_TOR_INSERTS_IO_MISS_ITOM                                  0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_HIT_ITOM                         EVENT_OPTION_MATCH0=0xCC43FD
UMASK_TOR_INSERTS_IO_HIT_ITOM                                   0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_ITOM                             EVENT_OPTION_MATCH0=0xCC43FF
UMASK_TOR_INSERTS_IO_ITOM                                       0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_ITOMCACHENEAR                    EVENT_OPTION_MATCH0=0xCD43FF
UMASK_TOR_INSERTS_IO_ITOMCACHENEAR                              0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_HIT_ITOMCACHENEAR                EVENT_OPTION_MATCH0=0xCD43FD
UMASK_TOR_INSERTS_IO_HIT_ITOMCACHENEAR                          0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_MISS_ITOMCACHENEAR               EVENT_OPTION_MATCH0=0xCD43FE
UMASK_TOR_INSERTS_IO_MISS_ITOMCACHENEAR                         0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_MISS_PCIRDCUR                    EVENT_OPTION_MATCH0=0xC8F3FE
UMASK_TOR_INSERTS_IO_MISS_PCIRDCUR                              0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_HIT_PCIRDCUR                     EVENT_OPTION_MATCH0=0xC8F3FD
UMASK_TOR_INSERTS_IO_HIT_PCIRDCUR                               0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_PCIRDCUR                         EVENT_OPTION_MATCH0=0xC8F3FF
UMASK_TOR_INSERTS_IO_PCIRDCUR                                   0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_ITOM_LOCAL                       EVENT_OPTION_MATCH0=0xCC42FF
UMASK_TOR_INSERTS_IO_ITOM_LOCAL                                 0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_ITOM_REMOTE                      EVENT_OPTION_MATCH0=0xCC437F
UMASK_TOR_INSERTS_IO_ITOM_REMOTE                                0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_ITOMCACHENEAR_LOCAL              EVENT_OPTION_MATCH0=0xCD42FF
UMASK_TOR_INSERTS_IO_ITOMCACHENEAR_LOCAL                        0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_ITOMCACHENEAR_REMOTE             EVENT_OPTION_MATCH0=0xCD437F
UMASK_TOR_INSERTS_IO_ITOMCACHENEAR_REMOTE                       0x04


EVENT_TOR_OCCUPANCY                 0x36 CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0|CBOX24C0|CBOX25C0|CBOX26C0|CBOX27C0|CBOX28C0|CBOX29C0|CBOX30C0|CBOX31C0|CBOX32C0|CBOX33C0|CBOX34C0|CBOX35C0|CBOX36C0|CBOX37C0|CBOX38C0|CBOX39C0
UMASK_TOR_OCCUPANCY_IRQ_IA          0x01
UMASK_TOR_OCCUPANCY_EVICT           0x02
UMASK_TOR_OCCUPANCY_PRQ             0x04
UMASK_TOR_OCCUPANCY_IPQ             0x08
UMASK_TOR_OCCUPANCY_IRQ_NON_IA      0x10
UMASK_TOR_OCCUPANCY_PRQ_NON_IOSF    0x20
DEFAULT_OPTIONS_TOR_OCCUPANCY_LOC_IO                    EVENT_OPTION_MATCH0=0xC000FF
UMASK_TOR_OCCUPANCY_LOC_IO                              0x04
DEFAULT_OPTIONS_TOR_OCCUPANCY_LOC_IA                    EVENT_OPTION_MATCH0=0xC000FF
UMASK_TOR_OCCUPANCY_LOC_IA                              0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_LOC_ALL                   EVENT_OPTION_MATCH0=0xC000FF
UMASK_TOR_OCCUPANCY_LOC_ALL                             0x05
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_HIT_CRD                EVENT_OPTION_MATCH0=0xC80FFD
UMASK_TOR_OCCUPANCY_IA_HIT_CRD                          0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_HIT_DRD                EVENT_OPTION_MATCH0=0xC817FD
UMASK_TOR_OCCUPANCY_IA_HIT_DRD                          0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_HIT_LLCPREFRFO         EVENT_OPTION_MATCH0=0xCCC7FD
UMASK_TOR_OCCUPANCY_IA_HIT_LLCPREFRFO                   0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_HIT_RFO                EVENT_OPTION_MATCH0=0xC807FD
UMASK_TOR_OCCUPANCY_IA_HIT_RFO                          0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_LLCPREFRFO        EVENT_OPTION_MATCH0=0xCCC7FE
UMASK_TOR_OCCUPANCY_IA_MISS_LLCPREFRFO                  0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_MISS_RFO               EVENT_OPTION_MATCH0=0xC803FE
UMASK_TOR_OCCUPANCY_IO_MISS_RFO                         0x04
DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_MISS_ITOM              EVENT_OPTION_MATCH0=0xCC43FE
UMASK_TOR_OCCUPANCY_IO_MISS_ITOM                        0x04
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_HIT_CRD_PREF           EVENT_OPTION_MATCH0=0xC88FFD
UMASK_TOR_OCCUPANCY_IA_HIT_CRD_PREF                     0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_HIT_DRD_PREF           EVENT_OPTION_MATCH0=0xC897FD
UMASK_TOR_OCCUPANCY_IA_HIT_DRD_PREF                     0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_HIT_DRD_OPT            EVENT_OPTION_MATCH0=0xC827FD
UMASK_TOR_OCCUPANCY_IA_HIT_DRD_OPT                      0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_HIT_DRD_OPT_PREF       EVENT_OPTION_MATCH0=0xC8A7FD
UMASK_TOR_OCCUPANCY_IA_HIT_DRD_OPT_PREF                 0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_HIT_RFO_PREF           EVENT_OPTION_MATCH0=0xC887FD
UMASK_TOR_OCCUPANCY_IA_HIT_RFO_PREF                     0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_CRD_PREF          EVENT_OPTION_MATCH0=0xC88FFE
UMASK_TOR_OCCUPANCY_IA_MISS_CRD_PREF                    0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_DRD_PREF          EVENT_OPTION_MATCH0=0xC897FE
UMASK_TOR_OCCUPANCY_IA_MISS_DRD_PREF                    0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_DRD_OPT           EVENT_OPTION_MATCH0=0xC827FE
UMASK_TOR_OCCUPANCY_IA_MISS_DRD_OPT                     0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_DRD_OPT_PREF      EVENT_OPTION_MATCH0=0xC8A7FE
UMASK_TOR_OCCUPANCY_IA_MISS_DRD_OPT_PREF                0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_RFO_PREF          EVENT_OPTION_MATCH0=0xC887FE
UMASK_TOR_OCCUPANCY_IA_MISS_RFO_PREF                    0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_HIT_ITOM               EVENT_OPTION_MATCH0=0xCC43FD
UMASK_TOR_OCCUPANCY_IO_HIT_ITOM                         0x04
DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_HIT_RFO                EVENT_OPTION_MATCH0=0xC803FD
UMASK_TOR_OCCUPANCY_IO_HIT_RFO                          0x04
DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_RFO                    EVENT_OPTION_MATCH0=0xC803FF
UMASK_TOR_OCCUPANCY_IO_RFO                              0x04
DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_ITOM                   EVENT_OPTION_MATCH0=0xCC43FF
UMASK_TOR_OCCUPANCY_IO_ITOM                             0x04
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_RFO_PREF               EVENT_OPTION_MATCH0=0xC887FF
UMASK_TOR_OCCUPANCY_IA_RFO_PREF                         0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_LLCPREFRFO             EVENT_OPTION_MATCH0=0xCCC7FF
UMASK_TOR_OCCUPANCY_IA_LLCPREFRFO                       0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_DRD_OPT                EVENT_OPTION_MATCH0=0xC827FF
UMASK_TOR_OCCUPANCY_IA_DRD_OPT                          0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_DRD_OPT_PREF           EVENT_OPTION_MATCH0=0xC8A7FF
UMASK_TOR_OCCUPANCY_IA_DRD_OPT_PREF                     0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_CRD_PREF               EVENT_OPTION_MATCH0=0xC88FFF
UMASK_TOR_OCCUPANCY_IA_CRD_PREF                         0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_DRD_PREF               EVENT_OPTION_MATCH0=0xC897FF
UMASK_TOR_OCCUPANCY_IA_DRD_PREF                         0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_DRD_PREF_LOCAL    EVENT_OPTION_MATCH0=0xC896FE
UMASK_TOR_OCCUPANCY_IA_MISS_DRD_PREF_LOCAL              0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_DRD_PREF_REMOTE   EVENT_OPTION_MATCH0=0xC8977E
UMASK_TOR_OCCUPANCY_IA_MISS_DRD_PREF_REMOTE             0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_RFO_LOCAL         EVENT_OPTION_MATCH0=0xC806FE
UMASK_TOR_OCCUPANCY_IA_MISS_RFO_LOCAL                   0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_RFO_REMOTE        EVENT_OPTION_MATCH0=0xC8077E
UMASK_TOR_OCCUPANCY_IA_MISS_RFO_REMOTE                  0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_RFO_PREF_LOCAL    EVENT_OPTION_MATCH0=0xC886FE
UMASK_TOR_OCCUPANCY_IA_MISS_RFO_PREF_LOCAL              0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_RFO_PREF_REMOTE   EVENT_OPTION_MATCH0=0xC8877E
UMASK_TOR_OCCUPANCY_IA_MISS_RFO_PREF_REMOTE             0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_DRD_LOCAL_DDR     EVENT_OPTION_MATCH0=0xC81686
UMASK_TOR_OCCUPANCY_IA_MISS_DRD_LOCAL_DDR               0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_DRD_REMOTE_DDR    EVENT_OPTION_MATCH0=0xC81706
UMASK_TOR_OCCUPANCY_IA_MISS_DRD_REMOTE_DDR              0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_DRD_LOCAL_PMM     EVENT_OPTION_MATCH0=0xC8168A
UMASK_TOR_OCCUPANCY_IA_MISS_DRD_LOCAL_PMM               0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_DRD_REMOTE_PMM    EVENT_OPTION_MATCH0=0xC8170A
UMASK_TOR_OCCUPANCY_IA_MISS_DRD_REMOTE_PMM              0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_DRD_PREF_DDR          EVENT_OPTION_MATCH0=0xC89786
UMASK_TOR_OCCUPANCY_IA_MISS_DRD_PREF_DDR                    0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_DRD_PREF_LOCAL_DDR    EVENT_OPTION_MATCH0=0xC89686
UMASK_TOR_OCCUPANCY_IA_MISS_DRD_PREF_LOCAL_DDR              0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_DRD_PREF_REMOTE_DDR   EVENT_OPTION_MATCH0=0xC89706
UMASK_TOR_OCCUPANCY_IA_MISS_DRD_PREF_REMOTE_DDR             0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_DRD_PREF_PMM          EVENT_OPTION_MATCH0=0xC8978A
UMASK_TOR_OCCUPANCY_IA_MISS_DRD_PREF_PMM                    0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_DRD_PREF_LOCAL_PMM    EVENT_OPTION_MATCH0=0xC8968A
UMASK_TOR_OCCUPANCY_IA_MISS_DRD_PREF_LOCAL_PMM              0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_DRD_PREF_REMOTE_PMM   EVENT_OPTION_MATCH0=0xC8970A
UMASK_TOR_OCCUPANCY_IA_MISS_DRD_PREF_REMOTE_PMM             0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_FULL_STREAMING_WR     EVENT_OPTION_MATCH0=0xC867FE
UMASK_TOR_OCCUPANCY_IA_MISS_FULL_STREAMING_WR               0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_FULL_STREAMING_WR_DRAM        EVENT_OPTION_MATCH0=0xC86786
UMASK_TOR_OCCUPANCY_IA_MISS_FULL_STREAMING_WR_DRAM                  0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_FULL_STREAMING_WR_LOCAL_DRAM  EVENT_OPTION_MATCH0=0xC86686
UMASK_TOR_OCCUPANCY_IA_MISS_FULL_STREAMING_WR_LOCAL_DRAM            0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_FULL_STREAMING_WR_REMOTE_DRAM EVENT_OPTION_MATCH0=0xC86706
UMASK_TOR_OCCUPANCY_IA_MISS_FULL_STREAMING_WR_REMOTE_DRAM           0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_FULL_STREAMING_WR_DDR         EVENT_OPTION_MATCH0=0xC86786
UMASK_TOR_OCCUPANCY_IA_MISS_FULL_STREAMING_WR_DDR                   0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_FULL_STREAMING_WR_LOCAL_DDR   EVENT_OPTION_MATCH0=0xC86686
UMASK_TOR_OCCUPANCY_IA_MISS_FULL_STREAMING_WR_LOCAL_DDR             0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_FULL_STREAMING_WR_REMOTE_DDR  EVENT_OPTION_MATCH0=0xC86706
UMASK_TOR_OCCUPANCY_IA_MISS_FULL_STREAMING_WR_REMOTE_DDR            0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_FULL_STREAMING_WR_PMM         EVENT_OPTION_MATCH0=0xC8678A
UMASK_TOR_OCCUPANCY_IA_MISS_FULL_STREAMING_WR_PMM                   0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_FULL_STREAMING_WR_LOCAL_PMM   EVENT_OPTION_MATCH0=0xC8668A
UMASK_TOR_OCCUPANCY_IA_MISS_FULL_STREAMING_WR_LOCAL_PMM             0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_FULL_STREAMING_WR_REMOTE_PMM  EVENT_OPTION_MATCH0=0xC8670A
UMASK_TOR_OCCUPANCY_IA_MISS_FULL_STREAMING_WR_REMOTE_PMM            0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_PARTIAL_STREAMING_WR_DRAM         EVENT_OPTION_MATCH0=0xC86F86
UMASK_TOR_OCCUPANCY_IA_MISS_PARTIAL_STREAMING_WR_DRAM                   0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DRAM   EVENT_OPTION_MATCH0=0xC86E86
UMASK_TOR_OCCUPANCY_IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DRAM             0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DRAM  EVENT_OPTION_MATCH0=0xC86F06
UMASK_TOR_OCCUPANCY_IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DRAM            0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_PARTIAL_STREAMING_WR_DDR          EVENT_OPTION_MATCH0=0xC86F86
UMASK_TOR_OCCUPANCY_IA_MISS_PARTIAL_STREAMING_WR_DDR                    0x01 0xC86F86 0x00
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR    EVENT_OPTION_MATCH0=0xC86E86
UMASK_TOR_OCCUPANCY_IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR              0x01 0xC86E86 0x00
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR   EVENT_OPTION_MATCH0=0xC86F06
UMASK_TOR_OCCUPANCY_IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR             0x01 0xC86F06 0x00
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_PARTIAL_STREAMING_WR              EVENT_OPTION_MATCH0=0xC86FFE
UMASK_TOR_OCCUPANCY_IA_MISS_PARTIAL_STREAMING_WR                        0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_PARTIAL_STREAMING_WR_PMM          EVENT_OPTION_MATCH0=0xC86F8A
UMASK_TOR_OCCUPANCY_IA_MISS_PARTIAL_STREAMING_WR_PMM                    0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM    EVENT_OPTION_MATCH0=0xC86E8A
UMASK_TOR_OCCUPANCY_IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM              0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM   EVENT_OPTION_MATCH0=0xC86F0A
UMASK_TOR_OCCUPANCY_IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM             0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_HIT_LLCPREFCODE        EVENT_OPTION_MATCH0=0xCCCFFD
UMASK_TOR_OCCUPANCY_IA_HIT_LLCPREFCODE                  0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_HIT_LLCPREFDATA        EVENT_OPTION_MATCH0=0xCCD7FD
UMASK_TOR_OCCUPANCY_IA_HIT_LLCPREFDATA                  0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_LLCPREFCODE       EVENT_OPTION_MATCH0=0xCCCFFE
UMASK_TOR_OCCUPANCY_IA_MISS_LLCPREFCODE                 0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_LLCPREFDATA       EVENT_OPTION_MATCH0=0xCCD7FE
UMASK_TOR_OCCUPANCY_IA_MISS_LLCPREFDATA                 0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_WCILF_DDR         EVENT_OPTION_MATCH0=0xC86786
UMASK_TOR_OCCUPANCY_IA_MISS_WCILF_DDR                   0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_LOCAL_WCILF_DDR   EVENT_OPTION_MATCH0=0xC86686
UMASK_TOR_OCCUPANCY_IA_MISS_LOCAL_WCILF_DDR             0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_REMOTE_WCILF_DDR  EVENT_OPTION_MATCH0=0xC86706
UMASK_TOR_OCCUPANCY_IA_MISS_REMOTE_WCILF_DDR            0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_WCILF_PMM         EVENT_OPTION_MATCH0=0xC8678A
UMASK_TOR_OCCUPANCY_IA_MISS_WCILF_PMM                   0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_LOCAL_WCILF_PMM   EVENT_OPTION_MATCH0=0xC8668A
UMASK_TOR_OCCUPANCY_IA_MISS_LOCAL_WCILF_PMM             0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_REMOTE_WCILF_PMM  EVENT_OPTION_MATCH0=0xC8670A
UMASK_TOR_OCCUPANCY_IA_MISS_REMOTE_WCILF_PMM            0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_WCIL_DDR          EVENT_OPTION_MATCH0=0xC86F86
UMASK_TOR_OCCUPANCY_IA_MISS_WCIL_DDR                    0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_LOCAL_WCIL_DDR    EVENT_OPTION_MATCH0=0xC86E86
UMASK_TOR_OCCUPANCY_IA_MISS_LOCAL_WCIL_DDR              0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_REMOTE_WCIL_DDR   EVENT_OPTION_MATCH0=0xC86F06
UMASK_TOR_OCCUPANCY_IA_MISS_REMOTE_WCIL_DDR             0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_WCIL_PMM          EVENT_OPTION_MATCH0=0xC86F8A
UMASK_TOR_OCCUPANCY_IA_MISS_WCIL_PMM                    0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_LOCAL_WCIL_PMM    EVENT_OPTION_MATCH0=0xC86E8A
UMASK_TOR_OCCUPANCY_IA_MISS_LOCAL_WCIL_PMM              0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_REMOTE_WCIL_PMM   EVENT_OPTION_MATCH0=0xC86F0A
UMASK_TOR_OCCUPANCY_IA_MISS_REMOTE_WCIL_PMM             0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_HIT_PCIRDCUR           EVENT_OPTION_MATCH0=0xC8F3FD
UMASK_TOR_OCCUPANCY_IO_HIT_PCIRDCUR                     0x04
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_LLCPREFDATA            EVENT_OPTION_MATCH0=0xCCD7FF
UMASK_TOR_OCCUPANCY_IA_LLCPREFDATA                      0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_WCILF             EVENT_OPTION_MATCH0=0xC867FE
UMASK_TOR_OCCUPANCY_IA_MISS_WCILF                       0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_WCIL              EVENT_OPTION_MATCH0=0xC86FFE
UMASK_TOR_OCCUPANCY_IA_MISS_WCIL                        0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_CRD_LOCAL         EVENT_OPTION_MATCH0=0xC80EFE
UMASK_TOR_OCCUPANCY_IA_MISS_CRD_LOCAL                   0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_CRD_REMOTE        EVENT_OPTION_MATCH0=0xC80F7E
UMASK_TOR_OCCUPANCY_IA_MISS_CRD_REMOTE                  0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_CRD_PREF_LOCAL    EVENT_OPTION_MATCH0=0xC88EFE
UMASK_TOR_OCCUPANCY_IA_MISS_CRD_PREF_LOCAL              0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_CRD_PREF_REMOTE   EVENT_OPTION_MATCH0=0xC88F7E
UMASK_TOR_OCCUPANCY_IA_MISS_CRD_PREF_REMOTE             0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_CLFLUSH                EVENT_OPTION_MATCH0=0xC8C7FF
UMASK_TOR_OCCUPANCY_IA_CLFLUSH                          0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_CLFLUSHOPT             EVENT_OPTION_MATCH0=0xC8D7FF
UMASK_TOR_OCCUPANCY_IA_CLFLUSHOPT                       0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_ITOMCACHENEAR          EVENT_OPTION_MATCH0=0xCD47FF
UMASK_TOR_OCCUPANCY_IA_ITOMCACHENEAR                    0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_SPECITOM               EVENT_OPTION_MATCH0=0xCC57FF
UMASK_TOR_OCCUPANCY_IA_SPECITOM                         0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_WBMTOI                 EVENT_OPTION_MATCH0=0xCC27FF
UMASK_TOR_OCCUPANCY_IA_WBMTOI                           0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_ITOM                   EVENT_OPTION_MATCH0=0xCC47FF
UMASK_TOR_OCCUPANCY_IA_ITOM                             0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_HIT_ITOM               EVENT_OPTION_MATCH0=0xCC47FD
UMASK_TOR_OCCUPANCY_IA_HIT_ITOM                         0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_ITOM              EVENT_OPTION_MATCH0=0xCC47FE
UMASK_TOR_OCCUPANCY_IA_MISS_ITOM                        0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_UCRDF             EVENT_OPTION_MATCH0=0xC877DE
UMASK_TOR_OCCUPANCY_IA_MISS_UCRDF                       0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_WIL               EVENT_OPTION_MATCH0=0xC87FDE
UMASK_TOR_OCCUPANCY_IA_MISS_WIL                         0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_WCILF                  EVENT_OPTION_MATCH0=0xC867FF
UMASK_TOR_OCCUPANCY_IA_WCILF                            0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_WCIL                   EVENT_OPTION_MATCH0=0xC86FFF
UMASK_TOR_OCCUPANCY_IA_WCIL                             0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_LLCPREFCODE            EVENT_OPTION_MATCH0=0xCCCFFF
UMASK_TOR_OCCUPANCY_IA_LLCPREFCODE                      0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_WBMTOI                 EVENT_OPTION_MATCH0=0xCC23FF
UMASK_TOR_OCCUPANCY_IO_WBMTOI                           0x04
DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_CLFLUSH                EVENT_OPTION_MATCH0=0xC8C3FF
UMASK_TOR_OCCUPANCY_IO_CLFLUSH                          0x04
DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_ITOMCACHENEAR          EVENT_OPTION_MATCH0=0xCD43FF
UMASK_TOR_OCCUPANCY_IO_ITOMCACHENEAR                    0x04
DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_HIT_ITOMCACHENEAR      EVENT_OPTION_MATCH0=0xCD43FD
UMASK_TOR_OCCUPANCY_IO_HIT_ITOMCACHENEAR                0x04
DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_MISS_ITOMCACHENEAR     EVENT_OPTION_MATCH0=0xCD43FE
UMASK_TOR_OCCUPANCY_IO_MISS_ITOMCACHENEAR               0x04
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_SPECITOM          EVENT_OPTION_MATCH0=0xCC57FE
UMASK_TOR_OCCUPANCY_IA_MISS_SPECITOM                    0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_DRDPTE                 EVENT_OPTION_MATCH0=0xC837FF
UMASK_TOR_OCCUPANCY_IA_DRDPTE                           0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_HIT_DRDPTE             EVENT_OPTION_MATCH0=0xC837FD
UMASK_TOR_OCCUPANCY_IA_HIT_DRDPTE                       0x01
DEFAULT_OPTIONS_TOR_OCCUPANCY_IA_MISS_DRDPTE            EVENT_OPTION_MATCH0=0xC837FE
UMASK_TOR_OCCUPANCY_IA_MISS_DRDPTE                      0x01

EVENT_CMS_CLOCKTICKS                0xC0 CBOX|M2M|PBOX|SBOX
UMASK_CMS_CLOCKTICKS                0x00

EVENT_AG0_AD_CRD_ACQUIRED0       0x80 CBOX|M2M|PBOX|SBOX
UMASK_AG0_AD_CRD_ACQUIRED0_TGR0  0x01
UMASK_AG0_AD_CRD_ACQUIRED0_TGR1  0x02
UMASK_AG0_AD_CRD_ACQUIRED0_TGR2  0x04
UMASK_AG0_AD_CRD_ACQUIRED0_TGR3  0x08
UMASK_AG0_AD_CRD_ACQUIRED0_TGR4  0x10
UMASK_AG0_AD_CRD_ACQUIRED0_TGR5  0x20
UMASK_AG0_AD_CRD_ACQUIRED0_TGR6  0x40
UMASK_AG0_AD_CRD_ACQUIRED0_TGR7  0x80

EVENT_AG0_AD_CRD_ACQUIRED1       0x81 CBOX|M2M|PBOX|SBOX
UMASK_AG0_AD_CRD_ACQUIRED1_TGR8  0x01
UMASK_AG0_AD_CRD_ACQUIRED1_TGR9  0x02
UMASK_AG0_AD_CRD_ACQUIRED1_TGR10 0x04

# Shouldn't this event be only allowed for CBOX*C0?
EVENT_AG0_AD_CRD_OCCUPANCY0       0x82 CBOX|M2M|PBOX|SBOX
UMASK_AG0_AD_CRD_OCCUPANCY0_TGR0  0x01
UMASK_AG0_AD_CRD_OCCUPANCY0_TGR1  0x02
UMASK_AG0_AD_CRD_OCCUPANCY0_TGR2  0x04
UMASK_AG0_AD_CRD_OCCUPANCY0_TGR3  0x08
UMASK_AG0_AD_CRD_OCCUPANCY0_TGR4  0x10
UMASK_AG0_AD_CRD_OCCUPANCY0_TGR5  0x20
UMASK_AG0_AD_CRD_OCCUPANCY0_TGR6  0x40
UMASK_AG0_AD_CRD_OCCUPANCY0_TGR7  0x80

# Shouldn't this event be only allowed for CBOX*C0?
EVENT_AG0_AD_CRD_OCCUPANCY1       0x83 CBOX|M2M|PBOX|SBOX
UMASK_AG0_AD_CRD_OCCUPANCY1_TGR8  0x01
UMASK_AG0_AD_CRD_OCCUPANCY1_TGR9  0x02
UMASK_AG0_AD_CRD_OCCUPANCY1_TGR10 0x04

EVENT_AG0_BL_CRD_ACQUIRED0       0x88 CBOX|M2M|PBOX|SBOX
UMASK_AG0_BL_CRD_ACQUIRED0_TGR0  0x01
UMASK_AG0_BL_CRD_ACQUIRED0_TGR1  0x02
UMASK_AG0_BL_CRD_ACQUIRED0_TGR2  0x04
UMASK_AG0_BL_CRD_ACQUIRED0_TGR3  0x08
UMASK_AG0_BL_CRD_ACQUIRED0_TGR4  0x10
UMASK_AG0_BL_CRD_ACQUIRED0_TGR5  0x20
UMASK_AG0_BL_CRD_ACQUIRED0_TGR6  0x40
UMASK_AG0_BL_CRD_ACQUIRED0_TGR7  0x80

EVENT_AG0_BL_CRD_ACQUIRED1       0x89 CBOX|M2M|PBOX|SBOX
UMASK_AG0_BL_CRD_ACQUIRED1_TGR8  0x01
UMASK_AG0_BL_CRD_ACQUIRED1_TGR9  0x02
UMASK_AG0_BL_CRD_ACQUIRED1_TGR10 0x04

# Shouldn't this event be only allowed for CBOX*C0?
EVENT_AG0_BL_CRD_OCCUPANCY0       0x8A CBOX|M2M|PBOX|SBOX
UMASK_AG0_BL_CRD_OCCUPANCY0_TGR0  0x01
UMASK_AG0_BL_CRD_OCCUPANCY0_TGR1  0x02
UMASK_AG0_BL_CRD_OCCUPANCY0_TGR2  0x04
UMASK_AG0_BL_CRD_OCCUPANCY0_TGR3  0x08
UMASK_AG0_BL_CRD_OCCUPANCY0_TGR4  0x10
UMASK_AG0_BL_CRD_OCCUPANCY0_TGR5  0x20
UMASK_AG0_BL_CRD_OCCUPANCY0_TGR6  0x40
UMASK_AG0_BL_CRD_OCCUPANCY0_TGR7  0x80

# Shouldn't this event be only allowed for CBOX*C0?
EVENT_AG0_BL_CRD_OCCUPANCY1       0x8B CBOX|M2M|PBOX|SBOX
UMASK_AG0_BL_CRD_OCCUPANCY1_TGR8  0x01
UMASK_AG0_BL_CRD_OCCUPANCY1_TGR9  0x02
UMASK_AG0_BL_CRD_OCCUPANCY1_TGR10 0x04

EVENT_AG1_AD_CRD_ACQUIRED0       0x84 CBOX|M2M|PBOX|SBOX
UMASK_AG1_AD_CRD_ACQUIRED0_TGR0  0x01
UMASK_AG1_AD_CRD_ACQUIRED0_TGR1  0x02
UMASK_AG1_AD_CRD_ACQUIRED0_TGR2  0x04
UMASK_AG1_AD_CRD_ACQUIRED0_TGR3  0x08
UMASK_AG1_AD_CRD_ACQUIRED0_TGR4  0x10
UMASK_AG1_AD_CRD_ACQUIRED0_TGR5  0x20
UMASK_AG1_AD_CRD_ACQUIRED0_TGR6  0x40
UMASK_AG1_AD_CRD_ACQUIRED0_TGR7  0x80

EVENT_AG1_AD_CRD_ACQUIRED1       0x85 CBOX|M2M|PBOX|SBOX
UMASK_AG1_AD_CRD_ACQUIRED1_TGR8  0x01
UMASK_AG1_AD_CRD_ACQUIRED1_TGR9  0x02
UMASK_AG1_AD_CRD_ACQUIRED1_TGR10 0x04

# Shouldn't this event be only allowed for CBOX*C0?
EVENT_AG1_AD_CRD_OCCUPANCY0       0x86 CBOX|M2M|PBOX|SBOX
UMASK_AG1_AD_CRD_OCCUPANCY0_TGR0  0x01
UMASK_AG1_AD_CRD_OCCUPANCY0_TGR1  0x02
UMASK_AG1_AD_CRD_OCCUPANCY0_TGR2  0x04
UMASK_AG1_AD_CRD_OCCUPANCY0_TGR3  0x08
UMASK_AG1_AD_CRD_OCCUPANCY0_TGR4  0x10
UMASK_AG1_AD_CRD_OCCUPANCY0_TGR5  0x20
UMASK_AG1_AD_CRD_OCCUPANCY0_TGR6  0x40
UMASK_AG1_AD_CRD_OCCUPANCY0_TGR7  0x80

# Shouldn't this event be only allowed for CBOX*C0?
EVENT_AG1_AD_CRD_OCCUPANCY1       0x87 CBOX|M2M|PBOX|SBOX
UMASK_AG1_AD_CRD_OCCUPANCY1_TGR8  0x01
UMASK_AG1_AD_CRD_OCCUPANCY1_TGR9  0x02
UMASK_AG1_AD_CRD_OCCUPANCY1_TGR10 0x04

EVENT_AG1_BL_CRD_ACQUIRED0       0x8C CBOX|M2M|PBOX|SBOX
UMASK_AG1_BL_CRD_ACQUIRED0_TGR0  0x01
UMASK_AG1_BL_CRD_ACQUIRED0_TGR1  0x02
UMASK_AG1_BL_CRD_ACQUIRED0_TGR2  0x04
UMASK_AG1_BL_CRD_ACQUIRED0_TGR3  0x08
UMASK_AG1_BL_CRD_ACQUIRED0_TGR4  0x10
UMASK_AG1_BL_CRD_ACQUIRED0_TGR5  0x20
UMASK_AG1_BL_CRD_ACQUIRED0_TGR6  0x40
UMASK_AG1_BL_CRD_ACQUIRED0_TGR7  0x80

EVENT_AG1_BL_CRD_ACQUIRED1       0x8D CBOX|M2M|PBOX|SBOX
UMASK_AG1_BL_CRD_ACQUIRED1_TGR8  0x01
UMASK_AG1_BL_CRD_ACQUIRED1_TGR9  0x02
UMASK_AG1_BL_CRD_ACQUIRED1_TGR10 0x04

# Shouldn't this event be only allowed for CBOX*C0?
EVENT_AG1_BL_CRD_OCCUPANCY0       0x8E CBOX|M2M|PBOX|SBOX
UMASK_AG1_BL_CRD_OCCUPANCY0_TGR0  0x01
UMASK_AG1_BL_CRD_OCCUPANCY0_TGR1  0x02
UMASK_AG1_BL_CRD_OCCUPANCY0_TGR2  0x04
UMASK_AG1_BL_CRD_OCCUPANCY0_TGR3  0x08
UMASK_AG1_BL_CRD_OCCUPANCY0_TGR4  0x10
UMASK_AG1_BL_CRD_OCCUPANCY0_TGR5  0x20
UMASK_AG1_BL_CRD_OCCUPANCY0_TGR6  0x40
UMASK_AG1_BL_CRD_OCCUPANCY0_TGR7  0x80

# Shouldn't this event be only allowed for CBOX*C0?
EVENT_AG1_BL_CRD_OCCUPANCY1       0x8F CBOX|M2M|PBOX|SBOX
UMASK_AG1_BL_CRD_OCCUPANCY1_TGR8  0x01
UMASK_AG1_BL_CRD_OCCUPANCY1_TGR9  0x02
UMASK_AG1_BL_CRD_OCCUPANCY1_TGR10 0x04

EVENT_DISTRESS_ASSERTED                 0xAF CBOX|M2M|PBOX|SBOX
UMASK_DISTRESS_ASSERTED_VERT            0x01
UMASK_DISTRESS_ASSERTED_HORZ            0x02
UMASK_DISTRESS_ASSERTED_DPT_LOCAL       0x04
UMASK_DISTRESS_ASSERTED_DPT_NONLOCAL    0x08
UMASK_DISTRESS_ASSERTED_DPT_STALL_IV    0x40
UMASK_DISTRESS_ASSERTED_DPT_STALL_NOCRD 0x80
UMASK_DISTRESS_ASSERTED_PMM_LOCAL       0x10
UMASK_DISTRESS_ASSERTED_PMM_NONLOCAL    0x20

EVENT_EGRESS_ORDERING               0xBA CBOX|M2M|PBOX|SBOX
UMASK_EGRESS_ORDERING_IV_SNOOPGO_UP 0x01
UMASK_EGRESS_ORDERING_IV_SNOOPGO_DN 0x04

EVENT_HORZ_RING_AD_IN_USE               0xB6 CBOX|M2M|PBOX|SBOX
UMASK_HORZ_RING_AD_IN_USE_LEFT_EVEN     0x01
UMASK_HORZ_RING_AD_IN_USE_LEFT_ODD      0x02
UMASK_HORZ_RING_AD_IN_USE_RIGHT_EVEN    0x04
UMASK_HORZ_RING_AD_IN_USE_RIGHT_ODD     0x08

EVENT_HORZ_RING_AKC_IN_USE               0xBB CBOX|M2M|PBOX|SBOX
UMASK_HORZ_RING_AKC_IN_USE_LEFT_EVEN     0x01
UMASK_HORZ_RING_AKC_IN_USE_LEFT_ODD      0x02
UMASK_HORZ_RING_AKC_IN_USE_RIGHT_EVEN    0x04
UMASK_HORZ_RING_AKC_IN_USE_RIGHT_ODD     0x08

EVENT_HORZ_RING_AK_IN_USE               0xB7 CBOX|M2M|PBOX|SBOX
UMASK_HORZ_RING_AK_IN_USE_LEFT_EVEN     0x01
UMASK_HORZ_RING_AK_IN_USE_LEFT_ODD      0x02
UMASK_HORZ_RING_AK_IN_USE_RIGHT_EVEN    0x04
UMASK_HORZ_RING_AK_IN_USE_RIGHT_ODD     0x08

EVENT_HORZ_RING_BL_IN_USE               0xB8 CBOX|M2M|PBOX|SBOX
UMASK_HORZ_RING_BL_IN_USE_LEFT_EVEN     0x01
UMASK_HORZ_RING_BL_IN_USE_LEFT_ODD      0x02
UMASK_HORZ_RING_BL_IN_USE_RIGHT_EVEN    0x04
UMASK_HORZ_RING_BL_IN_USE_RIGHT_ODD     0x08

EVENT_HORZ_RING_IV_IN_USE               0xB9 CBOX|M2M|PBOX|SBOX
UMASK_HORZ_RING_IV_IN_USE_LEFT          0x01
UMASK_HORZ_RING_IV_IN_USE_RIGHT         0x04

EVENT_MISC_EXTERNAL                     0xE6 CBOX|M2M|PBOX|SBOX
UMASK_MISC_EXTERNAL_MBE_INST0           0x01
UMASK_MISC_EXTERNAL_MBE_INST1           0x01

EVENT_RING_BOUNCES_HORZ                 0xAC CBOX|M2M|PBOX|SBOX
UMASK_RING_BOUNCES_HORZ_AD              0x01
UMASK_RING_BOUNCES_HORZ_AK              0x02
UMASK_RING_BOUNCES_HORZ_BL              0x04
UMASK_RING_BOUNCES_HORZ_IV              0x08

EVENT_RING_BOUNCES_VERT                 0xAA CBOX|M2M|PBOX|SBOX
UMASK_RING_BOUNCES_VERT_AD              0x01
UMASK_RING_BOUNCES_VERT_AK              0x02
UMASK_RING_BOUNCES_VERT_BL              0x04
UMASK_RING_BOUNCES_VERT_IV              0x08
UMASK_RING_BOUNCES_VERT_AKC             0x10

EVENT_RING_SINK_STARVED_HORZ            0xAD CBOX|M2M|PBOX|SBOX
UMASK_RING_SINK_STARVED_HORZ_AD         0x01
UMASK_RING_SINK_STARVED_HORZ_AK         0x02
UMASK_RING_SINK_STARVED_HORZ_BL         0x04
UMASK_RING_SINK_STARVED_HORZ_IV         0x08
UMASK_RING_SINK_STARVED_HORZ_AK_AG1     0x20

EVENT_RING_SINK_STARVED_VERT            0xAB CBOX|M2M|PBOX|SBOX
UMASK_RING_SINK_STARVED_VERT_AD         0x01
UMASK_RING_SINK_STARVED_VERT_AK         0x02
UMASK_RING_SINK_STARVED_VERT_BL         0x04
UMASK_RING_SINK_STARVED_VERT_IV         0x08
UMASK_RING_SINK_STARVED_VERT_AKC        0x10

EVENT_RXR_BUSY_STARVED                  0xE5 CBOX|M2M|PBOX|SBOX
UMASK_RXR_BUSY_STARVED_AD_UNCRD         0x01
UMASK_RXR_BUSY_STARVED_BL_UNCRD         0x04
UMASK_RXR_BUSY_STARVED_AD_CRD           0x10
UMASK_RXR_BUSY_STARVED_BL_CRD           0x40
UMASK_RXR_BUSY_STARVED_AD_ALL           0x11
UMASK_RXR_BUSY_STARVED_BL_ALL           0x44

EVENT_RXR_BYPASS                        0xE2 CBOX|M2M|PBOX|SBOX
UMASK_RXR_BYPASS_AD_UNCRD               0x01
UMASK_RXR_BYPASS_AK                     0x02
UMASK_RXR_BYPASS_BL_UNCRD               0x04
UMASK_RXR_BYPASS_IV                     0x08
UMASK_RXR_BYPASS_AD_CRD                 0x10
UMASK_RXR_BYPASS_BL_CRD                 0x40
UMASK_RXR_BYPASS_AKC_UNCRD              0x80
UMASK_RXR_BYPASS_AD_ALL                 0x11
UMASK_RXR_BYPASS_BL_ALL                 0x44

EVENT_RXR_CRD_STARVED                   0xE3 CBOX|M2M|PBOX|SBOX
UMASK_RXR_CRD_STARVED_AD_UNCRD          0x01
UMASK_RXR_CRD_STARVED_AK                0x02
UMASK_RXR_CRD_STARVED_BL_UNCRD          0x04
UMASK_RXR_CRD_STARVED_IV                0x08
UMASK_RXR_CRD_STARVED_AD_CRD            0x10
UMASK_RXR_CRD_STARVED_BL_CRD            0x40
UMASK_RXR_CRD_STARVED_IFV               0x80
UMASK_RXR_CRD_STARVED_AD_ALL            0x11
UMASK_RXR_CRD_STARVED_BL_ALL            0x44

EVENT_RXR_CRD_STARVED_1                 0xE4 CBOX|M2M|PBOX|SBOX
UMASK_RXR_CRD_STARVED_1                 0x00

EVENT_RXR_INSERTS                        0xE1 CBOX|M2M|PBOX|SBOX
UMASK_RXR_INSERTS_AD_UNCRD               0x01
UMASK_RXR_INSERTS_AK                     0x02
UMASK_RXR_INSERTS_BL_UNCRD               0x04
UMASK_RXR_INSERTS_IV                     0x08
UMASK_RXR_INSERTS_AD_CRD                 0x10
UMASK_RXR_INSERTS_BL_CRD                 0x40
UMASK_RXR_INSERTS_AKC_UNCRD              0x80
UMASK_RXR_INSERTS_AD_ALL                 0x11
UMASK_RXR_INSERTS_BL_ALL                 0x44

EVENT_RXR_OCCUPANCY                        0xE0 CBOX|M2M|PBOX|SBOX
UMASK_RXR_OCCUPANCY_AD_UNCRD               0x01
UMASK_RXR_OCCUPANCY_AK                     0x02
UMASK_RXR_OCCUPANCY_BL_UNCRD               0x04
UMASK_RXR_OCCUPANCY_IV                     0x08
UMASK_RXR_OCCUPANCY_AD_CRD                 0x10
UMASK_RXR_OCCUPANCY_BL_CRD                 0x40
UMASK_RXR_OCCUPANCY_AKC_UNCRD              0x80
UMASK_RXR_OCCUPANCY_AD_ALL                 0x11
UMASK_RXR_OCCUPANCY_BL_ALL                 0x44

EVENT_STALL0_NO_TXR_HORZ_CRD_AD_AG0          0xD0 CBOX|M2M|PBOX|SBOX
UMASK_STALL0_NO_TXR_HORZ_CRD_AD_AG0_TGR0     0x01
UMASK_STALL0_NO_TXR_HORZ_CRD_AD_AG0_TGR1     0x02
UMASK_STALL0_NO_TXR_HORZ_CRD_AD_AG0_TGR2     0x04
UMASK_STALL0_NO_TXR_HORZ_CRD_AD_AG0_TGR3     0x08
UMASK_STALL0_NO_TXR_HORZ_CRD_AD_AG0_TGR4     0x10
UMASK_STALL0_NO_TXR_HORZ_CRD_AD_AG0_TGR5     0x20
UMASK_STALL0_NO_TXR_HORZ_CRD_AD_AG0_TGR6     0x40
UMASK_STALL0_NO_TXR_HORZ_CRD_AD_AG0_TGR7     0x80

EVENT_STALL1_NO_TXR_HORZ_CRD_AD_AG0          0xD1 CBOX|M2M|PBOX|SBOX
UMASK_STALL1_NO_TXR_HORZ_CRD_AD_AG0_TGR8     0x01
UMASK_STALL1_NO_TXR_HORZ_CRD_AD_AG0_TGR9     0x02
UMASK_STALL1_NO_TXR_HORZ_CRD_AD_AG0_TGR10    0x04

EVENT_STALL0_NO_TXR_HORZ_CRD_AD_AG1          0xD2 CBOX|M2M|PBOX|SBOX
UMASK_STALL0_NO_TXR_HORZ_CRD_AD_AG1_TGR0     0x01
UMASK_STALL0_NO_TXR_HORZ_CRD_AD_AG1_TGR1     0x02
UMASK_STALL0_NO_TXR_HORZ_CRD_AD_AG1_TGR2     0x04
UMASK_STALL0_NO_TXR_HORZ_CRD_AD_AG1_TGR3     0x08
UMASK_STALL0_NO_TXR_HORZ_CRD_AD_AG1_TGR4     0x10
UMASK_STALL0_NO_TXR_HORZ_CRD_AD_AG1_TGR5     0x20
UMASK_STALL0_NO_TXR_HORZ_CRD_AD_AG1_TGR6     0x40
UMASK_STALL0_NO_TXR_HORZ_CRD_AD_AG1_TGR7     0x80

EVENT_STALL1_NO_TXR_HORZ_CRD_AD_AG1_1          0xD3 CBOX|M2M|PBOX|SBOX
UMASK_STALL1_NO_TXR_HORZ_CRD_AD_AG1_1_TGR8     0x01
UMASK_STALL1_NO_TXR_HORZ_CRD_AD_AG1_1_TGR9     0x02
UMASK_STALL1_NO_TXR_HORZ_CRD_AD_AG1_1_TGR10    0x04

EVENT_STALL0_NO_TXR_HORZ_CRD_BL_AG0          0xD4 CBOX|M2M|PBOX|SBOX
UMASK_STALL0_NO_TXR_HORZ_CRD_BL_AG0_TGR0     0x01
UMASK_STALL0_NO_TXR_HORZ_CRD_BL_AG0_TGR1     0x02
UMASK_STALL0_NO_TXR_HORZ_CRD_BL_AG0_TGR2     0x04
UMASK_STALL0_NO_TXR_HORZ_CRD_BL_AG0_TGR3     0x08
UMASK_STALL0_NO_TXR_HORZ_CRD_BL_AG0_TGR4     0x10
UMASK_STALL0_NO_TXR_HORZ_CRD_BL_AG0_TGR5     0x20
UMASK_STALL0_NO_TXR_HORZ_CRD_BL_AG0_TGR6     0x40
UMASK_STALL0_NO_TXR_HORZ_CRD_BL_AG0_TGR7     0x80

EVENT_STALL0_NO_TXR_HORZ_CRD_BL_AG0_1          0xD5 CBOX|M2M|PBOX|SBOX
UMASK_STALL0_NO_TXR_HORZ_CRD_BL_AG0_1_TGR8     0x01
UMASK_STALL0_NO_TXR_HORZ_CRD_BL_AG0_1_TGR9     0x02
UMASK_STALL0_NO_TXR_HORZ_CRD_BL_AG0_1_TGR10    0x04

EVENT_STALL0_NO_TXR_HORZ_CRD_BL_AG1          0xD6 CBOX|M2M|PBOX|SBOX
UMASK_STALL0_NO_TXR_HORZ_CRD_BL_AG1_TGR0     0x01
UMASK_STALL0_NO_TXR_HORZ_CRD_BL_AG1_TGR1     0x02
UMASK_STALL0_NO_TXR_HORZ_CRD_BL_AG1_TGR2     0x04
UMASK_STALL0_NO_TXR_HORZ_CRD_BL_AG1_TGR3     0x08
UMASK_STALL0_NO_TXR_HORZ_CRD_BL_AG1_TGR4     0x10
UMASK_STALL0_NO_TXR_HORZ_CRD_BL_AG1_TGR5     0x20
UMASK_STALL0_NO_TXR_HORZ_CRD_BL_AG1_TGR6     0x40
UMASK_STALL0_NO_TXR_HORZ_CRD_BL_AG1_TGR7     0x80

EVENT_STALL1_NO_TXR_HORZ_CRD_BL_AG1_1          0xD7 CBOX|M2M|PBOX|SBOX
UMASK_STALL1_NO_TXR_HORZ_CRD_BL_AG1_1_TGR8     0x01
UMASK_STALL1_NO_TXR_HORZ_CRD_BL_AG1_1_TGR9     0x02
UMASK_STALL1_NO_TXR_HORZ_CRD_BL_AG1_1_TGR10    0x04

EVENT_TXR_HORZ_ADS_USED                 0xA6 CBOX|M2M|PBOX|SBOX
UMASK_TXR_HORZ_ADS_USED_AD_UNCRD        0x01
UMASK_TXR_HORZ_ADS_USED_BL_UNCRD        0x04
UMASK_TXR_HORZ_ADS_USED_AD_CRD          0x10
UMASK_TXR_HORZ_ADS_USED_BL_CRD          0x40
UMASK_TXR_HORZ_ADS_USED_AD_ALL          0x11
UMASK_TXR_HORZ_ADS_USED_BL_ALL          0x44

EVENT_TXR_HORZ_BYPASS                   0xA7 CBOX|M2M|PBOX|SBOX
UMASK_TXR_HORZ_BYPASS_AD_UNCRD          0x01
UMASK_TXR_HORZ_BYPASS_AK                0x02
UMASK_TXR_HORZ_BYPASS_BL_UNCRD          0x04
UMASK_TXR_HORZ_BYPASS_IV                0x08
UMASK_TXR_HORZ_BYPASS_AD_CRD            0x10
UMASK_TXR_HORZ_BYPASS_BL_CRD            0x40
UMASK_TXR_HORZ_BYPASS_AKC_UNCRD         0x80
UMASK_TXR_HORZ_BYPASS_AD_ALL            0x11
UMASK_TXR_HORZ_BYPASS_BL_ALL            0x44

EVENT_TXR_HORZ_CYCLES_FULL                   0xA2 CBOX|M2M|PBOX|SBOX
UMASK_TXR_HORZ_CYCLES_FULL_AD_UNCRD          0x01
UMASK_TXR_HORZ_CYCLES_FULL_AK                0x02
UMASK_TXR_HORZ_CYCLES_FULL_BL_UNCRD          0x04
UMASK_TXR_HORZ_CYCLES_FULL_IV                0x08
UMASK_TXR_HORZ_CYCLES_FULL_AD_CRD            0x10
UMASK_TXR_HORZ_CYCLES_FULL_BL_CRD            0x40
UMASK_TXR_HORZ_CYCLES_FULL_AKC_UNCRD         0x80
UMASK_TXR_HORZ_CYCLES_FULL_AD_ALL            0x11
UMASK_TXR_HORZ_CYCLES_FULL_BL_ALL            0x44

EVENT_TXR_HORZ_CYCLES_NE                   0xA3 CBOX|M2M|PBOX|SBOX
UMASK_TXR_HORZ_CYCLES_NE_AD_UNCRD          0x01
UMASK_TXR_HORZ_CYCLES_NE_AK                0x02
UMASK_TXR_HORZ_CYCLES_NE_BL_UNCRD          0x04
UMASK_TXR_HORZ_CYCLES_NE_IV                0x08
UMASK_TXR_HORZ_CYCLES_NE_AD_CRD            0x10
UMASK_TXR_HORZ_CYCLES_NE_BL_CRD            0x40
UMASK_TXR_HORZ_CYCLES_NE_AKC_UNCRD         0x80
UMASK_TXR_HORZ_CYCLES_NE_AD_ALL            0x11
UMASK_TXR_HORZ_CYCLES_NE_BL_ALL            0x44

EVENT_TXR_HORZ_INSERTS                   0xA1 CBOX|M2M|PBOX|SBOX
UMASK_TXR_HORZ_INSERTS_AD_UNCRD          0x01
UMASK_TXR_HORZ_INSERTS_AK                0x02
UMASK_TXR_HORZ_INSERTS_BL_UNCRD          0x04
UMASK_TXR_HORZ_INSERTS_IV                0x08
UMASK_TXR_HORZ_INSERTS_AD_CRD            0x10
UMASK_TXR_HORZ_INSERTS_BL_CRD            0x40
UMASK_TXR_HORZ_INSERTS_AKC_UNCRD         0x80
UMASK_TXR_HORZ_INSERTS_AD_ALL            0x11
UMASK_TXR_HORZ_INSERTS_BL_ALL            0x44

EVENT_TXR_HORZ_NACK                   0xA4 CBOX|M2M|PBOX|SBOX
UMASK_TXR_HORZ_NACK_AD_UNCRD          0x01
UMASK_TXR_HORZ_NACK_AK                0x02
UMASK_TXR_HORZ_NACK_BL_UNCRD          0x04
UMASK_TXR_HORZ_NACK_IV                0x08
UMASK_TXR_HORZ_NACK_AD_CRD            0x10
UMASK_TXR_HORZ_NACK_BL_CRD            0x40
UMASK_TXR_HORZ_NACK_AKC_UNCRD         0x80
UMASK_TXR_HORZ_NACK_AD_ALL            0x11
UMASK_TXR_HORZ_NACK_BL_ALL            0x44

# Shouldn't this event be only allowed for CBOX*C0?
EVENT_TXR_HORZ_OCCUPANCY                   0xA0 CBOX|M2M|PBOX|SBOX
UMASK_TXR_HORZ_OCCUPANCY_AD_UNCRD          0x01
UMASK_TXR_HORZ_OCCUPANCY_AK                0x02
UMASK_TXR_HORZ_OCCUPANCY_BL_UNCRD          0x04
UMASK_TXR_HORZ_OCCUPANCY_IV                0x08
UMASK_TXR_HORZ_OCCUPANCY_AD_CRD            0x10
UMASK_TXR_HORZ_OCCUPANCY_BL_CRD            0x40
UMASK_TXR_HORZ_OCCUPANCY_AKC_UNCRD         0x80
UMASK_TXR_HORZ_OCCUPANCY_AD_ALL            0x11
UMASK_TXR_HORZ_OCCUPANCY_BL_ALL            0x44

EVENT_TXR_HORZ_STARVED                   0xA5 CBOX|M2M|PBOX|SBOX
UMASK_TXR_HORZ_STARVED_AD_UNCRD          0x01
UMASK_TXR_HORZ_STARVED_AK                0x02
UMASK_TXR_HORZ_STARVED_BL_UNCRD          0x04
UMASK_TXR_HORZ_STARVED_IV                0x08
UMASK_TXR_HORZ_STARVED_AKC_UNCRD         0x80
UMASK_TXR_HORZ_STARVED_AD_ALL            0x01
UMASK_TXR_HORZ_STARVED_BL_ALL            0x04

EVENT_TXR_VERT_ADS_USED                 0x9C CBOX|M2M|PBOX|SBOX
UMASK_TXR_VERT_ADS_USED_AD_AG0          0x01
UMASK_TXR_VERT_ADS_USED_BL_AG0          0x04
UMASK_TXR_VERT_ADS_USED_AD_AG1          0x10
UMASK_TXR_VERT_ADS_USED_BL_AG1          0x40
UMASK_TXR_VERT_ADS_USED_AD_ALL          0x11
UMASK_TXR_VERT_ADS_USED_BL_ALL          0x44

EVENT_TXR_VERT_BYPASS0                 0x9D CBOX|M2M|PBOX|SBOX
UMASK_TXR_VERT_BYPASS0_AD_AG0          0x01
UMASK_TXR_VERT_BYPASS0_AK_AG0          0x02
UMASK_TXR_VERT_BYPASS0_BL_AG0          0x04
UMASK_TXR_VERT_BYPASS0_IV_AG1          0x08
UMASK_TXR_VERT_BYPASS0_AD_AG1          0x10
UMASK_TXR_VERT_BYPASS0_AK_AG1          0x20
UMASK_TXR_VERT_BYPASS0_BL_AG1          0x40
UMASK_TXR_VERT_BYPASS0_AD_ALL          0x11
UMASK_TXR_VERT_BYPASS0_AK_ALL          0x22
UMASK_TXR_VERT_BYPASS0_BL_ALL          0x44

EVENT_TXR_VERT_BYPASS1                0x9E CBOX|M2M|PBOX|SBOX
UMASK_TXR_VERT_BYPASS1_AKC_AG0        0x01
UMASK_TXR_VERT_BYPASS1_AKC_AG1        0x02
UMASK_TXR_VERT_BYPASS1_AKC_ALL        0x03

EVENT_TXR_VERT_CYCLES_FULL0                   0x94 CBOX|M2M|PBOX|SBOX
UMASK_TXR_VERT_CYCLES_FULL0_AD_AG0            0x01
UMASK_TXR_VERT_CYCLES_FULL0_AK_AG0            0x02
UMASK_TXR_VERT_CYCLES_FULL0_BL_AG0            0x04
UMASK_TXR_VERT_CYCLES_FULL0_IV_AG0            0x08
UMASK_TXR_VERT_CYCLES_FULL0_AD_AG1            0x10
UMASK_TXR_VERT_CYCLES_FULL0_AK_AG1            0x20
UMASK_TXR_VERT_CYCLES_FULL0_BL_AG1            0x40
UMASK_TXR_VERT_CYCLES_FULL0_AD_ALL            0x11
UMASK_TXR_VERT_CYCLES_FULL0_AK_ALL            0x22
UMASK_TXR_VERT_CYCLES_FULL0_BL_ALL            0x44

EVENT_TXR_VERT_CYCLES_FULL1                   0x95 CBOX|M2M|PBOX|SBOX
UMASK_TXR_VERT_CYCLES_FULL1_AKC_AG0           0x01
UMASK_TXR_VERT_CYCLES_FULL1_AKC_AG1           0x02
UMASK_TXR_VERT_CYCLES_FULL1_AKC_ALL           0x03

EVENT_TXR_VERT_CYCLES_NE0                   0x96 CBOX|M2M|PBOX|SBOX
UMASK_TXR_VERT_CYCLES_NE0_AD_AG0            0x01
UMASK_TXR_VERT_CYCLES_NE0_AK_AG0            0x02
UMASK_TXR_VERT_CYCLES_NE0_BL_AG0            0x04
UMASK_TXR_VERT_CYCLES_NE0_IV_AG0            0x08
UMASK_TXR_VERT_CYCLES_NE0_AD_AG1            0x10
UMASK_TXR_VERT_CYCLES_NE0_AK_AG1            0x20
UMASK_TXR_VERT_CYCLES_NE0_BL_AG1            0x40
UMASK_TXR_VERT_CYCLES_NE0_AD_ALL            0x11
UMASK_TXR_VERT_CYCLES_NE0_AK_ALL            0x22
UMASK_TXR_VERT_CYCLES_NE0_BL_ALL            0x44

EVENT_TXR_VERT_CYCLES_NE1                   0x97 CBOX|M2M|PBOX|SBOX
UMASK_TXR_VERT_CYCLES_NE1_AKC_AG0           0x01
UMASK_TXR_VERT_CYCLES_NE1_AKC_AG1           0x02
UMASK_TXR_VERT_CYCLES_NE1_AKC_ALL           0x03

EVENT_TXR_VERT_INSERTS0                      0x92 CBOX|M2M|PBOX|SBOX
UMASK_TXR_VERT_INSERTS0_AD_AG0               0x01
UMASK_TXR_VERT_INSERTS0_AK_AG0               0x02
UMASK_TXR_VERT_INSERTS0_BL_AG0               0x04
UMASK_TXR_VERT_INSERTS0_IV_AG0               0x08
UMASK_TXR_VERT_INSERTS0_AD_AG1               0x10
UMASK_TXR_VERT_INSERTS0_AK_AG1               0x20
UMASK_TXR_VERT_INSERTS0_BL_AG1               0x40
UMASK_TXR_VERT_INSERTS0_AD_ALL               0x11
UMASK_TXR_VERT_INSERTS0_AK_ALL               0x22
UMASK_TXR_VERT_INSERTS0_BL_ALL               0x44

EVENT_TXR_VERT_INSERTS1                      0x93 CBOX|M2M|PBOX|SBOX
UMASK_TXR_VERT_INSERTS1_AKC_AG0              0x01
UMASK_TXR_VERT_INSERTS1_AKC_AG1              0x02
UMASK_TXR_VERT_INSERTS1_AKC_ALL              0x03

EVENT_TXR_VERT_NACK0                      0x98 CBOX|M2M|PBOX|SBOX
UMASK_TXR_VERT_NACK0_AD_AG0               0x01
UMASK_TXR_VERT_NACK0_AK_AG0               0x02
UMASK_TXR_VERT_NACK0_BL_AG0               0x04
UMASK_TXR_VERT_NACK0_IV_AG0               0x08
UMASK_TXR_VERT_NACK0_AD_AG1               0x10
UMASK_TXR_VERT_NACK0_AK_AG1               0x20
UMASK_TXR_VERT_NACK0_BL_AG1               0x40
UMASK_TXR_VERT_NACK0_AD_ALL               0x11
UMASK_TXR_VERT_NACK0_AK_ALL               0x22
UMASK_TXR_VERT_NACK0_BL_ALL               0x44

EVENT_TXR_VERT_NACK1                      0x99 CBOX|M2M|PBOX|SBOX
UMASK_TXR_VERT_NACK1_AKC_AG0              0x01
UMASK_TXR_VERT_NACK1_AKC_AG1              0x02
UMASK_TXR_VERT_NACK1_AKC_ALL              0x03

# Shouldn't this event be only allowed for CBOX*C0?
EVENT_TXR_VERT_OCCUPANCY0                      0x90 CBOX|M2M|PBOX|SBOX
UMASK_TXR_VERT_OCCUPANCY0_AD_AG0               0x01
UMASK_TXR_VERT_OCCUPANCY0_AK_AG0               0x02
UMASK_TXR_VERT_OCCUPANCY0_BL_AG0               0x04
UMASK_TXR_VERT_OCCUPANCY0_IV_AG0               0x08
UMASK_TXR_VERT_OCCUPANCY0_AD_AG1               0x10
UMASK_TXR_VERT_OCCUPANCY0_AK_AG1               0x20
UMASK_TXR_VERT_OCCUPANCY0_BL_AG1               0x40
UMASK_TXR_VERT_OCCUPANCY0_AD_ALL               0x11
UMASK_TXR_VERT_OCCUPANCY0_AK_ALL               0x22
UMASK_TXR_VERT_OCCUPANCY0_BL_ALL               0x44

# Shouldn't this event be only allowed for CBOX*C0?
EVENT_TXR_VERT_OCCUPANCY1                      0x91 CBOX|M2M|PBOX|SBOX
UMASK_TXR_VERT_OCCUPANCY1_AKC_AG0              0x01
UMASK_TXR_VERT_OCCUPANCY1_AKC_AG1              0x02
UMASK_TXR_VERT_OCCUPANCY1_AKC_ALL              0x03

EVENT_TXR_VERT_STARVED0                      0x9A CBOX|M2M|PBOX|SBOX
UMASK_TXR_VERT_STARVED0_AD_AG0               0x01
UMASK_TXR_VERT_STARVED0_AK_AG0               0x02
UMASK_TXR_VERT_STARVED0_BL_AG0               0x04
UMASK_TXR_VERT_STARVED0_IV_AG0               0x08
UMASK_TXR_VERT_STARVED0_AD_AG1               0x10
UMASK_TXR_VERT_STARVED0_AK_AG1               0x20
UMASK_TXR_VERT_STARVED0_BL_AG1               0x40
UMASK_TXR_VERT_STARVED0_AD_ALL               0x11
UMASK_TXR_VERT_STARVED0_AK_ALL               0x22
UMASK_TXR_VERT_STARVED0_BL_ALL               0x44

EVENT_TXR_VERT_STARVED1                      0x9B CBOX|M2M|PBOX|SBOX
UMASK_TXR_VERT_STARVED1_AKC_AG0              0x01
UMASK_TXR_VERT_STARVED1_AKC_AG1              0x02
UMASK_TXR_VERT_STARVED1_TGC                  0x04
UMASK_TXR_VERT_STARVED1_AKC_ALL              0x03

EVENT_VERT_RING_AD_IN_USE               0xB0 CBOX|M2M|PBOX|SBOX
UMASK_VERT_RING_AD_IN_USE_UP_EVEN       0x01
UMASK_VERT_RING_AD_IN_USE_UP_ODD        0x02
UMASK_VERT_RING_AD_IN_USE_DN_EVEN       0x04
UMASK_VERT_RING_AD_IN_USE_DN_ODD        0x08

EVENT_VERT_RING_AKC_IN_USE               0xB4 CBOX|M2M|PBOX|SBOX
UMASK_VERT_RING_AKC_IN_USE_UP_EVEN       0x01
UMASK_VERT_RING_AKC_IN_USE_UP_ODD        0x02
UMASK_VERT_RING_AKC_IN_USE_DN_EVEN       0x04
UMASK_VERT_RING_AKC_IN_USE_DN_ODD        0x08

EVENT_VERT_RING_AK_IN_USE               0xB1 CBOX|M2M|PBOX|SBOX
UMASK_VERT_RING_AK_IN_USE_UP_EVEN       0x01
UMASK_VERT_RING_AK_IN_USE_UP_ODD        0x02
UMASK_VERT_RING_AK_IN_USE_DN_EVEN       0x04
UMASK_VERT_RING_AK_IN_USE_DN_ODD        0x08

EVENT_VERT_RING_BL_IN_USE               0xB2 CBOX|M2M|PBOX|SBOX
UMASK_VERT_RING_BL_IN_USE_UP_EVEN       0x01
UMASK_VERT_RING_BL_IN_USE_UP_ODD        0x02
UMASK_VERT_RING_BL_IN_USE_DN_EVEN       0x04
UMASK_VERT_RING_BL_IN_USE_DN_ODD        0x08

EVENT_VERT_RING_IV_IN_USE               0xB3 CBOX|M2M|PBOX|SBOX
UMASK_VERT_RING_IV_IN_USE_UP            0x01
UMASK_VERT_RING_IV_IN_USE_DN            0x04

EVENT_VERT_RING_TGC_IN_USE               0xB5 CBOX|M2M|PBOX|SBOX
UMASK_VERT_RING_TGC_IN_USE_UP_EVEN       0x01
UMASK_VERT_RING_TGC_IN_USE_UP_ODD        0x02
UMASK_VERT_RING_TGC_IN_USE_DN_EVEN       0x04
UMASK_VERT_RING_TGC_IN_USE_DN_ODD        0x08

EVENT_RING_SRC_THRTL                0xAE CBOX|M2M|PBOX|SBOX
UMASK_RING_SRC_THRTL                0x00

EVENT_PMM_QOS                           0x66 CBOX
UMASK_PMM_QOS_SLOW_INSERT               0x01
UMASK_PMM_QOS_DDR4_FAST_INSERT          0x02
UMASK_PMM_QOS_THROTTLE                  0x04
UMASK_PMM_QOS_REJ_IRQ                   0x08
UMASK_PMM_QOS_THROTTLE_PRQ              0x10
UMASK_PMM_QOS_THROTTLE_IRQ              0x20
UMASK_PMM_QOS_SLOWTORQ_SKIP             0x40

EVENT_PMM_QOS_OCCUPANCY                 0x67 CBOX
UMASK_PMM_QOS_OCCUPANCY_DDR_SLOW_FIFO   0x01
UMASK_PMM_QOS_OCCUPANCY_DDR_FAST_FIFO   0x02

EVENT_MEM_CLOCKTICKS                    0x00 MBOX
UMASK_MEM_CLOCKTICKS                    0x00

EVENT_PMM_CMD1                          0xEA MBOX
UMASK_PMM_CMD1_ALL                      0x01
UMASK_PMM_CMD1_RD                       0x02
UMASK_PMM_CMD1_WR                       0x04
UMASK_PMM_CMD1_UFILL_RD                 0x08
UMASK_PMM_CMD1_RPQ_GNTS                 0x10
UMASK_PMM_CMD1_WPQ_GNTS                 0x20
UMASK_PMM_CMD1_MISC_GNT                 0x40
UMASK_PMM_CMD1_MISC                     0x80

EVENT_PMM_CMD2                          0xEB MBOX
UMASK_PMM_CMD2_OPP_RD                   0x01
UMASK_PMM_CMD2_NODATA_EXP               0x02
UMASK_PMM_CMD2_NODATA_UNEXP             0x04
UMASK_PMM_CMD2_REQS_SLOT0               0x08
UMASK_PMM_CMD2_REQS_SLOT1               0x10
UMASK_PMM_CMD2_PMM_ECC_ERROR            0x20
UMASK_PMM_CMD2_PMM_ERID_ERROR           0x40
UMASK_PMM_CMD2_PMM_ERID_STARVED         0x80

EVENT_SB_ACCESSES                       0xD2 MBOX
UMASK_SB_ACCESSES_RD_ACCEPTS            0x01
UMASK_SB_ACCESSES_RD_REJECTS            0x02
UMASK_SB_ACCESSES_WR_ACCEPTS            0x04
UMASK_SB_ACCESSES_WR_REJECTS            0x08
UMASK_SB_ACCESSES_NM_RD_CMPS            0x10
UMASK_SB_ACCESSES_NM_WR_CMPS            0x20
UMASK_SB_ACCESSES_FM_RD_CMPS            0x40
UMASK_SB_ACCESSES_FM_WR_CMPS            0x80
UMASK_SB_ACCESSES_ACCEPTS               0x05
UMASK_SB_ACCESSES_REJECTS               0x0A

EVENT_CAS_COUNT                         0x04 MBOX
UMASK_CAS_COUNT_RD_REG                  0x01
UMASK_CAS_COUNT_RD_PRE_REG              0x02
UMASK_CAS_COUNT_RD_UNDERFILL            0x04
UMASK_CAS_COUNT_RD_PRE_UNDERFILL        0x08
UMASK_CAS_COUNT_WR_NONPRE               0x10
UMASK_CAS_COUNT_WR_PRE                  0x20
UMASK_CAS_COUNT_RD                      0x0F
UMASK_CAS_COUNT_WR                      0x30
UMASK_CAS_COUNT_ALL                     0x3F

EVENT_ACT_COUNT                         0x01 MBOX
UMASK_ACT_COUNT_BYP                     0x08

EVENT_ACT_PRIO                          0x28 MBOX
UMASK_ACT_PRIO_RD_NORMAL                0x01
UMASK_ACT_PRIO_RD_CRITICAL              0x02
UMASK_ACT_PRIO_RD_STARVED               0x04
UMASK_ACT_PRIO_WR_NORMAL                0x08
UMASK_ACT_PRIO_WR_CRITICAL              0x10
UMASK_ACT_PRIO_WR_STARVED               0x20
# Added by Thomas Gruber
UMASK_ACT_PRIO_RD_ANY                   0x07
UMASK_ACT_PRIO_WR_ANY                   0x38

EVENT_PRE_COUNT                         0x02 MBOX
UMASK_PRE_COUNT_PAGE_MISS               0x0C

EVENT_CAS_MM                            0x03 MBOX
UMASK_CAS_MM_RD_RMM                     0x01
UMASK_CAS_MM_RD_WMM                     0x02
UMASK_CAS_MM_WR_RMM                     0x04
UMASK_CAS_MM_WR_WMM                     0x08

EVENT_CRIT_MINOR_CAS                    0x2B MBOX
UMASK_CRIT_MINOR_CAS_RD_PCH0            0x01
UMASK_CRIT_MINOR_CAS_RD_PCH1            0x02
UMASK_CRIT_MINOR_CAS_WR_PCH0            0x04
UMASK_CRIT_MINOR_CAS_WR_PCH1            0x08
# Added by Thomas Gruber
UMASK_CRIT_MINOR_CAS_RD_ANY             0x03
UMASK_CRIT_MINOR_CAS_WR_ANY             0x0C

EVENT_PMM_RPQ_OCCUPANCY                 0xE0 MBOX
UMASK_PMM_RPQ_OCCUPANCY_NO_GNT          0x02
UMASK_PMM_RPQ_OCCUPANCY_GNT_WAIT        0x04

EVENT_PMM_RPQ_CYCLES_FULL               0xE2 MBOX
UMASK_PMM_RPQ_CYCLES_FULL               0x00

EVENT_PMM_RPQ_CYCLES_NE                 0xE1 MBOX
UMASK_PMM_RPQ_CYCLES_NE                 0x00

EVENT_PMM_WPQ_OCCUPANCY                 0xE4 MBOX
UMASK_PMM_WPQ_OCCUPANCY_CAS             0x02
UMASK_PMM_WPQ_OCCUPANCY_PWR             0x04

EVENT_PMM_WPQ_CYCLES_FULL               0xE6 MBOX
UMASK_PMM_WPQ_CYCLES_FULL               0x00

EVENT_PMM_WPQ_CYCLES_NE                 0xE5 MBOX
UMASK_PMM_WPQ_CYCLES_NE                 0x00

EVENT_PMM_WPQ_FLUSH                     0xE8 MBOX
UMASK_PMM_WPQ_FLUSH                     0x00

EVENT_PMM_WPQ_FLUSH_CYC                 0xE9 MBOX
UMASK_PMM_WPQ_FLUSH_CYC                 0x00

EVENT_PMM_MAJMODE1                      0xEC MBOX
UMASK_PMM_MAJMODE1_RMM_CYC              0x01
UMASK_PMM_MAJMODE1_WMM_CYC              0x02
UMASK_PMM_MAJMODE1_PWMM_CYC             0x04
UMASK_PMM_MAJMODE1_WMM_ENTER            0x08
UMASK_PMM_MAJMODE1_WMM_EXIT             0x10
UMASK_PMM_MAJMODE1_PWMM_ENTER           0x20
UMASK_PMM_MAJMODE1_PWMM_EXIT            0x40

EVENT_PMM_MAJMODE2                      0xED MBOX
UMASK_PMM_MAJMODE2_PMM_CYC              0x01
UMASK_PMM_MAJMODE2_DDR_CYC              0x02
UMASK_PMM_MAJMODE2_PMM_ENTER            0x04
UMASK_PMM_MAJMODE2_DDR_ENTER            0x08

EVENT_MAJOR_MODES                       0x07 MBOX
UMASK_MAJOR_MODES_PREF_RD               0x01
UMASK_MAJOR_MODES_STARVED_RD            0x02
UMASK_MAJOR_MODES_PREF_WR               0x04
UMASK_MAJOR_MODES_STARVED_WR            0x08
# Added by Thomas Gruber
UMASK_MAJOR_MODES_ANY_RD                0x03
UMASK_MAJOR_MODES_ANY_WR                0x0C

EVENT_MAJOR_MODE_CHANGE_PCH0            0x50 MBOX
UMASK_MAJOR_MODE_CHANGE_PCH0_PR_TO_SW   0x01
UMASK_MAJOR_MODE_CHANGE_PCH0_PR_TO_PW   0x02
UMASK_MAJOR_MODE_CHANGE_PCH0_SW_TO_PR   0x04
UMASK_MAJOR_MODE_CHANGE_PCH0_SW_TO_PW   0x08
UMASK_MAJOR_MODE_CHANGE_PCH0_SR_TO_PR   0x10
UMASK_MAJOR_MODE_CHANGE_PCH0_SR_TO_PW   0x20
UMASK_MAJOR_MODE_CHANGE_PCH0_PW_TO_SR   0x40
UMASK_MAJOR_MODE_CHANGE_PCH0_PW_TO_PR   0x80

EVENT_MAJOR_MODE_CHANGE_PCH1            0x51 MBOX
UMASK_MAJOR_MODE_CHANGE_PCH1_PR_TO_SW   0x01
UMASK_MAJOR_MODE_CHANGE_PCH1_PR_TO_PW   0x02
UMASK_MAJOR_MODE_CHANGE_PCH1_SW_TO_PR   0x04
UMASK_MAJOR_MODE_CHANGE_PCH1_SW_TO_PW   0x08
UMASK_MAJOR_MODE_CHANGE_PCH1_SR_TO_PR   0x10
UMASK_MAJOR_MODE_CHANGE_PCH1_SR_TO_PW   0x20
UMASK_MAJOR_MODE_CHANGE_PCH1_PW_TO_SR   0x40
UMASK_MAJOR_MODE_CHANGE_PCH1_PW_TO_PR   0x80

EVENT_MAJOR_MODE_VOTE_MISMATCH          0x52 MBOX
UMASK_MAJOR_MODE_VOTE_MISMATCH_PCH0     0x01
UMASK_MAJOR_MODE_VOTE_MISMATCH_PCH1     0x02
# Added by Thomas Gruber
UMASK_MAJOR_MODE_VOTE_MISMATCH_ANY      0x03

#can be filtered by rank
EVENT_POWER_CKE_CYCLES                  0x47 MBOX
UMASK_POWER_CKE_CYCLES_LOW_0            0x01
UMASK_POWER_CKE_CYCLES_LOW_1            0x02
UMASK_POWER_CKE_CYCLES_LOW_2            0x04
UMASK_POWER_CKE_CYCLES_LOW_3            0x08

#can be filtered by rank
EVENT_POWER_CRIT_THROTTLE_CYCLES        0x86 MBOX
UMASK_POWER_CRIT_THROTTLE_CYCLES_SLOT0  0x01
UMASK_POWER_CRIT_THROTTLE_CYCLES_SLOT1  0x02
# Added by Thomas Gruber
UMASK_POWER_CRIT_THROTTLE_CYCLES_ANY    0x03

#can be filtered by rank
EVENT_POWER_THROTTLE_CYCLES             0x46 MBOX
UMASK_POWER_THROTTLE_CYCLES_SLOT0       0x01
UMASK_POWER_THROTTLE_CYCLES_SLOT1       0x02
# Added by Thomas Gruber
UMASK_POWER_THROTTLE_CYCLES_ANY         0x03

EVENT_PREEMPTION                        0x08 MBOX
UMASK_PREEMPTION_RD_PCH0                0x01
UMASK_PREEMPTION_WR_PCH0                0x02
UMASK_PREEMPTION_RD_PCH1                0x04
UMASK_PREEMPTION_WR_PCH1                0x08
# Added by Thomas Gruber
UMASK_PREEMPTION_RD_ANY                 0x05
UMASK_PREEMPTION_WR_ANY                 0x09

EVENT_PREEMPTION_AS                     0x1B MBOX
UMASK_PREEMPTION_AS_PCH0                0x01
UMASK_PREEMPTION_AS_PCH1                0x02
# Added by Thomas Gruber
UMASK_PREEMPTION_AS_ANY                 0x03

EVENT_PREEMPTION_MM_SWITCH              0x1C MBOX
UMASK_PREEMPTION_MM_SWITCH_WMM_PCH0     0x01
UMASK_PREEMPTION_MM_SWITCH_RMM_PCH0     0x02
UMASK_PREEMPTION_MM_SWITCH_WMM_PCH1     0x04
UMASK_PREEMPTION_MM_SWITCH_RMM_PCH1     0x08
# Added by Thomas Gruber
UMASK_PREEMPTION_MM_SWITCH_WMM_ANY      0x05
UMASK_PREEMPTION_MM_SWITCH_RMM_ANY      0x0A

EVENT_RD_CAS_PRIO                       0x26 MBOX
UMASK_RD_CAS_PRIO_NORMAL                0x01
UMASK_RD_CAS_PRIO_CRITICAL              0x02
UMASK_RD_CAS_PRIO_STARVED               0x04

EVENT_WR_CAS_PRIO                       0x27 MBOX
UMASK_WR_CAS_PRIO_NORMAL                0x01
UMASK_WR_CAS_PRIO_CRITICAL              0x02
UMASK_WR_CAS_PRIO_STARVED               0x04

EVENT_RPQ_CYCLES_NE                     0x11 MBOX
UMASK_RPQ_CYCLES_NE_PCH0                0x01
UMASK_RPQ_CYCLES_NE_PCH1                0x02
# Added by Thomas Gruber
UMASK_RPQ_CYCLES_NE_ANY                 0x03

EVENT_RPQ_CYCLES_FULL_PCH0              0x12 MBOX
UMASK_RPQ_CYCLES_FULL_PCH0              0x00

EVENT_RPQ_CYCLES_FULL_PCH1              0x15 MBOX
UMASK_RPQ_CYCLES_FULL_PCH1              0x00

EVENT_RPQ_PRIO                          0x13 MBOX
UMASK_RPQ_PRIO_PCH0_LOW                 0x01
UMASK_RPQ_PRIO_PCH0_MED                 0x02
UMASK_RPQ_PRIO_PCH0_HIGH                0x04
UMASK_RPQ_PRIO_PCH0_CRIT                0x08
UMASK_RPQ_PRIO_PCH1_LOW                 0x10
UMASK_RPQ_PRIO_PCH1_MED                 0x20
UMASK_RPQ_PRIO_PCH1_HIGH                0x40
UMASK_RPQ_PRIO_PCH1_CRIT                0x80
# Added by Thomas Gruber
UMASK_RPQ_PRIO_ANY_LOW                  0x11
UMASK_RPQ_PRIO_ANY_MED                  0x22
UMASK_RPQ_PRIO_ANY_HIGH                 0x44
UMASK_RPQ_PRIO_ANY_CRIT                 0x88
UMASK_RPQ_PRIO_PCH0_ANY                 0x0F
UMASK_RPQ_PRIO_PCH1_ANY                 0xF0

EVENT_WPQ_CYCLES_NE                     0x21 MBOX
UMASK_WPQ_CYCLES_NE_PCH0                0x01
UMASK_WPQ_CYCLES_NE_PCH1                0x02
# Added by Thomas Gruber
UMASK_WPQ_CYCLES_NE_ANY                 0x03

EVENT_WPQ_CYCLES_FULL_PCH0              0x22 MBOX
UMASK_WPQ_CYCLES_FULL_PCH0              0x00

EVENT_WPQ_CYCLES_FULL_PCH1              0x16 MBOX
UMASK_WPQ_CYCLES_FULL_PCH1              0x00

EVENT_WPQ_PRIO                          0x14 MBOX
UMASK_WPQ_PRIO_PCH0_LOW                 0x01
UMASK_WPQ_PRIO_PCH0_MED                 0x02
UMASK_WPQ_PRIO_PCH0_HIGH                0x04
UMASK_WPQ_PRIO_PCH0_CRIT                0x08
UMASK_WPQ_PRIO_PCH1_LOW                 0x10
UMASK_WPQ_PRIO_PCH1_MED                 0x20
UMASK_WPQ_PRIO_PCH1_HIGH                0x40
UMASK_WPQ_PRIO_PCH1_CRIT                0x80
# Added by Thomas Gruber
UMASK_WPQ_PRIO_ANY_LOW                  0x11
UMASK_WPQ_PRIO_ANY_MED                  0x22
UMASK_WPQ_PRIO_ANY_HIGH                 0x44
UMASK_WPQ_PRIO_ANY_CRIT                 0x88
UMASK_WPQ_PRIO_PCH0_ANY                 0x0F
UMASK_WPQ_PRIO_PCH1_ANY                 0xF0

EVENT_WPQ_READ_HIT                      0x23 MBOX
UMASK_WPQ_READ_HIT_PCH0                 0x01
UMASK_WPQ_READ_HIT_PCH1                 0x02
# Added by Thomas Gruber
UMASK_WPQ_READ_HIT_ANY                  0x03

EVENT_WPQ_WRITE_HIT                     0x24 MBOX
UMASK_WPQ_WRITE_HIT_PCH0                0x01
UMASK_WPQ_WRITE_HIT_PCH1                0x02
# Added by Thomas Gruber
UMASK_WPQ_WRITE_HIT_ANY                 0x03

EVENT_SB_CYCLES_FULL                    0xD1 MBOX
UMASK_SB_CYCLES_FULL                    0x00

EVENT_SB_CYCLES_NE                      0xD0 MBOX
UMASK_SB_CYCLES_NE                      0x00

EVENT_SB_CANARY                         0xD9 MBOX
UMASK_SB_CANARY_ALLOC                   0x01
UMASK_SB_CANARY_DEALLOC                 0x02
UMASK_SB_CANARY_VLD                     0x04
UMASK_SB_CANARY_NM_RD_STARVED           0x08
UMASK_SB_CANARY_NM_WR_STARVED           0x10
UMASK_SB_CANARY_FM_RD_STARVED           0x20
UMASK_SB_CANARY_FM_WR_STARVED           0x40
UMASK_SB_CANARY_FM_TGR_WR_STARVED       0x80

EVENT_SB_INSERTS                        0xD6 MBOX
UMASK_SB_INSERTS_RDS                    0x01
UMASK_SB_INSERTS_WRS                    0x02
UMASK_SB_INSERTS_PMM_RDS                0x04
UMASK_SB_INSERTS_PMM_WRS                0x08
UMASK_SB_INSERTS_BLOCK_RDS              0x10
UMASK_SB_INSERTS_BLOCK_WRS              0x20
# Added by Thomas Gruber
UMASK_SB_INSERTS_ANY_RDS                0x15
UMASK_SB_INSERTS_ANY_WRS                0x2A

EVENT_SB_OCCUPANCY                      0xD5 MBOX
UMASK_SB_OCCUPANCY_RDS                  0x01
UMASK_SB_OCCUPANCY_PMM_RDS              0x04
UMASK_SB_OCCUPANCY_PMM_WRS              0x08
UMASK_SB_OCCUPANCY_BLOCK_RDS            0x20
UMASK_SB_OCCUPANCY_BLOCK_WRS            0x40
# Added by Thomas Gruber
UMASK_SB_OCCUPANCY_ANY_RDS              0x25
UMASK_SB_OCCUPANCY_ANY_WRS              0x48

EVENT_SB_REJECT                         0xD4 MBOX
UMASK_SB_REJECT_NM_SET_CNFLT            0x01
UMASK_SB_REJECT_FM_ADDR_CNFLT           0x02
UMASK_SB_REJECT_PATROL_SET_CNFLT        0x04
UMASK_SB_REJECT_CANARY                  0x08
UMASK_SB_REJECT_DDR_EARLY_CMP           0x20

EVENT_SB_STRV_ALLOC                     0xD7 MBOX
UMASK_SB_STRV_ALLOC_NM_RD               0x01
UMASK_SB_STRV_ALLOC_FM_RD               0x02
UMASK_SB_STRV_ALLOC_NM_WR               0x04
UMASK_SB_STRV_ALLOC_FM_WR               0x08
UMASK_SB_STRV_ALLOC_FM_TGR              0x10

EVENT_SB_STRV_DEALLOC                   0xDE MBOX
UMASK_SB_STRV_DEALLOC_NM_RD             0x01
UMASK_SB_STRV_DEALLOC_FM_RD             0x02
UMASK_SB_STRV_DEALLOC_NM_WR             0x04
UMASK_SB_STRV_DEALLOC_FM_WR             0x08
UMASK_SB_STRV_DEALLOC_FM_TGR            0x10

EVENT_SB_STRV_OCC                       0xD8 MBOX
UMASK_SB_STRV_OCC_NM_RD                 0x01
UMASK_SB_STRV_OCC_FM_RD                 0x02
UMASK_SB_STRV_OCC_NM_WR                 0x04
UMASK_SB_STRV_OCC_FM_WR                 0x08
UMASK_SB_STRV_OCC_FM_TGR                0x10

EVENT_SB_TAGGED                         0xDD MBOX
UMASK_SB_TAGGED_NEW                     0x01
UMASK_SB_TAGGED_RD_HIT                  0x02
UMASK_SB_TAGGED_RD_MISS                 0x04
UMASK_SB_TAGGED_DDR4_CMP                0x08
UMASK_SB_TAGGED_PMM0_CMP                0x10
UMASK_SB_TAGGED_PMM1_CMP                0x20
UMASK_SB_TAGGED_PMM2_CMP                0x40
UMASK_SB_TAGGED_OCC                     0x80

EVENT_SB_PREF_INSERTS                   0xDA MBOX
UMASK_SB_PREF_INSERTS_ALL               0x01
UMASK_SB_PREF_INSERTS_DDR               0x02
UMASK_SB_PREF_INSERTS_PMM               0x04

EVENT_SB_PREF_OCCUPANCY                 0xDB MBOX
UMASK_SB_PREF_OCCUPANCY_ALL             0x01
UMASK_SB_PREF_OCCUPANCY_DDR             0x02
UMASK_SB_PREF_OCCUPANCY_PMM             0x04

EVENT_OTHER_CTR                         0x3B MBOX
UMASK_OTHER_CTR_CTR0                    0x01
UMASK_OTHER_CTR_CTR1                    0x02
UMASK_OTHER_CTR_CTR2                    0x04
UMASK_OTHER_CTR_CTR3                    0x08
UMASK_OTHER_CTR_CTR4                    0x10

EVENT_PCLS                              0xA0 MBOX
UMASK_PCLS_RD                           0x01
UMASK_PCLS_WR                           0x02
UMASK_PCLS_TOTAL                        0x04

EVENT_DRAM_PRE_ALL                      0x44 MBOX
UMASK_DRAM_PRE_ALL                      0x00

EVENT_PARITY_ERRORS                     0x2C MBOX
UMASK_PARITY_ERRORS                     0x00

EVENT_POWER_CHANNEL_PPD                 0x85 MBOX
UMASK_POWER_CHANNEL_PPD                 0x00

EVENT_POWER_SELF_REFRESH                0x43 MBOX
UMASK_POWER_SELF_REFRESH                0x00

EVENT_MBOX_CLOCKTICKS                   0x00 MBOX0FIX|MBOX1FIX|MBOX2FIX|MBOX3FIX|MBOX4FIX|MBOX5FIX|MBOX6FIX|MBOX7FIX
UMASK_MBOX_CLOCKTICKS                   0x00

EVENT_DDR_READ_BYTES                    0x00 MDEV0C0|MDEV1C0|MDEV2C0|MDEV3C0
UMASK_DDR_READ_BYTES                    0x00

EVENT_DDR_WRITE_BYTES                   0x00 MDEV0C1|MDEV1C1|MDEV2C1|MDEV3C1
UMASK_DDR_WRITE_BYTES                   0x00

EVENT_PMM_READ_BYTES                    0x00 MDEV0C2|MDEV1C2|MDEV2C2|MDEV3C2
UMASK_PMM_READ_BYTES                    0x00

EVENT_PMM_WRITE_BYTES                   0x00 MDEV0C3|MDEV1C3|MDEV2C3|MDEV3C3
UMASK_PMM_WRITE_BYTES                   0x00

EVENT_IMC_DEV_CLOCKTICKS                0x00 MDEV0C4|MDEV1C4|MDEV2C4|MDEV3C4
UMASK_IMC_DEV_CLOCKTICKS                0x00

EVENT_DIRECT2UPI_NOT_TAKEN_CREDITS      0x28 M2M
UMASK_DIRECT2UPI_NOT_TAKEN_CREDITS      0x00

EVENT_DIRECT2UPI_NOT_TAKEN_DIRSTATE     0x27 M2M
UMASK_DIRECT2UPI_NOT_TAKEN_DIRSTATE     0x00

EVENT_DIRECT2UPI_TXN_OVERRIDE           0x29 M2M
UMASK_DIRECT2UPI_TXN_OVERRIDE           0x00

EVENT_DIRECT2CORE_NOT_TAKEN_DIRSTATE    0x24 M2M
UMASK_DIRECT2CORE_NOT_TAKEN_DIRSTATE    0x00

EVENT_DIRECT2CORE_TXN_OVERRIDE          0x25 M2M
UMASK_DIRECT2CORE_TXN_OVERRIDE          0x00

EVENT_DIRECT2CORE_NOT_TAKEN_NOTFORKED   0x60 M2M
UMASK_DIRECT2CORE_NOT_TAKEN_NOTFORKED   0x00

EVENT_IMC_READS                         0x37 M2M
UMASK_IMC_READS_NORMAL                  0x01 0x07 0x00
UMASK_IMC_READS_ISOCH                   0x02 0x07 0x00
UMASK_IMC_READS_ALL                     0x04 0x07 0x00
UMASK_IMC_READS_TO_DDR_AS_MEM           0x08 0x07 0x00
UMASK_IMC_READS_TO_DDR_AS_CACHE         0x10 0x07 0x00
UMASK_IMC_READS_TO_PMM                  0x20 0x07 0x00
UMASK_IMC_READS_FROM_TGR                0x40 0x07 0x00
UMASK_IMC_READS_CH0_NORMAL              0x01 0x01 0x00
UMASK_IMC_READS_CH0_ISOCH               0x02 0x01 0x00
UMASK_IMC_READS_CH0_ALL                 0x04 0x01 0x00
UMASK_IMC_READS_CH0_TO_DDR_AS_MEM       0x08 0x01 0x00
UMASK_IMC_READS_CH0_TO_DDR_AS_CACHE     0x10 0x01 0x00
UMASK_IMC_READS_CH0_TO_PMM              0x20 0x01 0x00
UMASK_IMC_READS_CH0_FROM_TGR            0x40 0x01 0x00
UMASK_IMC_READS_CH1_NORMAL              0x01 0x02 0x00
UMASK_IMC_READS_CH1_ISOCH               0x02 0x02 0x00
UMASK_IMC_READS_CH1_ALL                 0x04 0x02 0x00
UMASK_IMC_READS_CH1_TO_DDR_AS_MEM       0x08 0x02 0x00
UMASK_IMC_READS_CH1_TO_DDR_AS_CACHE     0x10 0x02 0x00
UMASK_IMC_READS_CH1_TO_PMM              0x20 0x02 0x00
UMASK_IMC_READS_CH1_FROM_TGR            0x40 0x02 0x00
#UMASK_IMC_READS_CH2_NORMAL              0x01 0x04 0x00
#UMASK_IMC_READS_CH2_ISOCH               0x02 0x04 0x00
#UMASK_IMC_READS_CH2_ALL                 0x04 0x04 0x00
UMASK_IMC_READS_CH2_FROM_TGR            0x40 0x04 0x00

EVENT_IMC_WRITES                        0x38 M2M
UMASK_IMC_WRITES_NI                     0x00 0x1E 0x00
UMASK_IMC_WRITES_FULL                   0x01 0x1C 0x00
UMASK_IMC_WRITES_PARTIAL                0x02 0x1C 0x00
UMASK_IMC_WRITES_FULL_ISOCH             0x04 0x1C 0x00
UMASK_IMC_WRITES_PARTIAL_ISOCH          0x08 0x1C 0x00
UMASK_IMC_WRITES_ALL                    0x10 0x1C 0x00
UMASK_IMC_WRITES_TO_DDR_AS_MEM          0x20 0x1C 0x00
UMASK_IMC_WRITES_TO_DDR_AS_CACHE        0x40 0x1C 0x00
UMASK_IMC_WRITES_FROM_TGR               0x00 0x1D 0x00
UMASK_IMC_WRITES_NI_MISS                0x00 0x1C 0x00
UMASK_IMC_WRITES_CH0_FULL               0x01 0x04 0x00
UMASK_IMC_WRITES_CH0_PARTIAL            0x02 0x04 0x00
UMASK_IMC_WRITES_CH0_FULL_ISOCH         0x04 0x04 0x00
UMASK_IMC_WRITES_CH0_PARTIAL_ISOCH      0x08 0x04 0x00
UMASK_IMC_WRITES_CH0_ALL                0x10 0x04 0x00
UMASK_IMC_WRITES_CH0_TO_DDR_AS_MEM      0x20 0x04 0x00
UMASK_IMC_WRITES_CH0_TO_DDR_AS_CACHE    0x40 0x04 0x00
UMASK_IMC_WRITES_CH0_TO_PMM             0x80 0x04 0x00
UMASK_IMC_WRITES_CH0_FROM_TGR           0x00 0x05 0x00
UMASK_IMC_WRITES_CH0_NI                 0x00 0x06 0x00
UMASK_IMC_WRITES_CH0_NI_MISS            0x00 0x20 0x00
UMASK_IMC_WRITES_CH1_FULL               0x01 0x08 0x00
UMASK_IMC_WRITES_CH1_PARTIAL            0x02 0x08 0x00
UMASK_IMC_WRITES_CH1_FULL_ISOCH         0x04 0x08 0x00
UMASK_IMC_WRITES_CH1_PARTIAL_ISOCH      0x08 0x08 0x00
UMASK_IMC_WRITES_CH1_ALL                0x10 0x08 0x00
UMASK_IMC_WRITES_CH1_TO_DDR_AS_MEM      0x20 0x08 0x00
UMASK_IMC_WRITES_CH1_TO_DDR_AS_CACHE    0x40 0x08 0x00
UMASK_IMC_WRITES_CH1_TO_PMM             0x80 0x08 0x00
UMASK_IMC_WRITES_CH1_FROM_TGR           0x00 0x09 0x00
UMASK_IMC_WRITES_CH1_NI                 0x00 0x0A 0x00
UMASK_IMC_WRITES_CH1_NI_MISS            0x00 0x0C 0x00

EVENT_TAG_HIT                           0x2C M2M
UMASK_TAG_HIT_NM_UFILL_HIT_CLEAN        0x04
UMASK_TAG_HIT_NM_UFILL_HIT_DIRTY        0x08

EVENT_TAG_MISS                          0x61 M2M
UMASK_TAG_MISS                          0x00

EVENT_BYPASS_M2M_INGRESS                0x21 M2M
UMASK_BYPASS_M2M_INGRESS_TAKEN          0x01
UMASK_BYPASS_M2M_INGRESS_NOT_TAKEN      0x02

EVENT_BYPASS_M2M_EGRESS                 0x22 M2M
UMASK_BYPASS_M2M_EGRESS_TAKEN           0x01
UMASK_BYPASS_M2M_EGRESS_NOT_TAKEN       0x02

EVENT_RXC_AD_INSERTS                    0x01 M2M
UMASK_RXC_AD_INSERTS                    0x00

EVENT_RXC_AD_OCCUPANCY                  0x02 M2M
UMASK_RXC_AD_OCCUPANCY                  0x00

EVENT_RXC_BL_INSERTS                    0x05 M2M
UMASK_RXC_BL_INSERTS                    0x00

EVENT_RXC_BL_OCCUPANCY                  0x06 M2M
UMASK_RXC_BL_OCCUPANCY                  0x00

EVENT_RXC_AD_CYCLES_FULL                0x04 M2M
UMASK_RXC_AD_CYCLES_FULL                0x00

EVENT_RXC_AD_CYCLES_NE                  0x03 M2M
UMASK_RXC_AD_CYCLES_NE                  0x00

EVENT_RXC_AD_PREF_OCCUPANCY             0x77 M2M
UMASK_RXC_AD_PREF_OCCUPANCY             0x00

EVENT_RXC_AK_WR_CMP                     0x5C M2M
UMASK_RXC_AK_WR_CMP                     0x00

EVENT_RXC_BL_CH0_WPQ_PROXY_CYCLES_NE    0x7C M2M
UMASK_RXC_BL_CH0_WPQ_PROXY_CYCLES_NE    0x00

EVENT_RXC_BL_CH0_WPQ_PROXY_OCCUPANCY    0x7B M2M
UMASK_RXC_BL_CH0_WPQ_PROXY_OCCUPANCY    0x00

EVENT_RXC_BL_CYCLES_FULL                0x08 M2M
UMASK_RXC_BL_CYCLES_FULL                0x00

EVENT_RXC_BL_CYCLES_NE                  0x07 M2M
UMASK_RXC_BL_CYCLES_NE                  0x00

EVENT_TXC_AD_INSERTS                    0x09 M2M
UMASK_TXC_AD_INSERTS                    0x00

EVENT_TXC_AD_OCCUPANCY                  0x0A M2M
UMASK_TXC_AD_OCCUPANCY                  0x00

EVENT_TXC_AD_CREDITS_ACQUIRED           0x0D M2M
UMASK_TXC_AD_CREDITS_ACQUIRED           0x00

EVENT_TXC_AD_CREDIT_OCCUPANCY           0x0E M2M
UMASK_TXC_AD_CREDIT_OCCUPANCY           0x00

EVENT_TXC_AD_CYCLES_FULL                0x0C M2M
UMASK_TXC_AD_CYCLES_FULL                0x00

EVENT_TXC_AD_CYCLES_NE                  0x0B M2M
UMASK_TXC_AD_CYCLES_NE                  0x00

EVENT_TXC_AD_NO_CREDIT_CYCLES           0x0F M2M
UMASK_TXC_AD_NO_CREDIT_CYCLES           0x00

EVENT_TXC_AD_NO_CREDIT_STALLED          0x10 M2M
UMASK_TXC_AD_NO_CREDIT_STALLED          0x00

EVENT_TXC_AKC_CREDITS                   0x5F M2M
UMASK_TXC_AKC_CREDITS                   0x00

EVENT_TXC_AK                            0x39 M2M
UMASK_TXC_AK_NDR                        0x01
UMASK_TXC_AK_CRD_CBO                    0x02

EVENT_TXC_AK_CREDITS_ACQUIRED           0x1D M2M
UMASK_TXC_AK_CREDITS_ACQUIRED_CMS0      0x01
UMASK_TXC_AK_CREDITS_ACQUIRED_CMS1      0x02

EVENT_TXC_AK_CYCLES                     0x14 M2M
UMASK_TXC_AK_CYCLES_FULL_CMS0           0x01
UMASK_TXC_AK_CYCLES_FULL_CMS1           0x02
UMASK_TXC_AK_CYCLES_ALL                 0x03
UMASK_TXC_AK_CYCLES_RDCRD0              0x08
UMASK_TXC_AK_CYCLES_WRCRD0              0x10
UMASK_TXC_AK_CYCLES_WRCMP0              0x20
UMASK_TXC_AK_CYCLES_RDCRD1              0x88
UMASK_TXC_AK_CYCLES_WRCRD1              0x90
UMASK_TXC_AK_CYCLES_WRCMP1              0xA0

EVENT_TXC_AK_CYCLES_NE                  0x13 M2M
UMASK_TXC_AK_CYCLES_NE_CMS0             0x01
UMASK_TXC_AK_CYCLES_NE_CMS1             0x02
UMASK_TXC_AK_CYCLES_NE_ALL              0x03
UMASK_TXC_AK_CYCLES_NE_RDCRD            0x08
UMASK_TXC_AK_CYCLES_NE_WRCRD            0x10
UMASK_TXC_AK_CYCLES_NE_WRCMP            0x20

EVENT_TXC_AK_INSERTS                    0x11 M2M
UMASK_TXC_AK_INSERTS_CMS0               0x01
UMASK_TXC_AK_INSERTS_CMS1               0x02
UMASK_TXC_AK_INSERTS_ALL                0x03
UMASK_TXC_AK_INSERTS_RDCRD              0x08
UMASK_TXC_AK_INSERTS_WRCRD              0x10
UMASK_TXC_AK_INSERTS_WRCMP              0x20
UMASK_TXC_AK_INSERTS_PREF_RD_CAM_HIT    0x40

EVENT_TXC_AK_NO_CREDIT_CYCLES           0x1F M2M
UMASK_TXC_AK_NO_CREDIT_CYCLES_CMS0      0x01
UMASK_TXC_AK_NO_CREDIT_CYCLES_CMS1      0x02
#Added by Thomas Gruber
UMASK_TXC_AK_NO_CREDIT_CYCLES_ALL       0x03

EVENT_TXC_AK_NO_CREDIT_STALLED          0x20 M2M
UMASK_TXC_AK_NO_CREDIT_STALLED_CMS0     0x01
UMASK_TXC_AK_NO_CREDIT_STALLED_CMS1     0x02
#Added by Thomas Gruber
UMASK_TXC_AK_NO_CREDIT_STALLED_ALL      0x03

EVENT_TXC_AK_OCCUPANCY                  0x12 MEM
UMASK_TXC_AK_OCCUPANCY_CMS0             0x01
UMASK_TXC_AK_OCCUPANCY_CMS1             0x02
UMASK_TXC_AK_OCCUPANCY_ALL              0x03
UMASK_TXC_AK_OCCUPANCY_RDCRD            0x08
UMASK_TXC_AK_OCCUPANCY_WRCRD            0x10
UMASK_TXC_AK_OCCUPANCY_WRCMP            0x20

EVENT_TXC_BL                            0x40 M2M
UMASK_TXC_BL_DRS_CACHE                  0x01
UMASK_TXC_BL_DRS_CORE                   0x02
UMASK_TXC_BL_DRS_UPI                    0x04

EVENT_TXC_BL_CREDITS_ACQUIRED           0x19 M2M
UMASK_TXC_BL_CREDITS_ACQUIRED_CMS0      0x01
UMASK_TXC_BL_CREDITS_ACQUIRED_CMS1      0x02
#Added by Thomas Gruber
UMASK_TXC_BL_CREDITS_ACQUIRED_ALL       0x03

EVENT_TXC_BL_CYCLES_FULL                0x18 M2M
UMASK_TXC_BL_CYCLES_FULL_CMS0           0x01
UMASK_TXC_BL_CYCLES_FULL_CMS1           0x02
UMASK_TXC_BL_CYCLES_FULL_ALL            0x03

EVENT_TXC_BL_CYCLES_NE                  0x17 M2M
UMASK_TXC_BL_CYCLES_NE_CMS0             0x01
UMASK_TXC_BL_CYCLES_NE_CMS1             0x02
UMASK_TXC_BL_CYCLES_NE_ALL              0x03

EVENT_TXC_BL_INSERTS                  0x15 M2M
UMASK_TXC_BL_INSERTS_CMS0             0x01
UMASK_TXC_BL_INSERTS_CMS1             0x02
#Added by Thomas Gruber
UMASK_TXC_BL_INSERTS_ALL              0x03

EVENT_TXC_BL_NO_CREDIT_CYCLES                  0x1B M2M
UMASK_TXC_BL_NO_CREDIT_CYCLES_CMS0             0x01
UMASK_TXC_BL_NO_CREDIT_CYCLES_CMS1             0x02
#Added by Thomas Gruber
UMASK_TXC_BL_NO_CREDIT_CYCLES_ALL              0x03

EVENT_TXC_BL_NO_CREDIT_STALLED                  0x1C M2M
UMASK_TXC_BL_NO_CREDIT_STALLED_CMS0             0x01
UMASK_TXC_BL_NO_CREDIT_STALLED_CMS1             0x02
#Added by Thomas Gruber
UMASK_TXC_BL_NO_CREDIT_STALLED_ALL              0x03

EVENT_DIRECTORY_HIT                     0x2A M2M
UMASK_DIRECTORY_HIT_DIRTY_I             0x01
UMASK_DIRECTORY_HIT_DIRTY_S             0x02
UMASK_DIRECTORY_HIT_DIRTY_P             0x04
UMASK_DIRECTORY_HIT_DIRTY_A             0x08
UMASK_DIRECTORY_HIT_CLEAN_I             0x10
UMASK_DIRECTORY_HIT_CLEAN_S             0x20
UMASK_DIRECTORY_HIT_CLEAN_P             0x40
UMASK_DIRECTORY_HIT_CLEAN_A             0x80
#Added by Thomas Gruber
UMASK_DIRECTORY_HIT_DIRTY_ANY           0x0F
UMASK_DIRECTORY_HIT_CLEAN_ANY           0xF0

EVENT_DIRECTORY_MISS                     0x2B M2M
UMASK_DIRECTORY_MISS_DIRTY_I             0x01
UMASK_DIRECTORY_MISS_DIRTY_S             0x02
UMASK_DIRECTORY_MISS_DIRTY_P             0x04
UMASK_DIRECTORY_MISS_DIRTY_A             0x08
UMASK_DIRECTORY_MISS_CLEAN_I             0x10
UMASK_DIRECTORY_MISS_CLEAN_S             0x20
UMASK_DIRECTORY_MISS_CLEAN_P             0x40
UMASK_DIRECTORY_MISS_CLEAN_A             0x80
#Added by Thomas Gruber
UMASK_DIRECTORY_MISS_DIRTY_ANY           0x0F
UMASK_DIRECTORY_MISS_CLEAN_ANY           0xF0

EVENT_PKT_MATCH                         0x4C M2M
UMASK_PKT_MATCH_MESH                    0x01
UMASK_PKT_MATCH_MC                      0x02

EVENT_RPQ_NO_REG_CRD                    0x43 M2M
UMASK_RPQ_NO_REG_CRD_CH0                0x01
UMASK_RPQ_NO_REG_CRD_CH1                0x02
UMASK_RPQ_NO_REG_CRD_CH2                0x04
# Added by Thomas Gruber
UMASK_RPQ_NO_REG_CRD_ALLCH              0x07

EVENT_RPQ_NO_REG_CRD_MEE                0x50 M2M
UMASK_RPQ_NO_REG_CRD_MEE_CHN0           0x01
UMASK_RPQ_NO_REG_CRD_MEE_CHN1           0x02
UMASK_RPQ_NO_REG_CRD_MEE_CHN2           0x04
# Added by Thomas Gruber
UMASK_RPQ_NO_REG_CRD_MEE_ALLCH          0x07

EVENT_RPQ_NO_SPEC_CRD                   0x44 M2M
UMASK_RPQ_NO_SPEC_CRD_CH0               0x01
UMASK_RPQ_NO_SPEC_CRD_CH1               0x02
UMASK_RPQ_NO_SPEC_CRD_CH2               0x04
# Added by Thomas Gruber
UMASK_RPQ_NO_SPEC_CRD_ALLCH             0x07

EVENT_RPQ_NO_REG_CRD_PMM                0x4F M2M
UMASK_RPQ_NO_REG_CRD_PMM_CHN0           0x01
UMASK_RPQ_NO_REG_CRD_PMM_CHN1           0x02
UMASK_RPQ_NO_REG_CRD_PMM_CHN2           0x04
# Added by Thomas Gruber
UMASK_RPQ_NO_REG_CRD_PMM_ALLCH          0x07

EVENT_WPQ_FLUSH                         0x58 M2M
UMASK_WPQ_FLUSH_CH0                     0x01
UMASK_WPQ_FLUSH_CH1                     0x02
UMASK_WPQ_FLUSH_CH2                     0x04
# Added by Thomas Gruber
UMASK_WPQ_FLUSH_ALLCH                   0x07

EVENT_WPQ_NO_REG_CRD                    0x4D M2M
UMASK_WPQ_NO_REG_CRD_CHN0               0x01
UMASK_WPQ_NO_REG_CRD_CHN1               0x02
UMASK_WPQ_NO_REG_CRD_CHN2               0x04
# Added by Thomas Gruber
UMASK_WPQ_NO_REG_CRD_ALLCH              0x07

EVENT_WPQ_NO_REG_CRD_MEE                0x52 M2M
UMASK_WPQ_NO_REG_CRD_MEE_CHN0           0x01
UMASK_WPQ_NO_REG_CRD_MEE_CHN1           0x02
UMASK_WPQ_NO_REG_CRD_MEE_CHN2           0x04
# Added by Thomas Gruber
UMASK_WPQ_NO_REG_CRD_MEE_ALLCH          0x07

EVENT_WPQ_NO_SPEC_CRD                    0x4E M2M
UMASK_WPQ_NO_SPEC_CRD_CHN0               0x01
UMASK_WPQ_NO_SPEC_CRD_CHN1               0x02
UMASK_WPQ_NO_SPEC_CRD_CHN2               0x04
# Added by Thomas Gruber
UMASK_WPQ_NO_SPEC_CRD_ALLCH              0x07

EVENT_WPQ_NO_REG_CRD_PMM                0x51 M2M
UMASK_WPQ_NO_REG_CRD_PMM_CHN0           0x01
UMASK_WPQ_NO_REG_CRD_PMM_CHN1           0x02
UMASK_WPQ_NO_REG_CRD_PMM_CHN2           0x04
# Added by Thomas Gruber
UMASK_WPQ_NO_REG_CRD_PMM_ALLCH          0x07

EVENT_TRACKER_FULL                      0x45 M2M
UMASK_TRACKER_FULL_CH0                  0x01
UMASK_TRACKER_FULL_CH1                  0x02
UMASK_TRACKER_FULL_CH2                  0x04
# Added by Thomas Gruber
UMASK_TRACKER_FULL_ALLCH                0x07

EVENT_TRACKER_NE                        0x46 M2M
UMASK_TRACKER_NE_CH0                    0x01
UMASK_TRACKER_NE_CH1                    0x02
UMASK_TRACKER_NE_CH2                    0x04
# Added by Thomas Gruber
UMASK_TRACKER_NE_ALLCH                  0x07

EVENT_TRACKER_OCCUPANCY                 0x47 M2M
UMASK_TRACKER_OCCUPANCY_CH0             0x01
UMASK_TRACKER_OCCUPANCY_CH1             0x02
UMASK_TRACKER_OCCUPANCY_CH2             0x04
# Added by Thomas Gruber
UMASK_TRACKER_OCCUPANCY_ALLCH           0x07

EVENT_TRACKER_INSERTS                   0x49 M2M
UMASK_TRACKER_INSERTS_CH0               0x01
UMASK_TRACKER_INSERTS_CH1               0x02
UMASK_TRACKER_INSERTS_CH2               0x04
# Added by Thomas Gruber
UMASK_TRACKER_INSERTS_ALLCH             0x07

EVENT_WR_TRACKER_FULL                   0x4A M2M
UMASK_WR_TRACKER_FULL_CH0               0x01
UMASK_WR_TRACKER_FULL_CH1               0x02
UMASK_WR_TRACKER_FULL_CH2               0x04
UMASK_WR_TRACKER_FULL_MIRR              0x08
# Added by Thomas Gruber
UMASK_WR_TRACKER_FULL_ALLCH             0x07

EVENT_WR_TRACKER_INSERTS                   0x56 M2M
UMASK_WR_TRACKER_INSERTS_CH0               0x01
UMASK_WR_TRACKER_INSERTS_CH1               0x02
UMASK_WR_TRACKER_INSERTS_CH2               0x04
# Added by Thomas Gruber
UMASK_WR_TRACKER_INSERTS_ALLCH             0x07

EVENT_WR_TRACKER_NE                        0x4B M2M
UMASK_WR_TRACKER_NE_CH0                    0x01
UMASK_WR_TRACKER_NE_CH1                    0x02
UMASK_WR_TRACKER_NE_CH2                    0x04
UMASK_WR_TRACKER_NE_MIRR                   0x08
UMASK_WR_TRACKER_NE_MIRR_NONTGR            0x10
UMASK_WR_TRACKER_NE_MIRR_PWR               0x20
# Added by Thomas Gruber
UMASK_WR_TRACKER_NE_ALLCH                  0x07

EVENT_WR_TRACKER_OCCUPANCY                        0x55 M2M
UMASK_WR_TRACKER_OCCUPANCY_CH0                    0x01
UMASK_WR_TRACKER_OCCUPANCY_CH1                    0x02
UMASK_WR_TRACKER_OCCUPANCY_CH2                    0x04
UMASK_WR_TRACKER_OCCUPANCY_MIRR                   0x08
UMASK_WR_TRACKER_OCCUPANCY_MIRR_NONTGR            0x10
UMASK_WR_TRACKER_OCCUPANCY_MIRR_PWR               0x20
# Added by Thomas Gruber
UMASK_WR_TRACKER_OCCUPANCY_ALLCH                  0x07

EVENT_WR_TRACKER_NONPOSTED_INSERTS                   0x63 M2M
UMASK_WR_TRACKER_NONPOSTED_INSERTS_CH0               0x01
UMASK_WR_TRACKER_NONPOSTED_INSERTS_CH1               0x02
UMASK_WR_TRACKER_NONPOSTED_INSERTS_CH2               0x04
# Added by Thomas Gruber
UMASK_WR_TRACKER_NONPOSTED_INSERTS_ALLCH             0x07

EVENT_WR_TRACKER_NONPOSTED_OCCUPANCY                   0x62 M2M
UMASK_WR_TRACKER_NONPOSTED_OCCUPANCY_CH0               0x01
UMASK_WR_TRACKER_NONPOSTED_OCCUPANCY_CH1               0x02
UMASK_WR_TRACKER_NONPOSTED_OCCUPANCY_CH2               0x04
# Added by Thomas Gruber
UMASK_WR_TRACKER_NONPOSTED_OCCUPANCY_ALLCH             0x07

EVENT_WR_TRACKER_POSTED_INSERTS                   0x5E M2M
UMASK_WR_TRACKER_POSTED_INSERTS_CH0               0x01
UMASK_WR_TRACKER_POSTED_INSERTS_CH1               0x02
UMASK_WR_TRACKER_POSTED_INSERTS_CH2               0x04
# Added by Thomas Gruber
UMASK_WR_TRACKER_POSTED_INSERTS_ALLCH             0x07

EVENT_WR_TRACKER_POSTED_OCCUPANCY                   0x5D M2M
UMASK_WR_TRACKER_POSTED_OCCUPANCY_CH0               0x01
UMASK_WR_TRACKER_POSTED_OCCUPANCY_CH1               0x02
UMASK_WR_TRACKER_POSTED_OCCUPANCY_CH2               0x04
# Added by Thomas Gruber
UMASK_WR_TRACKER_POSTED_OCCUPANCY_ALLCH             0x07

EVENT_PREFCAM_CYCLES_FULL               0x6B M2M
UMASK_PREFCAM_CYCLES_FULL_CH0           0x01
UMASK_PREFCAM_CYCLES_FULL_CH1           0x02
UMASK_PREFCAM_CYCLES_FULL_CH2           0x03
UMASK_PREFCAM_CYCLES_FULL_ALLCH         0x07

EVENT_PREFCAM_CYCLES_NE               0x6C M2M
UMASK_PREFCAM_CYCLES_NE_CH0           0x01
UMASK_PREFCAM_CYCLES_NE_CH1           0x02
UMASK_PREFCAM_CYCLES_NE_CH2           0x03
UMASK_PREFCAM_CYCLES_NE_ALLCH         0x07

EVENT_PREFCAM_OCCUPANCY               0x6A M2M
UMASK_PREFCAM_OCCUPANCY_CH0           0x01
UMASK_PREFCAM_OCCUPANCY_CH1           0x02
UMASK_PREFCAM_OCCUPANCY_CH2           0x03
UMASK_PREFCAM_OCCUPANCY_ALLCH         0x07

EVENT_PREFCAM_RESP_MISS               0x76 M2M
UMASK_PREFCAM_RESP_MISS_CH0           0x01
UMASK_PREFCAM_RESP_MISS_CH1           0x02
UMASK_PREFCAM_RESP_MISS_CH2           0x03
UMASK_PREFCAM_RESP_MISS_ALLCH         0x07

EVENT_PREFCAM_DEALLOCS                  0x6E M2M
UMASK_PREFCAM_DEALLOCS_CH0_HITA0_INVAL  0x01
UMASK_PREFCAM_DEALLOCS_CH0_HITA1_INVAL  0x02
UMASK_PREFCAM_DEALLOCS_CH0_MISS_INVAL   0x04
UMASK_PREFCAM_DEALLOCS_CH0_RSP_PDRESET  0x08
UMASK_PREFCAM_DEALLOCS_CH1_HITA0_INVAL  0x10
UMASK_PREFCAM_DEALLOCS_CH1_HITA1_INVAL  0x20
UMASK_PREFCAM_DEALLOCS_CH1_MISS_INVAL   0x40
UMASK_PREFCAM_DEALLOCS_CH1_RSP_PDRESET  0x80
UMASK_PREFCAM_DEALLOCS_CH2_HITA0_INVAL  0x00 0x01 0x00
UMASK_PREFCAM_DEALLOCS_CH2_HITA1_INVAL  0x00 0x02 0x00
UMASK_PREFCAM_DEALLOCS_CH2_MISS_INVAL   0x00 0x04 0x00
UMASK_PREFCAM_DEALLOCS_CH2_RSP_PDRESET  0x00 0x08 0x00
# Added by Thomas Gruber
UMASK_PREFCAM_DEALLOCS_HITA0_INVAL_ALLCH  0x11 0x01 0x00
UMASK_PREFCAM_DEALLOCS_HITA1_INVAL_ALLCH  0x22 0x02 0x00
UMASK_PREFCAM_DEALLOCS_MISS_INVAL_ALLCH   0x44 0x04 0x00
UMASK_PREFCAM_DEALLOCS_RSP_PDRESET_ALLCH  0x88 0x08 0x00

EVENT_PREFCAM_DEMAND_DROPS              0x6F M2M
UMASK_PREFCAM_DEMAND_DROPS_CH0_XPT      0x01
UMASK_PREFCAM_DEMAND_DROPS_CH0_UPI      0x02
UMASK_PREFCAM_DEMAND_DROPS_CH1_XPT      0x04
UMASK_PREFCAM_DEMAND_DROPS_CH1_UPI      0x08
UMASK_PREFCAM_DEMAND_DROPS_CH2_XPT      0x10
UMASK_PREFCAM_DEMAND_DROPS_CH2_UPI      0x20
UMASK_PREFCAM_DEMAND_DROPS_XPT_ALLCH    0x15
UMASK_PREFCAM_DEMAND_DROPS_UPI_ALLCH    0x2A

EVENT_PREFCAM_DEMAND_MERGE              0x74 M2M
UMASK_PREFCAM_DEMAND_MERGE_CH0_XPT      0x01
UMASK_PREFCAM_DEMAND_MERGE_CH0_UPI      0x02
UMASK_PREFCAM_DEMAND_MERGE_CH1_XPT      0x04
UMASK_PREFCAM_DEMAND_MERGE_CH1_UPI      0x08
UMASK_PREFCAM_DEMAND_MERGE_CH2_XPT      0x10
UMASK_PREFCAM_DEMAND_MERGE_CH2_UPI      0x20
UMASK_PREFCAM_DEMAND_MERGE_XPT_ALLCH    0x15
UMASK_PREFCAM_DEMAND_MERGE_UPI_ALLCH    0x2A

EVENT_PREFCAM_DROP_REASONS_CH0                      0x70 M2M
UMASK_PREFCAM_DROP_REASONS_CH0_PF_SECURE_DROP       0x01
UMASK_PREFCAM_DROP_REASONS_CH0_NOT_PF_SAD_REGION    0x02
UMASK_PREFCAM_DROP_REASONS_CH0_PF_CAM_HIT           0x04
UMASK_PREFCAM_DROP_REASONS_CH0_STOP_B2B             0x08
UMASK_PREFCAM_DROP_REASONS_CH0_ERRORBLK_RXC         0x10
UMASK_PREFCAM_DROP_REASONS_CH0_PF_AD_CRD            0x20
UMASK_PREFCAM_DROP_REASONS_CH0_PF_CAM_FULL          0x40
UMASK_PREFCAM_DROP_REASONS_CH0_WPQ_PROXY            0x80
UMASK_PREFCAM_DROP_REASONS_CH0_RPQ_PROXY            0x00 0x01 0x00
UMASK_PREFCAM_DROP_REASONS_CH0_XPT_THRESH           0x00 0x02 0x00
UMASK_PREFCAM_DROP_REASONS_CH0_UPI_THRESH           0x00 0x04 0x00

EVENT_PREFCAM_DROP_REASONS_CH1                      0x71 M2M
UMASK_PREFCAM_DROP_REASONS_CH1_PF_SECURE_DROP       0x01
UMASK_PREFCAM_DROP_REASONS_CH1_NOT_PF_SAD_REGION    0x02
UMASK_PREFCAM_DROP_REASONS_CH1_PF_CAM_HIT           0x04
UMASK_PREFCAM_DROP_REASONS_CH1_STOP_B2B             0x08
UMASK_PREFCAM_DROP_REASONS_CH1_ERRORBLK_RXC         0x10
UMASK_PREFCAM_DROP_REASONS_CH1_PF_AD_CRD            0x20
UMASK_PREFCAM_DROP_REASONS_CH1_PF_CAM_FULL          0x40
UMASK_PREFCAM_DROP_REASONS_CH1_WPQ_PROXY            0x80
UMASK_PREFCAM_DROP_REASONS_CH1_RPQ_PROXY            0x00 0x01 0x00
UMASK_PREFCAM_DROP_REASONS_CH1_XPT_THRESH           0x00 0x02 0x00
UMASK_PREFCAM_DROP_REASONS_CH1_UPI_THRESH           0x00 0x04 0x00

EVENT_PREFCAM_DROP_REASONS_CH2                      0x72 M2M
UMASK_PREFCAM_DROP_REASONS_CH2_PF_SECURE_DROP       0x01
UMASK_PREFCAM_DROP_REASONS_CH2_NOT_PF_SAD_REGION    0x02
UMASK_PREFCAM_DROP_REASONS_CH2_PF_CAM_HIT           0x04
UMASK_PREFCAM_DROP_REASONS_CH2_STOP_B2B             0x08
UMASK_PREFCAM_DROP_REASONS_CH2_ERRORBLK_RXC         0x10
UMASK_PREFCAM_DROP_REASONS_CH2_PF_AD_CRD            0x20
UMASK_PREFCAM_DROP_REASONS_CH2_PF_CAM_FULL          0x40
UMASK_PREFCAM_DROP_REASONS_CH2_WPQ_PROXY            0x80
UMASK_PREFCAM_DROP_REASONS_CH2_RPQ_PROXY            0x00 0x01 0x00
UMASK_PREFCAM_DROP_REASONS_CH2_XPT_THRESH           0x00 0x02 0x00
UMASK_PREFCAM_DROP_REASONS_CH2_UPI_THRESH           0x00 0x04 0x00

EVENT_PREFCAM_INSERTS              0x6D M2M
UMASK_PREFCAM_INSERTS_CH0_XPT      0x01
UMASK_PREFCAM_INSERTS_CH0_UPI      0x02
UMASK_PREFCAM_INSERTS_CH1_XPT      0x04
UMASK_PREFCAM_INSERTS_CH1_UPI      0x08
UMASK_PREFCAM_INSERTS_CH2_XPT      0x10
UMASK_PREFCAM_INSERTS_CH2_UPI      0x20
UMASK_PREFCAM_INSERTS_XPT_ALLCH    0x15
UMASK_PREFCAM_INSERTS_UPI_ALLCH    0x2A

EVENT_PREFCAM_RXC_DEALLOCS                      0x7A M2M
UMASK_PREFCAM_RXC_DEALLOCS_SQUASHED             0x01
UMASK_PREFCAM_RXC_DEALLOCS_1LM_POSTED           0x02
UMASK_PREFCAM_RXC_DEALLOCS_PMM_MEMMODE_ACCEPT   0x04
UMASK_PREFCAM_RXC_DEALLOCS_CIS                  0x08

EVENT_PREFCAM_CIS_DROPS     0x73 M2M
UMASK_PREFCAM_CIS_DROPS     0x00

EVENT_PREFCAM_RXC_CYCLES_NE     0x79 M2M
UMASK_PREFCAM_RXC_CYCLES_NE     0x00

EVENT_PREFCAM_RXC_INSERTS       0x78 M2M
UMASK_PREFCAM_RXC_INSERTS       0x00

EVENT_PREFCAM_RXC_OCCUPANCY     0x77 M2M
UMASK_PREFCAM_RXC_OCCUPANCY     0x00

EVENT_CMI_CH0_RPQ_PROXY_CYCLES_NE       0xF0 M2M
UMASK_CMI_CH0_RPQ_PROXY_CYCLES_NE       0x00

EVENT_CMI_CH0_RPQ_PROXY_OCCUPANCY       0x7F M2M
UMASK_CMI_CH0_RPQ_PROXY_OCCUPANCY       0x00

EVENT_CMI_CH0_WPQ_PROXY_CYCLES_NE       0x7E M2M
UMASK_CMI_CH0_WPQ_PROXY_CYCLES_NE       0x00

EVENT_CMI_CH0_WPQ_PROXY_OCCUPANCY       0x7D M2M
UMASK_CMI_CH0_WPQ_PROXY_OCCUPANCY       0x00

EVENT_MIRR_WRQ_INSERTS      0x64 M2M
UMASK_MIRR_WRQ_INSERTS      0x00

EVENT_MIRR_WRQ_OCCUPANCY    0x65 M2M
UMASK_MIRR_WRQ_OCCUPANCY    0x00

EVENT_SCOREBOARD_AD_RETRY_ACCEPTS       0x33 M2M
UMASK_SCOREBOARD_AD_RETRY_ACCEPTS       0x00

EVENT_SCOREBOARD_AD_RETRY_REJECTS       0x34 M2M
UMASK_SCOREBOARD_AD_RETRY_REJECTS       0x00

EVENT_SCOREBOARD_BL_RETRY_ACCEPTS       0x35 M2M
UMASK_SCOREBOARD_BL_RETRY_ACCEPTS       0x00

EVENT_SCOREBOARD_BL_RETRY_REJECTS       0x36 M2M
UMASK_SCOREBOARD_BL_RETRY_REJECTS       0x00

EVENT_SCOREBOARD_RD_ACCEPTS             0x2F M2M
UMASK_SCOREBOARD_RD_ACCEPTS             0x00

EVENT_SCOREBOARD_RD_REJECTS             0x30 M2M
UMASK_SCOREBOARD_RD_REJECTS             0x00

EVENT_SCOREBOARD_WR_ACCEPTS             0x31 M2M
UMASK_SCOREBOARD_WR_ACCEPTS             0x00

EVENT_SCOREBOARD_WR_REJECTS             0x32 M2M
UMASK_SCOREBOARD_WR_REJECTS             0x00

EVENT_TGR_AD_CREDITS                0x41 M2M
UMASK_TGR_AD_CREDITS                0x00

EVENT_TGR_BL_CREDITS                0x42 M2M
UMASK_TGR_BL_CREDITS                0x00

EVENT_M2M_CLOCKTICKS                    0x00 M2M
UMASK_M2M_CLOCKTICKS                    0x00

EVENT_PCI_CLOCKTICKS                    0x01 PBOX
UMASK_PCI_CLOCKTICKS                    0x00

EVENT_IIO_CREDITS_ACQUIRED              0x33 PBOX
UMASK_IIO_CREDITS_ACQUIRED_DRS_0        0x01
UMASK_IIO_CREDITS_ACQUIRED_DRS_1        0x02
UMASK_IIO_CREDITS_ACQUIRED_NCB_0        0x04
UMASK_IIO_CREDITS_ACQUIRED_NCB_1        0x08
UMASK_IIO_CREDITS_ACQUIRED_NCS_0        0x10
UMASK_IIO_CREDITS_ACQUIRED_NCS_1        0x20
# Added by Thomas Gruber
UMASK_IIO_CREDITS_ACQUIRED_DRS_ANY      0x03
UMASK_IIO_CREDITS_ACQUIRED_NCB_ANY      0x0C
UMASK_IIO_CREDITS_ACQUIRED_NCS_ANY      0x30

EVENT_IIO_CREDITS_REJECT                0x34 PBOX
UMASK_IIO_CREDITS_REJECT_DRS            0x08
UMASK_IIO_CREDITS_REJECT_NCB            0x10
UMASK_IIO_CREDITS_REJECT_NCS            0x20

EVENT_IIO_CREDITS_USED              0x32 PBOX
UMASK_IIO_CREDITS_USED_DRS_0        0x01
UMASK_IIO_CREDITS_USED_DRS_1        0x02
UMASK_IIO_CREDITS_USED_NCB_0        0x04
UMASK_IIO_CREDITS_USED_NCB_1        0x08
UMASK_IIO_CREDITS_USED_NCS_0        0x10
UMASK_IIO_CREDITS_USED_NCS_1        0x20
# Added by Thomas Gruber
UMASK_IIO_CREDITS_USED_DRS_ANY      0x03
UMASK_IIO_CREDITS_USED_NCB_ANY      0x0C
UMASK_IIO_CREDITS_USED_NCS_ANY      0x30

EVENT_RXC_CYCLES_NE                 0x10 PBOX
UMASK_RXC_CYCLES_NE_UPI_NCS         0x10
UMASK_RXC_CYCLES_NE_UPI_NCB         0x08
UMASK_RXC_CYCLES_NE_IIO_NCB         0x20
UMASK_RXC_CYCLES_NE_IIO_NCS         0x40
UMASK_RXC_CYCLES_NE_ALL             0x80

EVENT_RXC_INSERTS                   0x11 PBOX
UMASK_RXC_INSERTS_UPI_NCB           0x08
UMASK_RXC_INSERTS_UPI_NCS           0x10
UMASK_RXC_INSERTS_IIO_NCB           0x20
UMASK_RXC_INSERTS_IIO_NCS           0x40
UMASK_RXC_INSERTS_ALL               0x80

EVENT_TXC_CYCLES_FULL               0x25 PBOX
UMASK_TXC_CYCLES_FULL_AD_0          0x01
UMASK_TXC_CYCLES_FULL_AK_0          0x02
UMASK_TXC_CYCLES_FULL_BL_0          0x04
UMASK_TXC_CYCLES_FULL_PMM_BLOCK_1   0x08
UMASK_TXC_CYCLES_FULL_AD_1          0x10
UMASK_TXC_CYCLES_FULL_AK_1          0x20
UMASK_TXC_CYCLES_FULL_BL_1          0x40
UMASK_TXC_CYCLES_FULL_PMM_BLOCK_0   0x80
# Added by Thomas Gruber
UMASK_TXC_CYCLES_FULL_AD_ANY        0x11
UMASK_TXC_CYCLES_FULL_AK_ANY        0x22
UMASK_TXC_CYCLES_FULL_BL_ANY        0x44
UMASK_TXC_CYCLES_FULL_PMM_ANY       0x88

EVENT_TXC_CYCLES_NE                 0x23 PBOX
UMASK_TXC_CYCLES_NE_AD_0            0x01
UMASK_TXC_CYCLES_NE_AK_0            0x02
UMASK_TXC_CYCLES_NE_BL_0            0x04
UMASK_TXC_CYCLES_NE_PMM_DISTRESS_1  0x08
UMASK_TXC_CYCLES_NE_AD_1            0x10
UMASK_TXC_CYCLES_NE_AK_1            0x20
UMASK_TXC_CYCLES_NE_BL_1            0x40
UMASK_TXC_CYCLES_NE_PMM_DISTRESS_0  0x80
# Added by Thomas Gruber
UMASK_TXC_CYCLES_NE_AD_ANY        0x11
UMASK_TXC_CYCLES_NE_AK_ANY        0x22
UMASK_TXC_CYCLES_NE_BL_ANY        0x44
UMASK_TXC_CYCLES_NE_PMM_DISTRESS_ANY 0x88

EVENT_TXC_INSERTS                   0x24 PBOX
UMASK_TXC_INSERTS_AD_0              0x01
UMASK_TXC_INSERTS_BL_0              0x04
UMASK_TXC_INSERTS_AK_CRD_0          0x08
UMASK_TXC_INSERTS_AD_1              0x10
UMASK_TXC_INSERTS_BL_1              0x40
UMASK_TXC_INSERTS_AK_CRD_1          0x80
# Added by Thomas Gruber
UMASK_TXC_INSERTS_AD_ANY            0x11
UMASK_TXC_INSERTS_BL_ANY            0x44
UMASK_TXC_INSERTS_AK_CRD_ANY        0x88

EVENT_LOCAL_DED_P2P_CRD_TAKEN_0                 0x46 PBOX
UMASK_LOCAL_DED_P2P_CRD_TAKEN_0_M2IOSF0_NCB     0x01
UMASK_LOCAL_DED_P2P_CRD_TAKEN_0_M2IOSF0_NCS     0x02
UMASK_LOCAL_DED_P2P_CRD_TAKEN_0_M2IOSF1_NCB     0x04
UMASK_LOCAL_DED_P2P_CRD_TAKEN_0_M2IOSF1_NCS     0x08
UMASK_LOCAL_DED_P2P_CRD_TAKEN_0_M2IOSF2_NCB     0x10
UMASK_LOCAL_DED_P2P_CRD_TAKEN_0_M2IOSF2_NCS     0x20
UMASK_LOCAL_DED_P2P_CRD_TAKEN_0_M2IOSF3_NCB     0x40
UMASK_LOCAL_DED_P2P_CRD_TAKEN_0_M2IOSF3_NCS     0x80
# Added by Thomas Gruber
UMASK_LOCAL_DED_P2P_CRD_TAKEN_0_ANY_NCB         0x55
UMASK_LOCAL_DED_P2P_CRD_TAKEN_0_ANY_NCS         0xCC

EVENT_LOCAL_DED_P2P_CRD_TAKEN_1                 0x47 PBOX
UMASK_LOCAL_DED_P2P_CRD_TAKEN_1_M2IOSF4_NCB     0x01
UMASK_LOCAL_DED_P2P_CRD_TAKEN_1_M2IOSF4_NCS     0x02
UMASK_LOCAL_DED_P2P_CRD_TAKEN_1_M2IOSF5_NCB     0x04
UMASK_LOCAL_DED_P2P_CRD_TAKEN_1_M2IOSF5_NCS     0x08
# Added by Thomas Gruber
UMASK_LOCAL_DED_P2P_CRD_TAKEN_1_ANY_NCB         0x05
UMASK_LOCAL_DED_P2P_CRD_TAKEN_1_ANY_NCS         0x0C

EVENT_LOCAL_P2P_DED_RETURNED_0                  0x19 PBOX
UMASK_LOCAL_P2P_DED_RETURNED_0_MS2IOSF0_NCB     0x01
UMASK_LOCAL_P2P_DED_RETURNED_0_MS2IOSF0_NCS     0x02
UMASK_LOCAL_P2P_DED_RETURNED_0_MS2IOSF1_NCB     0x04
UMASK_LOCAL_P2P_DED_RETURNED_0_MS2IOSF1_NCS     0x08
UMASK_LOCAL_P2P_DED_RETURNED_0_MS2IOSF2_NCB     0x10
UMASK_LOCAL_P2P_DED_RETURNED_0_MS2IOSF2_NCS     0x20
UMASK_LOCAL_P2P_DED_RETURNED_0_MS2IOSF3_NCB     0x40
UMASK_LOCAL_P2P_DED_RETURNED_0_MS2IOSF3_NCS     0x80
# Added by Thomas Gruber
UMASK_LOCAL_P2P_DED_RETURNED_0_ANY_NCB          0x55
UMASK_LOCAL_P2P_DED_RETURNED_0_ANY_NCS          0xCC


EVENT_LOCAL_P2P_DED_RETURNED_1                  0x1A PBOX
UMASK_LOCAL_P2P_DED_RETURNED_1_MS2IOSF4_NCB     0x01
UMASK_LOCAL_P2P_DED_RETURNED_1_MS2IOSF4_NCS     0x02
UMASK_LOCAL_P2P_DED_RETURNED_1_MS2IOSF5_NCB     0x04
UMASK_LOCAL_P2P_DED_RETURNED_1_MS2IOSF5_NCS     0x08
# Added by Thomas Gruber
UMASK_LOCAL_P2P_DED_RETURNED_1_ANY_NCB          0x05
UMASK_LOCAL_P2P_DED_RETURNED_1_ANY_NCS          0x0C

EVENT_LOCAL_P2P_SHAR_RETURNED                   0x17 PBOX
UMASK_LOCAL_P2P_SHAR_RETURNED_AGENT_0           0x01
UMASK_LOCAL_P2P_SHAR_RETURNED_AGENT_1           0x02
UMASK_LOCAL_P2P_SHAR_RETURNED_AGENT_2           0x04
# Added by Thomas Gruber
UMASK_LOCAL_P2P_SHAR_RETURNED_ANY               0x07

EVENT_LOCAL_SHAR_P2P_CRD_RETURNED               0x44 PBOX
UMASK_LOCAL_SHAR_P2P_CRD_RETURNED_AGENT_0       0x01
UMASK_LOCAL_SHAR_P2P_CRD_RETURNED_AGENT_1       0x02
UMASK_LOCAL_SHAR_P2P_CRD_RETURNED_AGENT_2       0x04
UMASK_LOCAL_SHAR_P2P_CRD_RETURNED_AGENT_3       0x08
UMASK_LOCAL_SHAR_P2P_CRD_RETURNED_AGENT_4       0x10
UMASK_LOCAL_SHAR_P2P_CRD_RETURNED_AGENT_5       0x20
# Added by Thomas Gruber
UMASK_LOCAL_SHAR_P2P_CRD_RETURNED_ANY           0x2F

EVENT_LOCAL_SHAR_P2P_CRD_TAKEN_0                0x40 PBOX
UMASK_LOCAL_SHAR_P2P_CRD_TAKEN_0_M2IOSF0_NCB    0x01
UMASK_LOCAL_SHAR_P2P_CRD_TAKEN_0_M2IOSF0_NCS    0x02
UMASK_LOCAL_SHAR_P2P_CRD_TAKEN_0_M2IOSF1_NCB    0x04
UMASK_LOCAL_SHAR_P2P_CRD_TAKEN_0_M2IOSF1_NCS    0x08
UMASK_LOCAL_SHAR_P2P_CRD_TAKEN_0_M2IOSF2_NCB    0x10
UMASK_LOCAL_SHAR_P2P_CRD_TAKEN_0_M2IOSF2_NCS    0x20
UMASK_LOCAL_SHAR_P2P_CRD_TAKEN_0_M2IOSF3_NCB    0x40
UMASK_LOCAL_SHAR_P2P_CRD_TAKEN_0_M2IOSF3_NCS    0x80
# Added by Thomas Gruber
UMASK_LOCAL_SHAR_P2P_CRD_TAKEN_0_ANY_NCB        0x55
UMASK_LOCAL_SHAR_P2P_CRD_TAKEN_0_ANY_NCS        0xCC

EVENT_LOCAL_SHAR_P2P_CRD_TAKEN_1                0x41 PBOX
UMASK_LOCAL_SHAR_P2P_CRD_TAKEN_1_M2IOSF4_NCB    0x01
UMASK_LOCAL_SHAR_P2P_CRD_TAKEN_1_M2IOSF4_NCS    0x02
UMASK_LOCAL_SHAR_P2P_CRD_TAKEN_1_M2IOSF5_NCB    0x04
UMASK_LOCAL_SHAR_P2P_CRD_TAKEN_1_M2IOSF5_NCS    0x08
# Added by Thomas Gruber
UMASK_LOCAL_SHAR_P2P_CRD_TAKEN_1_ANY_NCB        0x05
UMASK_LOCAL_SHAR_P2P_CRD_TAKEN_1_ANY_NCS        0x0C

EVENT_LOCAL_SHAR_P2P_CRD_WAIT_0                 0x4A PBOX
UMASK_LOCAL_SHAR_P2P_CRD_WAIT_0_M2IOSF0_NCB     0x01
UMASK_LOCAL_SHAR_P2P_CRD_WAIT_0_M2IOSF0_NCS     0x02
UMASK_LOCAL_SHAR_P2P_CRD_WAIT_0_M2IOSF1_NCB     0x04
UMASK_LOCAL_SHAR_P2P_CRD_WAIT_0_M2IOSF1_NCS     0x08
UMASK_LOCAL_SHAR_P2P_CRD_WAIT_0_M2IOSF2_NCB     0x10
UMASK_LOCAL_SHAR_P2P_CRD_WAIT_0_M2IOSF2_NCS     0x20
UMASK_LOCAL_SHAR_P2P_CRD_WAIT_0_M2IOSF3_NCB     0x40
UMASK_LOCAL_SHAR_P2P_CRD_WAIT_0_M2IOSF3_NCS     0x80
# Added by Thomas Gruber
UMASK_LOCAL_SHAR_P2P_CRD_WAIT_0_ANY_NCB         0x55
UMASK_LOCAL_SHAR_P2P_CRD_WAIT_0_ANY_NCS         0xCC

EVENT_LOCAL_SHAR_P2P_CRD_WAIT_1                 0x4B PBOX
UMASK_LOCAL_SHAR_P2P_CRD_WAIT_1_M2IOSF4_NCB     0x01
UMASK_LOCAL_SHAR_P2P_CRD_WAIT_1_M2IOSF4_NCS     0x02
UMASK_LOCAL_SHAR_P2P_CRD_WAIT_1_M2IOSF5_NCB     0x04
UMASK_LOCAL_SHAR_P2P_CRD_WAIT_1_M2IOSF5_NCS     0x08
# Added by Thomas Gruber
UMASK_LOCAL_SHAR_P2P_CRD_WAIT_1_ANY_NCB         0x05
UMASK_LOCAL_SHAR_P2P_CRD_WAIT_1_ANY_NCS         0x0C

EVENT_P2P_CRD_OCCUPANCY                 0x14 PBOX0C0|PBOX0C1|PBOX1C0|PBOX1C1
UMASK_P2P_CRD_OCCUPANCY_LOCAL_NCB       0x01
UMASK_P2P_CRD_OCCUPANCY_LOCAL_NCS       0x02
UMASK_P2P_CRD_OCCUPANCY_REMOTE_NCB      0x04
UMASK_P2P_CRD_OCCUPANCY_REMOTE_NCS      0x08
UMASK_P2P_CRD_OCCUPANCY_ALL             0x10

EVENT_P2P_DED_RECEIVED                 0x16 PBOX
UMASK_P2P_DED_RECEIVED_LOCAL_NCB       0x01
UMASK_P2P_DED_RECEIVED_LOCAL_NCS       0x02
UMASK_P2P_DED_RECEIVED_REMOTE_NCB      0x04
UMASK_P2P_DED_RECEIVED_REMOTE_NCS      0x08
UMASK_P2P_DED_RECEIVED_ALL             0x10

EVENT_P2P_SHAR_RECEIVED                 0x15 PBOX
UMASK_P2P_SHAR_RECEIVED_LOCAL_NCB       0x01
UMASK_P2P_SHAR_RECEIVED_LOCAL_NCS       0x02
UMASK_P2P_SHAR_RECEIVED_REMOTE_NCB      0x04
UMASK_P2P_SHAR_RECEIVED_REMOTE_NCS      0x08
UMASK_P2P_SHAR_RECEIVED_ALL             0x10

EVENT_REMOTE_DED_P2P_CRD_TAKEN_0            0x48 PBOX
UMASK_REMOTE_DED_P2P_CRD_TAKEN_0_UPI0_DRS   0x01
UMASK_REMOTE_DED_P2P_CRD_TAKEN_0_UPI0_NCB   0x02
UMASK_REMOTE_DED_P2P_CRD_TAKEN_0_UPI0_NCS   0x04
UMASK_REMOTE_DED_P2P_CRD_TAKEN_0_UPI1_DRS   0x08
UMASK_REMOTE_DED_P2P_CRD_TAKEN_0_UPI1_NCB   0x10
UMASK_REMOTE_DED_P2P_CRD_TAKEN_0_UPI1_NCS   0x20
# Added by Thomas Gruber
UMASK_REMOTE_DED_P2P_CRD_TAKEN_0_ANY_DRS   0x09
UMASK_REMOTE_DED_P2P_CRD_TAKEN_0_ANY_NCB   0x12
UMASK_REMOTE_DED_P2P_CRD_TAKEN_0_ANY_NCS   0x24

EVENT_REMOTE_DED_P2P_CRD_TAKEN_1            0x49 PBOX
UMASK_REMOTE_DED_P2P_CRD_TAKEN_1_UPI2_DRS   0x01
UMASK_REMOTE_DED_P2P_CRD_TAKEN_1_UPI2_NCB   0x02
UMASK_REMOTE_DED_P2P_CRD_TAKEN_1_UPI2_NCS   0x04

EVENT_REMOTE_P2P_DED_RETURNED               0x1B PBOX
UMASK_REMOTE_P2P_DED_RETURNED_UPI0_NCB      0x01
UMASK_REMOTE_P2P_DED_RETURNED_UPI0_NCS      0x02
UMASK_REMOTE_P2P_DED_RETURNED_UPI1_NCB      0x04
UMASK_REMOTE_P2P_DED_RETURNED_UPI1_NCS      0x08
UMASK_REMOTE_P2P_DED_RETURNED_UPI2_NCB      0x10
UMASK_REMOTE_P2P_DED_RETURNED_UPI2_NCS      0x20
# Added by Thomas Gruber
UMASK_REMOTE_P2P_DED_RETURNED_ANY_NCB       0x15
UMASK_REMOTE_P2P_DED_RETURNED_ANY_NCS       0x2C

EVENT_REMOTE_P2P_SHAR_RETURNED              0x18 PBOX
UMASK_REMOTE_P2P_SHAR_RETURNED_AGENT_0      0x01
UMASK_REMOTE_P2P_SHAR_RETURNED_AGENT_1      0x02
UMASK_REMOTE_P2P_SHAR_RETURNED_AGENT_2      0x04
# Added by Thomas Gruber
UMASK_REMOTE_P2P_SHAR_RETURNED_ANY          0x07

EVENT_REMOTE_SHAR_P2P_CRD_RETURNED          0x45 PBOX
UMASK_REMOTE_SHAR_P2P_CRD_RETURNED_AGENT_0  0x01
UMASK_REMOTE_SHAR_P2P_CRD_RETURNED_AGENT_1  0x02
UMASK_REMOTE_SHAR_P2P_CRD_RETURNED_AGENT_2  0x04
# Added by Thomas Gruber
UMASK_REMOTE_SHAR_P2P_CRD_RETURNED_ANY      0x07

EVENT_REMOTE_SHAR_P2P_CRD_TAKEN_0             0x42 PBOX
UMASK_REMOTE_SHAR_P2P_CRD_TAKEN_0_UPI0_DRS    0x01
UMASK_REMOTE_SHAR_P2P_CRD_TAKEN_0_UPI0_NCB    0x02
UMASK_REMOTE_SHAR_P2P_CRD_TAKEN_0_UPI0_NCS    0x04
UMASK_REMOTE_SHAR_P2P_CRD_TAKEN_0_UPI1_DRS    0x08
UMASK_REMOTE_SHAR_P2P_CRD_TAKEN_0_UPI1_NCB    0x10
UMASK_REMOTE_SHAR_P2P_CRD_TAKEN_0_UPI1_NCS    0x20
# Added by Thomas Gruber
UMASK_REMOTE_SHAR_P2P_CRD_TAKEN_0_ANY_DRS   0x09
UMASK_REMOTE_SHAR_P2P_CRD_TAKEN_0_ANY_NCB   0x12
UMASK_REMOTE_SHAR_P2P_CRD_TAKEN_0_ANY_NCS   0x24

EVENT_REMOTE_SHAR_P2P_CRD_TAKEN_1            0x43 PBOX
UMASK_REMOTE_SHAR_P2P_CRD_TAKEN_1_UPI2_DRS   0x01
UMASK_REMOTE_SHAR_P2P_CRD_TAKEN_1_UPI2_NCB   0x02
UMASK_REMOTE_SHAR_P2P_CRD_TAKEN_1_UPI2_NCS   0x04

EVENT_REMOTE_SHAR_P2P_CRD_WAIT_0            0x4C PBOX
UMASK_REMOTE_SHAR_P2P_CRD_WAIT_0_UPI0_DRS    0x01
UMASK_REMOTE_SHAR_P2P_CRD_WAIT_0_UPI0_NCB    0x02
UMASK_REMOTE_SHAR_P2P_CRD_WAIT_0_UPI0_NCS    0x04
UMASK_REMOTE_SHAR_P2P_CRD_WAIT_0_UPI1_DRS    0x08
UMASK_REMOTE_SHAR_P2P_CRD_WAIT_0_UPI1_NCB    0x10
UMASK_REMOTE_SHAR_P2P_CRD_WAIT_0_UPI1_NCS    0x20
# Added by Thomas Gruber
UMASK_REMOTE_SHAR_P2P_CRD_WAIT_0_ANY_DRS   0x09
UMASK_REMOTE_SHAR_P2P_CRD_WAIT_0_ANY_NCB   0x12
UMASK_REMOTE_SHAR_P2P_CRD_WAIT_0_ANY_NCS   0x24

EVENT_REMOTE_SHAR_P2P_CRD_WAIT_1            0x4D PBOX
UMASK_REMOTE_SHAR_P2P_CRD_WAIT_1_UPI2_DRS   0x01
UMASK_REMOTE_SHAR_P2P_CRD_WAIT_1_UPI2_NCB   0x02
UMASK_REMOTE_SHAR_P2P_CRD_WAIT_1_UPI2_NCS   0x04

EVENT_RXC_CYCLES_NE                     0x10 PBOX
UMASK_RXC_CYCLES_NE_CHA_IDI             0x01
UMASK_RXC_CYCLES_NE_CHA_NCB             0x02
UMASK_RXC_CYCLES_NE_CHA_NCS             0x04

EVENT_RXC_INSERTS                     0x11 PBOX
UMASK_RXC_INSERTS_CHA_IDI             0x01
UMASK_RXC_INSERTS_CHA_NCB             0x02
UMASK_RXC_INSERTS_CHA_NCS             0x04

EVENT_TXC_CREDITS                       0x2D PBOX0C0|PBOX0C1|PBOX1C0|PBOX1C1
UMASK_TXC_CREDITS_PRQ                   0x01
UMASK_TXC_CREDITS_PMM                   0x02

EVENT_AD_CREDITS_EMPTY              0x22 SBOX
UMASK_AD_CREDITS_EMPTY_VNA          0x01
UMASK_AD_CREDITS_EMPTY_WB           0x02
UMASK_AD_CREDITS_EMPTY_REQ          0x04
UMASK_AD_CREDITS_EMPTY_SNP          0x08

EVENT_BL_CREDITS_EMPTY               0x23 SBOX
UMASK_BL_CREDITS_EMPTY_IIO1_NCB      0x01
UMASK_BL_CREDITS_EMPTY_IIO2_NCB      0x02
UMASK_BL_CREDITS_EMPTY_IIO3_NCB      0x04
UMASK_BL_CREDITS_EMPTY_IIO4_NCB      0x08
UMASK_BL_CREDITS_EMPTY_IIO5_NCB      0x10
UMASK_BL_CREDITS_EMPTY_UBOX_NCB      0x20
UMASK_BL_CREDITS_EMPTY_NCS           0x40
UMASK_BL_CREDITS_EMPTY_NCS_SEL       0x80
# Added by Thomas Gruber
UMASK_BL_CREDITS_EMPTY_ANY_NCB       0x3F

EVENT_MULTI_SLOT_RCVD                   0x3E SBOX
UMASK_MULTI_SLOT_RCVD_AD_SLOT0          0x01
UMASK_MULTI_SLOT_RCVD_AD_SLOT1          0x02
UMASK_MULTI_SLOT_RCVD_AD_SLOT2          0x04
UMASK_MULTI_SLOT_RCVD_BL_SLOT0          0x08
UMASK_MULTI_SLOT_RCVD_AK_SLOT0          0x10
UMASK_MULTI_SLOT_RCVD_AK_SLOT2          0x20
# Added by Thomas Gruber
UMASK_MULTI_SLOT_RCVD_AD_ANY            0x07
UMASK_MULTI_SLOT_RCVD_AK_ANY            0x30

EVENT_RXC_ARB_LOST_VN0                  0x4B SBOX
UMASK_RXC_ARB_LOST_VN0_AD_REQ           0x01
UMASK_RXC_ARB_LOST_VN0_AD_SNP           0x02
UMASK_RXC_ARB_LOST_VN0_AD_RSP           0x04
UMASK_RXC_ARB_LOST_VN0_BL_RSP           0x08
UMASK_RXC_ARB_LOST_VN0_BL_WB            0x10
UMASK_RXC_ARB_LOST_VN0_BL_NCB           0x20
UMASK_RXC_ARB_LOST_VN0_BL_NCS           0x40

EVENT_RXC_ARB_LOST_VN1                  0x4C SBOX
UMASK_RXC_ARB_LOST_VN1_AD_REQ           0x01
UMASK_RXC_ARB_LOST_VN1_AD_SNP           0x02
UMASK_RXC_ARB_LOST_VN1_AD_RSP           0x04
UMASK_RXC_ARB_LOST_VN1_BL_RSP           0x08
UMASK_RXC_ARB_LOST_VN1_BL_WB            0x10
UMASK_RXC_ARB_LOST_VN1_BL_NCB           0x20
UMASK_RXC_ARB_LOST_VN1_BL_NCS           0x40

EVENT_RXC_ARB_MISC                          0x4D SBOX
UMASK_RXC_ARB_MISC_NO_PROG_AD_VN0           0x01
UMASK_RXC_ARB_MISC_NO_PROG_AD_VN1           0x02
UMASK_RXC_ARB_MISC_NO_PROG_BL_VN0           0x04
UMASK_RXC_ARB_MISC_NO_PROG_BL_VN1           0x08
UMASK_RXC_ARB_MISC_ADBL_PARALLEL_WIN_VN0    0x10
UMASK_RXC_ARB_MISC_ADBL_PARALLEL_WIN_VN1    0x20
UMASK_RXC_ARB_MISC_VN01_PARALLEL_WIN        0x40
UMASK_RXC_ARB_MISC_ALL_PARALLEL_WIN         0x80

EVENT_RXC_ARB_NOCRD_VN0                 0x47 SBOX
UMASK_RXC_ARB_NOCRD_VN0_AD_REQ          0x01
UMASK_RXC_ARB_NOCRD_VN0_AD_SNP          0x02
UMASK_RXC_ARB_NOCRD_VN0_AD_RSP          0x04
UMASK_RXC_ARB_NOCRD_VN0_BL_RSP          0x08
UMASK_RXC_ARB_NOCRD_VN0_BL_WB           0x10
UMASK_RXC_ARB_NOCRD_VN0_BL_NCB          0x20
UMASK_RXC_ARB_NOCRD_VN0_BL_NCS          0x40

EVENT_RXC_ARB_NOCRD_VN1                 0x48 SBOX
UMASK_RXC_ARB_NOCRD_VN1_AD_REQ          0x01
UMASK_RXC_ARB_NOCRD_VN1_AD_SNP          0x02
UMASK_RXC_ARB_NOCRD_VN1_AD_RSP          0x04
UMASK_RXC_ARB_NOCRD_VN1_BL_RSP          0x08
UMASK_RXC_ARB_NOCRD_VN1_BL_WB           0x10
UMASK_RXC_ARB_NOCRD_VN1_BL_NCB          0x20
UMASK_RXC_ARB_NOCRD_VN1_BL_NCS          0x40

EVENT_RXC_ARB_NOREQ_VN0                 0x49 SBOX
UMASK_RXC_ARB_NOREQ_VN0_AD_REQ          0x01
UMASK_RXC_ARB_NOREQ_VN0_AD_SNP          0x02
UMASK_RXC_ARB_NOREQ_VN0_AD_RSP          0x04
UMASK_RXC_ARB_NOREQ_VN0_BL_RSP          0x08
UMASK_RXC_ARB_NOREQ_VN0_BL_WB           0x10
UMASK_RXC_ARB_NOREQ_VN0_BL_NCB          0x20
UMASK_RXC_ARB_NOREQ_VN0_BL_NCS          0x40

EVENT_RXC_ARB_NOREQ_VN1                 0x4A SBOX
UMASK_RXC_ARB_NOREQ_VN1_AD_REQ          0x01
UMASK_RXC_ARB_NOREQ_VN1_AD_SNP          0x02
UMASK_RXC_ARB_NOREQ_VN1_AD_RSP          0x04
UMASK_RXC_ARB_NOREQ_VN1_BL_RSP          0x08
UMASK_RXC_ARB_NOREQ_VN1_BL_WB           0x10
UMASK_RXC_ARB_NOREQ_VN1_BL_NCB          0x20
UMASK_RXC_ARB_NOREQ_VN1_BL_NCS          0x40

EVENT_RXC_BYPASSED                      0x40 SBOX0C0|SBOX0C1|SBOX0C2|SBOX1C0|SBOX1C1|SBOX1C2|SBOX2C0|SBOX2C1|SBOX2C2
UMASK_RXC_BYPASSED_AD_S0_IDLE           0x01
UMASK_RXC_BYPASSED_AD_S0_BL_ARB         0x02
UMASK_RXC_BYPASSED_AD_S1_BL_SLOT        0x04
UMASK_RXC_BYPASSED_AD_S2_BL_SLOT        0x08

EVENT_RXC_CRD_MISC                      0x5F SBOX
UMASK_RXC_CRD_MISC_ANY_BGF_FIFO         0x01
UMASK_RXC_CRD_MISC_ANY_BGF_PATH         0x02
UMASK_RXC_CRD_MISC_VN0_NO_D2K_FOR_ARB   0x04
UMASK_RXC_CRD_MISC_VN1_NO_D2K_FOR_ARB   0x08
UMASK_RXC_CRD_MISC_LT1_FOR_D2K          0x10
UMASK_RXC_CRD_MISC_LT2_FOR_D2K          0x20

EVENT_RXC_CRD_OCC                       0x60 SBOX
UMASK_RXC_CRD_OCC_VNA_IN_USE            0x01
UMASK_RXC_CRD_OCC_FLITS_IN_FIFO         0x02
UMASK_RXC_CRD_OCC_FLITS_IN_PATH         0x04
UMASK_RXC_CRD_OCC_TxQ_CRD               0x08
UMASK_RXC_CRD_OCC_D2K_CRD               0x10
UMASK_RXC_CRD_OCC_P1P_TOTAL             0x20
UMASK_RXC_CRD_OCC_P1P_FIFO              0x40
UMASK_RXC_CRD_OCC_CONSUMED              0x80

EVENT_RXC_CYCLES_NE_VN0                 0x43 SBOX
UMASK_RXC_CYCLES_NE_VN0_AD_REQ          0x01
UMASK_RXC_CYCLES_NE_VN0_AD_SNP          0x02
UMASK_RXC_CYCLES_NE_VN0_AD_RSP          0x04
UMASK_RXC_CYCLES_NE_VN0_BL_RSP          0x08
UMASK_RXC_CYCLES_NE_VN0_BL_WB           0x10
UMASK_RXC_CYCLES_NE_VN0_BL_NCB          0x20
UMASK_RXC_CYCLES_NE_VN0_BL_NCS          0x40

EVENT_RXC_CYCLES_NE_VN1                 0x44 SBOX
UMASK_RXC_CYCLES_NE_VN1_AD_REQ          0x01
UMASK_RXC_CYCLES_NE_VN1_AD_SNP          0x02
UMASK_RXC_CYCLES_NE_VN1_AD_RSP          0x04
UMASK_RXC_CYCLES_NE_VN1_BL_RSP          0x08
UMASK_RXC_CYCLES_NE_VN1_BL_WB           0x10
UMASK_RXC_CYCLES_NE_VN1_BL_NCB          0x20
UMASK_RXC_CYCLES_NE_VN1_BL_NCS          0x40

EVENT_RXC_DATA_FLITS_NOT_SENT                   0x55 SBOX
UMASK_RXC_DATA_FLITS_NOT_SENT_ALL               0x01
UMASK_RXC_DATA_FLITS_NOT_SENT_TSV_HI            0x02
UMASK_RXC_DATA_FLITS_NOT_SENT_VALID_FOR_FLIT    0x04
UMASK_RXC_DATA_FLITS_NOT_SENT_NO_BGF            0x08
UMASK_RXC_DATA_FLITS_NOT_SENT_NO_TXQ            0x10

EVENT_RXC_FLITS_GEN_BL                  0x57 SBOX
UMASK_RXC_FLITS_GEN_BL_P0_WAIT          0x01
UMASK_RXC_FLITS_GEN_BL_P1_WAIT          0x02
UMASK_RXC_FLITS_GEN_BL_P1P_TO_LIMBO     0x04
UMASK_RXC_FLITS_GEN_BL_P1P_BUSY         0x08
UMASK_RXC_FLITS_GEN_BL_P1P_AT_LIMIT     0x10
UMASK_RXC_FLITS_GEN_BL_P1P_HOLD_P0      0x20
UMASK_RXC_FLITS_GEN_BL_P1P_FIFO_FULL    0x40

EVENT_RXC_FLITS_MISC                    0x58 SBOX
UMASK_RXC_FLITS_MISC_S2REQ_RECEIVED     0x01
UMASK_RXC_FLITS_MISC_S2REQ_WITHDRAWN    0x02
UMASK_RXC_FLITS_MISC_S2REQ_IN_HOLDOFF   0x04
UMASK_RXC_FLITS_MISC_S2REQ_IN_SERVICE   0x08

EVENT_RXC_FLITS_SLOT_BL                         0x56 SBOX
UMASK_RXC_FLITS_SLOT_BL_ALL                     0x01
UMASK_RXC_FLITS_SLOT_BL_NEED_DATA               0x02
UMASK_RXC_FLITS_SLOT_BL_P0_WAIT                 0x04
UMASK_RXC_FLITS_SLOT_BL_P1_WAIT                 0x08
UMASK_RXC_FLITS_SLOT_BL_P1_NOT_REQ              0x10
UMASK_RXC_FLITS_SLOT_BL_P1_NOT_REQ_BUT_BUBBLE   0x20
UMASK_RXC_FLITS_SLOT_BL_P1_NOT_REQ_NOT_AVAIL    0x40

EVENT_RXC_FLIT_GEN_HDR1                     0x51 SBOX
UMASK_RXC_FLIT_GEN_HDR1_ACCUM               0x01
UMASK_RXC_FLIT_GEN_HDR1_ACCUM_READ          0x02
UMASK_RXC_FLIT_GEN_HDR1_ACCUM_WASTED        0x04
UMASK_RXC_FLIT_GEN_HDR1_AHEAD_BLOCKED       0x08
UMASK_RXC_FLIT_GEN_HDR1_AHEAD_MSG1_DURING   0x10
UMASK_RXC_FLIT_GEN_HDR1_AHEAD_MSG2_AFTER    0x20
UMASK_RXC_FLIT_GEN_HDR1_AHEAD_MSG2_SENT     0x40
UMASK_RXC_FLIT_GEN_HDR1_AHEAD_MSG1_AFTER    0x80

EVENT_RXC_FLIT_GEN_HDR2                     0x52 SBOX
UMASK_RXC_FLIT_GEN_HDR2_RMSTALL             0x01
UMASK_RXC_FLIT_GEN_HDR2_RMSTALL_NOMSG       0x02
UMASK_RXC_FLIT_GEN_HDR2_PAR                 0x04
UMASK_RXC_FLIT_GEN_HDR2_PAR_MSG             0x08
UMASK_RXC_FLIT_GEN_HDR2_PAR_FLIT            0x10

EVENT_RXC_HDR_FLITS_SENT                    0x54 SBOX
UMASK_RXC_HDR_FLITS_SENT_1_MSG              0x01
UMASK_RXC_HDR_FLITS_SENT_2_MSGS             0x02
UMASK_RXC_HDR_FLITS_SENT_3_MSGS             0x04
UMASK_RXC_HDR_FLITS_SENT_1_MSG_VNX          0x08
UMASK_RXC_HDR_FLITS_SENT_SLOTS_1            0x10
UMASK_RXC_HDR_FLITS_SENT_SLOTS_2            0x20
UMASK_RXC_HDR_FLITS_SENT_SLOTS_3            0x40

EVENT_RXC_HDR_FLIT_NOT_SENT                 0x53 SBOX
UMASK_RXC_HDR_FLIT_NOT_SENT_ALL             0x01
UMASK_RXC_HDR_FLIT_NOT_SENT_TSV_HI          0x02
UMASK_RXC_HDR_FLIT_NOT_SENT_VALID_FOR_FLIT  0x04
UMASK_RXC_HDR_FLIT_NOT_SENT_NO_BGF_CRD      0x08
UMASK_RXC_HDR_FLIT_NOT_SENT_NO_TXQ_CRD      0x10
UMASK_RXC_HDR_FLIT_NOT_SENT_NO_BGF_NO_MSG   0x20
UMASK_RXC_HDR_FLIT_NOT_SENT_NO_TXQ_NO_MSG   0x40

EVENT_RXC_HELD                              0x50 SBOX
UMASK_RXC_HELD_VN0                          0x01
UMASK_RXC_HELD_VN1                          0x02
UMASK_RXC_HELD_PARALLEL_ATTEMPT             0x04
UMASK_RXC_HELD_PARALLEL_SUCCESS             0x08
UMASK_RXC_HELD_CANT_SLOT_AD                 0x10
UMASK_RXC_HELD_CANT_SLOT_BL                 0x20

EVENT_RXC_INSERTS_VN0                       0x41 SBOX
UMASK_RXC_INSERTS_VN0_AD_REQ                0x01
UMASK_RXC_INSERTS_VN0_AD_SNP                0x02
UMASK_RXC_INSERTS_VN0_AD_RSP                0x04
UMASK_RXC_INSERTS_VN0_BL_RSP                0x08
UMASK_RXC_INSERTS_VN0_BL_WB                 0x10
UMASK_RXC_INSERTS_VN0_BL_NCB                0x20
UMASK_RXC_INSERTS_VN0_BL_NCS                0x40

EVENT_RXC_INSERTS_VN1                       0x42 SBOX
UMASK_RXC_INSERTS_VN1_AD_REQ                0x01
UMASK_RXC_INSERTS_VN1_AD_SNP                0x02
UMASK_RXC_INSERTS_VN1_AD_RSP                0x04
UMASK_RXC_INSERTS_VN1_BL_RSP                0x08
UMASK_RXC_INSERTS_VN1_BL_WB                 0x10
UMASK_RXC_INSERTS_VN1_BL_NCB                0x20
UMASK_RXC_INSERTS_VN1_BL_NCS                0x40

EVENT_RXC_OCCUPANCY_VN0                       0x45 SBOX
UMASK_RXC_OCCUPANCY_VN0_AD_REQ                0x01
UMASK_RXC_OCCUPANCY_VN0_AD_SNP                0x02
UMASK_RXC_OCCUPANCY_VN0_AD_RSP                0x04
UMASK_RXC_OCCUPANCY_VN0_BL_RSP                0x08
UMASK_RXC_OCCUPANCY_VN0_BL_WB                 0x10
UMASK_RXC_OCCUPANCY_VN0_BL_NCB                0x20
UMASK_RXC_OCCUPANCY_VN0_BL_NCS                0x40

EVENT_RXC_OCCUPANCY_VN1                       0x46 SBOX
UMASK_RXC_OCCUPANCY_VN1_AD_REQ                0x01
UMASK_RXC_OCCUPANCY_VN1_AD_SNP                0x02
UMASK_RXC_OCCUPANCY_VN1_AD_RSP                0x04
UMASK_RXC_OCCUPANCY_VN1_BL_RSP                0x08
UMASK_RXC_OCCUPANCY_VN1_BL_WB                 0x10
UMASK_RXC_OCCUPANCY_VN1_BL_NCB                0x20
UMASK_RXC_OCCUPANCY_VN1_BL_NCS                0x40

EVENT_RXC_PACKING_MISS_VN0                       0x4E SBOX
UMASK_RXC_PACKING_MISS_VN0_AD_REQ                0x01
UMASK_RXC_PACKING_MISS_VN0_AD_SNP                0x02
UMASK_RXC_PACKING_MISS_VN0_AD_RSP                0x04
UMASK_RXC_PACKING_MISS_VN0_BL_RSP                0x08
UMASK_RXC_PACKING_MISS_VN0_BL_WB                 0x10
UMASK_RXC_PACKING_MISS_VN0_BL_NCB                0x20
UMASK_RXC_PACKING_MISS_VN0_BL_NCS                0x40

EVENT_RXC_PACKING_MISS_VN1                       0x4F SBOX
UMASK_RXC_PACKING_MISS_VN1_AD_REQ                0x01
UMASK_RXC_PACKING_MISS_VN1_AD_SNP                0x02
UMASK_RXC_PACKING_MISS_VN1_AD_RSP                0x04
UMASK_RXC_PACKING_MISS_VN1_BL_RSP                0x08
UMASK_RXC_PACKING_MISS_VN1_BL_WB                 0x10
UMASK_RXC_PACKING_MISS_VN1_BL_NCB                0x20
UMASK_RXC_PACKING_MISS_VN1_BL_NCS                0x40

EVENT_RXC_VNA_CRD                       0x5A SBOX
UMASK_RXC_VNA_CRD_CORRECTED             0x01
UMASK_RXC_VNA_CRD_LT1                   0x02
UMASK_RXC_VNA_CRD_LT4                   0x04
UMASK_RXC_VNA_CRD_LT5                   0x08
UMASK_RXC_VNA_CRD_LT10                  0x10
UMASK_RXC_VNA_CRD_ANY_IN_USE            0x20

EVENT_RXC_VNA_CRD_MISC                      0x59 SBOX
UMASK_RXC_VNA_CRD_MISC_REQ_VN01_ALLOC_LT10  0x01
UMASK_RXC_VNA_CRD_MISC_REQ_ADBL_ALLOC_L5    0x02
UMASK_RXC_VNA_CRD_MISC_VN0_ONLY             0x04
UMASK_RXC_VNA_CRD_MISC_VN1_ONLY             0x08
UMASK_RXC_VNA_CRD_MISC_VN0_JUST_AD          0x10
UMASK_RXC_VNA_CRD_MISC_VN0_JUST_BL          0x20
UMASK_RXC_VNA_CRD_MISC_VN1_JUST_AD          0x40
UMASK_RXC_VNA_CRD_MISC_VN1_JUST_BL          0x80

EVENT_TXC_AD_ARB_FAIL                   0x30 SBOX
UMASK_TXC_AD_ARB_FAIL_VN0_REQ           0x01
UMASK_TXC_AD_ARB_FAIL_VN0_SNP           0x02
UMASK_TXC_AD_ARB_FAIL_VN0_RSP           0x04
UMASK_TXC_AD_ARB_FAIL_VN0_WB            0x08
UMASK_TXC_AD_ARB_FAIL_VN1_REQ           0x10
UMASK_TXC_AD_ARB_FAIL_VN1_SNP           0x20
UMASK_TXC_AD_ARB_FAIL_VN1_RSP           0x40
UMASK_TXC_AD_ARB_FAIL_VN1_WB            0x80

EVENT_TXC_AD_FLQ_BYPASS                 0x2C SBOX
UMASK_TXC_AD_FLQ_BYPASS_AD_SLOT0        0x01
UMASK_TXC_AD_FLQ_BYPASS_AD_SLOT1        0x02
UMASK_TXC_AD_FLQ_BYPASS_AD_SLOT2        0x04
UMASK_TXC_AD_FLQ_BYPASS_BL_EARLY_RSP    0x08

EVENT_TXC_AD_FLQ_CYCLES_NE              0x27 SBOX
UMASK_TXC_AD_FLQ_CYCLES_NE_VN0_REQ      0x01
UMASK_TXC_AD_FLQ_CYCLES_NE_VN0_SNP      0x02
UMASK_TXC_AD_FLQ_CYCLES_NE_VN0_RSP      0x04
UMASK_TXC_AD_FLQ_CYCLES_NE_VN0_WB       0x08
UMASK_TXC_AD_FLQ_CYCLES_NE_VN1_REQ      0x10
UMASK_TXC_AD_FLQ_CYCLES_NE_VN1_SNP      0x20
UMASK_TXC_AD_FLQ_CYCLES_NE_VN1_RSP      0x40
UMASK_TXC_AD_FLQ_CYCLES_NE_VN1_WB       0x80

EVENT_TXC_AD_FLQ_INSERTS                0x2D SBOX
UMASK_TXC_AD_FLQ_INSERTS_VN0_REQ        0x01
UMASK_TXC_AD_FLQ_INSERTS_VN0_SNP        0x02
UMASK_TXC_AD_FLQ_INSERTS_VN0_RSP        0x04
UMASK_TXC_AD_FLQ_INSERTS_VN0_WB         0x08
UMASK_TXC_AD_FLQ_INSERTS_VN1_REQ        0x10
UMASK_TXC_AD_FLQ_INSERTS_VN1_SNP        0x20
UMASK_TXC_AD_FLQ_INSERTS_VN1_RSP        0x40
UMASK_TXC_AD_FLQ_INSERTS_VN1_WB         0x80

EVENT_TXC_AD_FLQ_OCCUPANCY              0x1C SBOX
UMASK_TXC_AD_FLQ_OCCUPANCY_VN0_REQ      0x01
UMASK_TXC_AD_FLQ_OCCUPANCY_VN0_SNP      0x02
UMASK_TXC_AD_FLQ_OCCUPANCY_VN0_RSP      0x04
UMASK_TXC_AD_FLQ_OCCUPANCY_VN0_WB       0x08
UMASK_TXC_AD_FLQ_OCCUPANCY_VN1_REQ      0x10
UMASK_TXC_AD_FLQ_OCCUPANCY_VN1_SNP      0x20
UMASK_TXC_AD_FLQ_OCCUPANCY_VN1_RSP      0x40
UMASK_TXC_AD_FLQ_OCCUPANCY_VN1_WB       0x80

EVENT_TXC_BL_ARB_FAIL               0x35 SBOX
UMASK_TXC_BL_ARB_FAIL_VN0_RSP       0x01
UMASK_TXC_BL_ARB_FAIL_VN0_WB        0x02
UMASK_TXC_BL_ARB_FAIL_VN0_NCB       0x04
UMASK_TXC_BL_ARB_FAIL_VN0_NCS       0x08
UMASK_TXC_BL_ARB_FAIL_VN1_RSP       0x10
UMASK_TXC_BL_ARB_FAIL_VN1_WB        0x20
UMASK_TXC_BL_ARB_FAIL_VN1_NCB       0x40
UMASK_TXC_BL_ARB_FAIL_VN1_NCS       0x80

EVENT_TXC_BL_FLQ_CYCLES_NE          0x28 SBOX
UMASK_TXC_BL_FLQ_CYCLES_NE_VN0_REQ  0x01
UMASK_TXC_BL_FLQ_CYCLES_NE_VN0_SNP  0x02
UMASK_TXC_BL_FLQ_CYCLES_NE_VN0_RSP  0x04
UMASK_TXC_BL_FLQ_CYCLES_NE_VN0_WB   0x08
UMASK_TXC_BL_FLQ_CYCLES_NE_VN1_REQ  0x10
UMASK_TXC_BL_FLQ_CYCLES_NE_VN1_SNP  0x20
UMASK_TXC_BL_FLQ_CYCLES_NE_VN1_RSP  0x40
UMASK_TXC_BL_FLQ_CYCLES_NE_VN1_WB   0x80

EVENT_TXC_BL_FLQ_INSERTS            0x2E SBOX
UMASK_TXC_BL_FLQ_INSERTS_VN0_NCB    0x01
UMASK_TXC_BL_FLQ_INSERTS_VN0_NCS    0x02
UMASK_TXC_BL_FLQ_INSERTS_VN0_WB     0x04
UMASK_TXC_BL_FLQ_INSERTS_VN0_RSP    0x08
UMASK_TXC_BL_FLQ_INSERTS_VN1_NCB    0x10
UMASK_TXC_BL_FLQ_INSERTS_VN1_NCS    0x20
UMASK_TXC_BL_FLQ_INSERTS_VN1_WB     0x40
UMASK_TXC_BL_FLQ_INSERTS_VN1_RSP    0x80

EVENT_TXC_BL_FLQ_OCCUPANCY          0x1D SBOX0C0|SBOX1C0|SBOX2C0
UMASK_TXC_BL_FLQ_OCCUPANCY_VN0_RSP  0x01
UMASK_TXC_BL_FLQ_OCCUPANCY_VN0_WB   0x02
UMASK_TXC_BL_FLQ_OCCUPANCY_VN0_NCB  0x04
UMASK_TXC_BL_FLQ_OCCUPANCY_VN0_NCS  0x08
UMASK_TXC_BL_FLQ_OCCUPANCY_VN1_RSP  0x10
UMASK_TXC_BL_FLQ_OCCUPANCY_VN1_WB   0x20
UMASK_TXC_BL_FLQ_OCCUPANCY_VN1_NCB  0x40
UMASK_TXC_BL_FLQ_OCCUPANCY_VN1_NCS  0x80

EVENT_TXC_BL_WB_FLQ_OCCUPANCY               0x1F SBOX0C0|SBOX1C0|SBOX2C0
UMASK_TXC_BL_WB_FLQ_OCCUPANCY_VN0_LOCAL     0x01
UMASK_TXC_BL_WB_FLQ_OCCUPANCY_VN0_THROUGH   0x02
UMASK_TXC_BL_WB_FLQ_OCCUPANCY_VN0_WRPULL    0x04
UMASK_TXC_BL_WB_FLQ_OCCUPANCY_VN1_LOCAL     0x10
UMASK_TXC_BL_WB_FLQ_OCCUPANCY_VN1_THROUGH   0x20
UMASK_TXC_BL_WB_FLQ_OCCUPANCY_VN1_WRPULL    0x40

EVENT_TXC_AK_FLQ_INSERTS        0x2F SBOX
UMASK_TXC_AK_FLQ_INSERTS        0x00

EVENT_TXC_AK_FLQ_OCCUPANCY      0x1E SBOX0C0|SBOX1C0|SBOX2C0
UMASK_TXC_AK_FLQ_OCCUPANCY      0x00

EVENT_UPI_PEER_AD_CREDITS_EMPTY         0x20 SBOX
UMASK_UPI_PEER_AD_CREDITS_EMPTY_VNA     0x01
UMASK_UPI_PEER_AD_CREDITS_EMPTY_VN0_REQ 0x02
UMASK_UPI_PEER_AD_CREDITS_EMPTY_VN0_SNP 0x04
UMASK_UPI_PEER_AD_CREDITS_EMPTY_VN0_RSP 0x08
UMASK_UPI_PEER_AD_CREDITS_EMPTY_VN1_REQ 0x10
UMASK_UPI_PEER_AD_CREDITS_EMPTY_VN1_SNP 0x20
UMASK_UPI_PEER_AD_CREDITS_EMPTY_VN1_RSP 0x40

EVENT_UPI_PEER_BL_CREDITS_EMPTY             0x21 SBOX
UMASK_UPI_PEER_BL_CREDITS_EMPTY_VNA         0x01
UMASK_UPI_PEER_BL_CREDITS_EMPTY_VN0_RSP     0x02
UMASK_UPI_PEER_BL_CREDITS_EMPTY_VN0_NCS_NCB 0x04
UMASK_UPI_PEER_BL_CREDITS_EMPTY_VN0_WB      0x08
UMASK_UPI_PEER_BL_CREDITS_EMPTY_VN1_RSP     0x10
UMASK_UPI_PEER_BL_CREDITS_EMPTY_VN1_NCS_NCB 0x20
UMASK_UPI_PEER_BL_CREDITS_EMPTY_VN1_WB      0x40

EVENT_VN0_CREDITS_USED                  0x5B SBOX
UMASK_VN0_CREDITS_USED_REQ              0x01
UMASK_VN0_CREDITS_USED_SNP              0x02
UMASK_VN0_CREDITS_USED_RSP              0x04
UMASK_VN0_CREDITS_USED_WB               0x08
UMASK_VN0_CREDITS_USED_NCB              0x10
UMASK_VN0_CREDITS_USED_NCS              0x20

EVENT_VN0_NO_CREDITS                    0x5D SBOX
UMASK_VN0_NO_CREDITS_REQ                0x01
UMASK_VN0_NO_CREDITS_SNP                0x02
UMASK_VN0_NO_CREDITS_RSP                0x04
UMASK_VN0_NO_CREDITS_WB                 0x08
UMASK_VN0_NO_CREDITS_NCB                0x10
UMASK_VN0_NO_CREDITS_NCS                0x20

EVENT_VN1_CREDITS_USED                  0x5C SBOX
UMASK_VN1_CREDITS_USED_REQ              0x01
UMASK_VN1_CREDITS_USED_SNP              0x02
UMASK_VN1_CREDITS_USED_RSP              0x04
UMASK_VN1_CREDITS_USED_WB               0x08
UMASK_VN1_CREDITS_USED_NCB              0x10
UMASK_VN1_CREDITS_USED_NCS              0x20

EVENT_VN1_NO_CREDITS                    0x5E SBOX
UMASK_VN1_NO_CREDITS_REQ                0x01
UMASK_VN1_NO_CREDITS_SNP                0x02
UMASK_VN1_NO_CREDITS_RSP                0x04
UMASK_VN1_NO_CREDITS_WB                 0x08
UMASK_VN1_NO_CREDITS_NCB                0x10
UMASK_VN1_NO_CREDITS_NCS                0x20

EVENT_WB_OCC_COMPARE                                    0x7E SBOX
UMASK_WB_OCC_COMPARE_RT_GT_LOCALDEST_VN0                0x01
UMASK_WB_OCC_COMPARE_RT_EQ_LOCALDEST_VN0                0x02
UMASK_WB_OCC_COMPARE_RT_LT_LOCALDEST_VN0                0x04
UMASK_WB_OCC_COMPARE_RT_GT_LOCALDEST_VN1                0x10
UMASK_WB_OCC_COMPARE_RT_EQ_LOCALDEST_VN1                0x20
UMASK_WB_OCC_COMPARE_RT_LT_LOCALDEST_VN1                0x40
UMASK_WB_OCC_COMPARE_BOTHNONZERO_RT_GT_LOCALDEST_VN0    0x81
UMASK_WB_OCC_COMPARE_BOTHNONZERO_RT_EQ_LOCALDEST_VN0    0x82
UMASK_WB_OCC_COMPARE_BOTHNONZERO_RT_LT_LOCALDEST_VN0    0x84
UMASK_WB_OCC_COMPARE_BOTHNONZERO_RT_GT_LOCALDEST_VN1    0x90
UMASK_WB_OCC_COMPARE_BOTHNONZERO_RT_EQ_LOCALDEST_VN1    0xA0
UMASK_WB_OCC_COMPARE_BOTHNONZERO_RT_LT_LOCALDEST_VN1    0xC0

EVENT_WB_PENDING                            0x7D SBOX
UMASK_WB_PENDING_LOCALDEST_VN0              0x01
UMASK_WB_PENDING_ROUTETHRU_VN0              0x02
UMASK_WB_PENDING_LOCAL_AND_RT_VN0           0x04
UMASK_WB_PENDING_WAITING4PULL_VN0           0x08
UMASK_WB_PENDING_LOCALDEST_VN1              0x10
UMASK_WB_PENDING_ROUTETHRU_VN1              0x20
UMASK_WB_PENDING_LOCAL_AND_RT_VN1           0x40
UMASK_WB_PENDING_WAITING4PULL_VN1           0x80

EVENT_XPT_PFTCH                             0x61 SBOX
UMASK_XPT_PFTCH_ARRIVED                     0x01
UMASK_XPT_PFTCH_BYPASS                      0x02
UMASK_XPT_PFTCH_ARB                         0x04
UMASK_XPT_PFTCH_LOST_ARB                    0x08
UMASK_XPT_PFTCH_FLITTED                     0x10
UMASK_XPT_PFTCH_LOST_OLD                    0x20
UMASK_XPT_PFTCH_LOST_QFULL                  0x20

EVENT_D2C_SENT                  0x2B SBOX
UMASK_D2C_SENT                  0x00

EVENT_D2U_SENT                  0x2A SBOX
UMASK_D2U_SENT                  0x00

EVENT_UPI_PREFETCH_SPAWN        0x29 SBOX
UMASK_UPI_PREFETCH_SPAWN        0x00

EVENT_UNCORE_CLOCKTICKS                 0x00 UBOXFIX
UMASK_UNCORE_CLOCKTICKS                 0x00

EVENT_EVENT_MSG                         0x42 UBOX
UMASK_EVENT_MSG_VLW_RCVD                0x01
UMASK_EVENT_MSG_MSI_RCVD                0x02
UMASK_EVENT_MSG_IPI_RCVD                0x04
UMASK_EVENT_MSG_DOORBELL_RCVD           0x08
UMASK_EVENT_MSG_INT_PRIO                0x10

EVENT_PHOLD_CYCLES                      0x45 UBOX
UMASK_PHOLD_CYCLES_ASSERT_TO_ACK        0x01

EVENT_RACU_DRNG                         0x4C UBOX
UMASK_RACU_DRNG_RDRAND                  0x01
UMASK_RACU_DRNG_RDSEED                  0x02
UMASK_RACU_DRNG_PFTCH_BUF_EMPTY         0x04

EVENT_M2U_MISC1                             0x4D UBOX
UMASK_M2U_MISC1_RXC_CYCLES_NE_CBO_NCB       0x01
UMASK_M2U_MISC1_RXC_CYCLES_NE_CBO_NCS       0x02
UMASK_M2U_MISC1_RXC_CYCLES_NE_UPI_NCB       0x04
UMASK_M2U_MISC1_RXC_CYCLES_NE_UPI_NCS       0x08
UMASK_M2U_MISC1_TXC_CYCLES_CRD_OVF_CBO_NCB  0x10
UMASK_M2U_MISC1_TXC_CYCLES_CRD_OVF_CBO_NCS  0x20
UMASK_M2U_MISC1_TXC_CYCLES_CRD_OVF_UPI_NCB  0x40
UMASK_M2U_MISC1_TXC_CYCLES_CRD_OVF_UPI_NCS  0x80

EVENT_M2U_MISC2                             0x4E UBOX
UMASK_M2U_MISC2_RXC_CYCLES_FULL_BL          0x01
UMASK_M2U_MISC2_RXC_CYCLES_EMPTY_BL         0x02
UMASK_M2U_MISC2_TXC_CYCLES_CRD_OVF_VN0_NCB  0x04
UMASK_M2U_MISC2_TXC_CYCLES_CRD_OVF_VN0_NCS  0x08
UMASK_M2U_MISC2_TXC_CYCLES_EMPTY_BL         0x10
UMASK_M2U_MISC2_TXC_CYCLES_EMPTY_AK         0x20
UMASK_M2U_MISC2_TXC_CYCLES_EMPTY_AKC        0x40
UMASK_M2U_MISC2_TXC_CYCLES_FULL_BL          0x80

EVENT_M2U_MISC3                             0x4F UBOX
UMASK_M2U_MISC3_TXC_CYCLES_FULL_AK          0x01
UMASK_M2U_MISC3_TXC_CYCLES_FULL_AKC         0x02

EVENT_LOCK_CYCLES                       0x44 UBOX
UMASK_LOCK_CYCLES                       0x00

EVENT_RACU_REQUESTS                     0x46 UBOX
UMASK_RACU_REQUESTS                     0x00

EVENT_UPI_CLOCKTICKS                    0x01 QBOX
UMASK_UPI_CLOCKTICKS                    0x00

EVENT_DIRECT_ATTEMPTS                   0x12 QBOX
UMASK_DIRECT_ATTEMPTS_D2C               0x01
UMASK_DIRECT_ATTEMPTS_D2K               0x02

EVENT_FLOWQ_NO_VNA_CRD                  0x18 QBOX
UMASK_FLOWQ_NO_VNA_CRD_AD_VNA_EQ0       0x01
UMASK_FLOWQ_NO_VNA_CRD_AD_VNA_EQ1       0x02
UMASK_FLOWQ_NO_VNA_CRD_AD_VNA_EQ2       0x04
UMASK_FLOWQ_NO_VNA_CRD_BL_VNA_EQ0       0x08
UMASK_FLOWQ_NO_VNA_CRD_AK_VNA_EQ0       0x10
UMASK_FLOWQ_NO_VNA_CRD_AK_VNA_EQ1       0x20
UMASK_FLOWQ_NO_VNA_CRD_AK_VNA_EQ2       0x40
UMASK_FLOWQ_NO_VNA_CRD_AK_VNA_EQ3       0x80

EVENT_M3_BYP_BLOCKED                    0x14 QBOX
UMASK_M3_BYP_BLOCKED_FLOWQ_AD_VNA_LE2   0x01
UMASK_M3_BYP_BLOCKED_FLOWQ_BL_VNA_EQ0   0x02
UMASK_M3_BYP_BLOCKED_FLOWQ_AK_VNA_LE3   0x04
UMASK_M3_BYP_BLOCKED_BGF_CRD            0x08
UMASK_M3_BYP_BLOCKED_GV_BLOCK           0x10

EVENT_M3_RXQ_BLOCKED                            0x15 QBOX
UMASK_M3_RXQ_BLOCKED_FLOWQ_AD_VNA_LE2           0x01
UMASK_M3_RXQ_BLOCKED_FLOWQ_AD_VNA_BTW_2_THRESH  0x02
UMASK_M3_RXQ_BLOCKED_FLOWQ_BL_VNA_EQ0           0x04
UMASK_M3_RXQ_BLOCKED_FLOWQ_BL_VNA_BTW_0_THRESH  0x08
UMASK_M3_RXQ_BLOCKED_FLOWQ_AK_VNA_LE3           0x10
UMASK_M3_RXQ_BLOCKED_BGF_CRD                    0x20
UMASK_M3_RXQ_BLOCKED_GV_BLOCK                   0x40

EVENT_M3_CRD_RETURN_BLOCKED             0x16 QBOX
UMASK_M3_CRD_RETURN_BLOCKED             0x00

EVENT_REQ_SLOT2_FROM_M3                 0x46 QBOX
UMASK_REQ_SLOT2_FROM_M3_VNA             0x01
UMASK_REQ_SLOT2_FROM_M3_VN0             0x02
UMASK_REQ_SLOT2_FROM_M3_VN1             0x04
UMASK_REQ_SLOT2_FROM_M3_ACK             0x08

EVENT_RXL_BASIC_HDR_MATCH                   0x05 QBOX
OPTIONS_RXL_BASIC_HDR_MATCH_REQ             EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
UMASK_RXL_BASIC_HDR_MATCH_REQ               0x08
OPTIONS_RXL_BASIC_HDR_MATCH_REQ_OPC         EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_REQ_OPC EVENT_OPTION_OPCODE=0x0
UMASK_RXL_BASIC_HDR_MATCH_REQ_OPC           0x08 0x01 0x00
OPTIONS_RXL_BASIC_HDR_MATCH_SNP             EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
UMASK_RXL_BASIC_HDR_MATCH_SNP               0x09
OPTIONS_RXL_BASIC_HDR_MATCH_SNP_OPC         EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_SNP_OPC EVENT_OPTION_OPCODE=0x0
UMASK_RXL_BASIC_HDR_MATCH_SNP_OPC           0x09 0x01 0x00
OPTIONS_RXL_BASIC_HDR_MATCH_RSP_NODATA      EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
UMASK_RXL_BASIC_HDR_MATCH_RSP_NODATA        0x0A
OPTIONS_RXL_BASIC_HDR_MATCH_RSP_NODATA_OPC  EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_RSP_NODATA_OPC EVENT_OPTION_OPCODE=0x0
UMASK_RXL_BASIC_HDR_MATCH_RSP_NODATA_OPC    0x0A 0x01 0x00
OPTIONS_RXL_BASIC_HDR_MATCH_RSP_DATA        EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
UMASK_RXL_BASIC_HDR_MATCH_RSP_DATA          0x0C
OPTIONS_RXL_BASIC_HDR_MATCH_RSP_DATA_OPC    EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_RSP_DATA_OPC EVENT_OPTION_OPCODE=0x0
UMASK_RXL_BASIC_HDR_MATCH_RSP_DATA_OPC      0x0C 0x01 0x00
OPTIONS_RXL_BASIC_HDR_MATCH_WB              EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
UMASK_RXL_BASIC_HDR_MATCH_WB                0x0D
OPTIONS_RXL_BASIC_HDR_MATCH_WB_OPC          EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_WB_OPC  EVENT_OPTION_OPCODE=0x0
UMASK_RXL_BASIC_HDR_MATCH_WB_OPC            0x0D 0x01 0x00
OPTIONS_RXL_BASIC_HDR_MATCH_NCB             EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
UMASK_RXL_BASIC_HDR_MATCH_NCB               0x0E
OPTIONS_RXL_BASIC_HDR_MATCH_NCB_OPC         EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_NCB_OPC  EVENT_OPTION_OPCODE=0x0
UMASK_RXL_BASIC_HDR_MATCH_NCB_OPC           0x0E 0x01 0x00
OPTIONS_RXL_BASIC_HDR_MATCH_NCS             EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
UMASK_RXL_BASIC_HDR_MATCH_NCS               0x0F
OPTIONS_RXL_BASIC_HDR_MATCH_NCS_OPC         EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_NCS_OPC EVENT_OPTION_OPCODE=0x0
UMASK_RXL_BASIC_HDR_MATCH_NCS_OPC           0x0F 0x01 0x00
OPTIONS_RXL_BASIC_HDR_MATCH_RSPCNFLT        EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_RSPCNFLT EVENT_OPTION_OPCODE=0x0
UMASK_RXL_BASIC_HDR_MATCH_RSPCNFLT          0xAA 0x01 0x00
OPTIONS_RXL_BASIC_HDR_MATCH_RSPI            EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_RSPI    EVENT_OPTION_OPCODE=0x0
UMASK_RXL_BASIC_HDR_MATCH_RSPI              0x2A 0x01 0x00

EVENT_RXL_BYPASSED                          0x31 QBOX
UMASK_RXL_BYPASSED_SLOT0                    0x01
UMASK_RXL_BYPASSED_SLOT1                    0x02
UMASK_RXL_BYPASSED_SLOT2                    0x04

EVENT_RXL_FLITS                         0x03 QBOX
UMASK_RXL_FLITS_SLOT0                   0x01
UMASK_RXL_FLITS_SLOT1                   0x02
UMASK_RXL_FLITS_SLOT2                   0x04
UMASK_RXL_FLITS_DATA                    0x08
UMASK_RXL_FLITS_LLCRD                   0x10
UMASK_RXL_FLITS_NULL                    0x20
UMASK_RXL_FLITS_IDLE                    0x40
UMASK_RXL_FLITS_PROTHDR                 0x80
UMASK_RXL_FLITS_SLOT0_DATA              0x09
UMASK_RXL_FLITS_SLOT1_DATA              0x0A
UMASK_RXL_FLITS_SLOT2_DATA              0x0C
UMASK_RXL_FLITS_ALL_DATA                0x0F
UMASK_RXL_FLITS_SLOT0_LLCRD             0x11
UMASK_RXL_FLITS_SLOT1_LLCRD             0x12
UMASK_RXL_FLITS_SLOT2_LLCRD             0x14
UMASK_RXL_FLITS_ALL_LLCRD               0x17
UMASK_RXL_FLITS_SLOT0_NULL              0x21
UMASK_RXL_FLITS_SLOT1_NULL              0x22
UMASK_RXL_FLITS_SLOT2_NULL              0x24
UMASK_RXL_FLITS_ALL_NULL                0x27
UMASK_RXL_FLITS_SLOT0_IDLE              0x41
UMASK_RXL_FLITS_SLOT1_IDLE              0x42
UMASK_RXL_FLITS_SLOT2_IDLE              0x44
UMASK_RXL_FLITS_ALL_IDLE                0x47
UMASK_RXL_FLITS_SLOT0_PROTHDR           0x81
UMASK_RXL_FLITS_SLOT1_PROTHDR           0x82
UMASK_RXL_FLITS_SLOT2_PROTHDR           0x84
UMASK_RXL_FLITS_ALL_PROTHDR             0x87
UMASK_RXL_FLITS_NON_DATA                0xB7

EVENT_RXL_INSERTS                       0x30 QBOX
UMASK_RXL_INSERTS_SLOT0                 0x01
UMASK_RXL_INSERTS_SLOT1                 0x02
UMASK_RXL_INSERTS_SLOT2                 0x04

EVENT_RXL_OCCUPANCY                       0x32 QBOX
UMASK_RXL_OCCUPANCY_SLOT0                 0x01
UMASK_RXL_OCCUPANCY_SLOT1                 0x02
UMASK_RXL_OCCUPANCY_SLOT2                 0x04

EVENT_RXL_SLOT_BYPASS                   0x33 QBOX
UMASK_RXL_SLOT_BYPASS_S0_RXQ1           0x01
UMASK_RXL_SLOT_BYPASS_S0_RXQ2           0x02
UMASK_RXL_SLOT_BYPASS_S1_RXQ0           0x04
UMASK_RXL_SLOT_BYPASS_S1_RXQ2           0x08
UMASK_RXL_SLOT_BYPASS_S2_RXQ0           0x10
UMASK_RXL_SLOT_BYPASS_S2_RXQ1           0x20

EVENT_TXL0P_CLK_ACTIVE                  0x2A QBOX
UMASK_TXL0P_CLK_ACTIVE_CFG_CTL          0x01
UMASK_TXL0P_CLK_ACTIVE_RXQ              0x02
UMASK_TXL0P_CLK_ACTIVE_RXQ_BYPASS       0x04
UMASK_TXL0P_CLK_ACTIVE_RXQ_CRED         0x08
UMASK_TXL0P_CLK_ACTIVE_TXQ              0x10
UMASK_TXL0P_CLK_ACTIVE_RETRY            0x20
UMASK_TXL0P_CLK_ACTIVE_DFX              0x40
UMASK_TXL0P_CLK_ACTIVE_SPARE            0x80

EVENT_TXL_FLITS                         0x02 QBOX
UMASK_TXL_FLITS_SLOT0                   0x01
UMASK_TXL_FLITS_SLOT1                   0x02
UMASK_TXL_FLITS_SLOT2                   0x04
UMASK_TXL_FLITS_DATA                    0x08
UMASK_TXL_FLITS_LLCRD                   0x10
UMASK_TXL_FLITS_NULL                    0x20
UMASK_TXL_FLITS_LLCTRL                  0x40
UMASK_TXL_FLITS_PROTHDR                 0x80
UMASK_TXL_FLITS_SLOT0_DATA              0x09
UMASK_TXL_FLITS_SLOT1_DATA              0x0A
UMASK_TXL_FLITS_SLOT2_DATA              0x0C
UMASK_TXL_FLITS_ALL_DATA                0x0F
UMASK_TXL_FLITS_SLOT0_LLCRD             0x11
UMASK_TXL_FLITS_SLOT1_LLCRD             0x12
UMASK_TXL_FLITS_SLOT2_LLCRD             0x14
UMASK_TXL_FLITS_ALL_LLCRD               0x17
UMASK_TXL_FLITS_SLOT0_NULL              0x21
UMASK_TXL_FLITS_SLOT1_NULL              0x22
UMASK_TXL_FLITS_SLOT2_NULL              0x24
UMASK_TXL_FLITS_ALL_NULL                0x27
UMASK_TXL_FLITS_SLOT0_IDLE              0x41
UMASK_TXL_FLITS_SLOT1_IDLE              0x42
UMASK_TXL_FLITS_SLOT2_IDLE              0x44
UMASK_TXL_FLITS_ALL_IDLE                0x47
UMASK_TXL_FLITS_SLOT0_PROTHDR           0x81
UMASK_TXL_FLITS_SLOT1_PROTHDR           0x82
UMASK_TXL_FLITS_SLOT2_PROTHDR           0x84
UMASK_TXL_FLITS_ALL_PROTHDR             0x87
UMASK_TXL_FLITS_NON_DATA                0xB7

EVENT_TXL_BASIC_HDR_MATCH                   0x04 QBOX
OPTIONS_TXL_BASIC_HDR_MATCH_REQ             EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
UMASK_TXL_BASIC_HDR_MATCH_REQ               0x08
OPTIONS_TXL_BASIC_HDR_MATCH_REQ_OPC         EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_REQ_OPC EVENT_OPTION_OPCODE=0x0
UMASK_TXL_BASIC_HDR_MATCH_REQ_OPC           0x08 0x01 0x00
OPTIONS_TXL_BASIC_HDR_MATCH_SNP             EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
UMASK_TXL_BASIC_HDR_MATCH_SNP               0x09
OPTIONS_TXL_BASIC_HDR_MATCH_SNP_OPC         EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_SNP_OPC EVENT_OPTION_OPCODE=0x0
UMASK_TXL_BASIC_HDR_MATCH_SNP_OPC           0x09 0x01 0x00
OPTIONS_TXL_BASIC_HDR_MATCH_RSP_NODATA      EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
UMASK_TXL_BASIC_HDR_MATCH_RSP_NODATA        0x0A
OPTIONS_TXL_BASIC_HDR_MATCH_RSP_NODATA_OPC  EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_RSP_NODATA_OPC EVENT_OPTION_OPCODE=0x0
UMASK_TXL_BASIC_HDR_MATCH_RSP_NODATA_OPC    0x0A 0x01 0x00
OPTIONS_TXL_BASIC_HDR_MATCH_RSP_DATA        EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
UMASK_TXL_BASIC_HDR_MATCH_RSP_DATA          0x0C
OPTIONS_TXL_BASIC_HDR_MATCH_RSP_DATA_OPC    EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_RSP_DATA_OPC EVENT_OPTION_OPCODE=0x0
UMASK_TXL_BASIC_HDR_MATCH_RSP_DATA_OPC      0x0C 0x01 0x00
OPTIONS_TXL_BASIC_HDR_MATCH_WB              EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
UMASK_TXL_BASIC_HDR_MATCH_WB                0x0D
OPTIONS_TXL_BASIC_HDR_MATCH_WB_OPC          EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_WB_OPC  EVENT_OPTION_OPCODE=0x0
UMASK_TXL_BASIC_HDR_MATCH_WB_OPC            0x0D 0x01 0x00
OPTIONS_TXL_BASIC_HDR_MATCH_NCB             EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
UMASK_TXL_BASIC_HDR_MATCH_NCB               0x0E
OPTIONS_TXL_BASIC_HDR_MATCH_NCB_OPC         EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_NCB_OPC  EVENT_OPTION_OPCODE=0x0
UMASK_TXL_BASIC_HDR_MATCH_NCB_OPC           0x0E 0x01 0x00
OPTIONS_TXL_BASIC_HDR_MATCH_NCS             EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
UMASK_TXL_BASIC_HDR_MATCH_NCS               0x0F
OPTIONS_TXL_BASIC_HDR_MATCH_NCS_OPC         EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_NCS_OPC EVENT_OPTION_OPCODE=0x0
UMASK_TXL_BASIC_HDR_MATCH_NCS_OPC           0x0F 0x01 0x00
OPTIONS_TXL_BASIC_HDR_MATCH_RSPCNFLT        EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_RSPCNFLT EVENT_OPTION_OPCODE=0x0
UMASK_TXL_BASIC_HDR_MATCH_RSPCNFLT          0xAA 0x01 0x00
OPTIONS_TXL_BASIC_HDR_MATCH_RSPI            EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_OPCODE_MASK
DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_RSPI    EVENT_OPTION_OPCODE=0x0
UMASK_TXL_BASIC_HDR_MATCH_RSPI              0x2A 0x01 0x00

EVENT_PHY_INIT_CYCLES                   0x20 QBOX
UMASK_PHY_INIT_CYCLES                   0x00

EVENT_POWER_L1_NACK                     0x23 QBOX
UMASK_POWER_L1_NACK                     0x00

EVENT_POWER_L1_REQ                      0x22 QBOX
UMASK_POWER_L1_REQ                      0x00

EVENT_RXL0P_POWER_CYCLES                0x25 QBOX
UMASK_RXL0P_POWER_CYCLES                0x00

EVENT_RXL0_POWER_CYCLES                 0x24 QBOX
UMASK_RXL0_POWER_CYCLES                 0x00

EVENT_RXL_CRC_ERRORS                    0x0B QBOX
UMASK_RXL_CRC_ERRORS                    0x00

EVENT_RXL_CRC_LLR_REQ_TRANSMIT          0x08 QBOX
UMASK_RXL_CRC_LLR_REQ_TRANSMIT          0x00

EVENT_RXL_CREDITS_CONSUMED_VN0          0x39 QBOX
UMASK_RXL_CREDITS_CONSUMED_VN0          0x00

EVENT_RXL_CREDITS_CONSUMED_VN1          0x3A QBOX
UMASK_RXL_CREDITS_CONSUMED_VN1          0x00

EVENT_RXL_CREDITS_CONSUMED_VNA          0x38 QBOX
UMASK_RXL_CREDITS_CONSUMED_VNA          0x00

EVENT_TXL0P_POWER_CYCLES_LL_ENTER       0x28 QBOX
UMASK_TXL0P_POWER_CYCLES_LL_ENTER       0x00

EVENT_TXL0P_POWER_CYCLES_M3_EXIT        0x29 QBOX
UMASK_TXL0P_POWER_CYCLES_M3_EXIT        0x00

EVENT_TXL0_POWER_CYCLES                 0x26 QBOX
UMASK_TXL0_POWER_CYCLES                 0x00

EVENT_TXL_BYPASSED                      0x41 QBOX
UMASK_TXL_BYPASSED                      0x00

EVENT_TXL_INSERTS                       0x40 QBOX
UMASK_TXL_INSERTS                       0x00

EVENT_TXL_OCCUPANCY                     0x42 QBOX
UMASK_TXL_OCCUPANCY                     0x00

EVENT_VNA_CREDIT_RETURN_BLOCKED_VN01    0x45 QBOX
UMASK_VNA_CREDIT_RETURN_BLOCKED_VN01    0x00

EVENT_VNA_CREDIT_RETURN_OCCUPANCY       0x44 QBOX
UMASK_VNA_CREDIT_RETURN_OCCUPANCY       0x00

EVENT_CORE_TRANSITION_CYCLES            0x60 WBOX
UMASK_CORE_TRANSITION_CYCLES            0x00

EVENT_DEMOTIONS                         0x30 WBOX
UMASK_DEMOTIONS                         0x00

EVENT_FIVR_PS_PS0_CYCLES                0x75 WBOX
UMASK_FIVR_PS_PS0_CYCLES                0x00

EVENT_FIVR_PS_PS1_CYCLES                0x76 WBOX
UMASK_FIVR_PS_PS1_CYCLES                0x00

EVENT_FIVR_PS_PS2_CYCLES                0x77 WBOX
UMASK_FIVR_PS_PS2_CYCLES                0x00

EVENT_FIVR_PS_PS3_CYCLES                0x78 WBOX
UMASK_FIVR_PS_PS3_CYCLES                0x00

EVENT_FREQ_CLIP_AVX256                  0x49 WBOX
UMASK_FREQ_CLIP_AVX256                  0x00

EVENT_FREQ_CLIP_AVX512                  0x4A WBOX
UMASK_FREQ_CLIP_AVX512                  0x00

EVENT_FREQ_MAX_LIMIT_THERMAL_CYCLES     0x04 WBOX
UMASK_FREQ_MAX_LIMIT_THERMAL_CYCLES     0x00

EVENT_FREQ_MAX_POWER_CYCLES             0x05 WBOX
UMASK_FREQ_MAX_POWER_CYCLES             0x00

EVENT_FREQ_MIN_IO_P_CYCLES              0x73 WBOX
UMASK_FREQ_MIN_IO_P_CYCLES              0x00

EVENT_FREQ_TRANS_CYCLES                 0x74 WBOX
UMASK_FREQ_TRANS_CYCLES                 0x00

EVENT_MEMORY_PHASE_SHEDDING_CYCLES      0x2F WBOX
UMASK_MEMORY_PHASE_SHEDDING_CYCLES      0x00

EVENT_PKG_RESIDENCY_C0_CYCLES           0x2A WBOX
UMASK_PKG_RESIDENCY_C0_CYCLES           0x00

EVENT_PKG_RESIDENCY_C2E_CYCLES          0x2B WBOX
UMASK_PKG_RESIDENCY_C2E_CYCLES          0x00

EVENT_PKG_RESIDENCY_C3_CYCLES           0x2C WBOX
UMASK_PKG_RESIDENCY_C3_CYCLES           0x00

EVENT_PKG_RESIDENCY_C6_CYCLES           0x2D WBOX
UMASK_PKG_RESIDENCY_C6_CYCLES           0x00

EVENT_PMAX_THROTTLED_CYCLES             0x06 WBOX
UMASK_PMAX_THROTTLED_CYCLES             0x00

EVENT_PROCHOT_EXTERNAL_CYCLES           0x0A WBOX
UMASK_PROCHOT_EXTERNAL_CYCLES           0x00

EVENT_PROCHOT_INTERNAL_CYCLES           0x09 WBOX
UMASK_PROCHOT_INTERNAL_CYCLES           0x00

EVENT_TOTAL_TRANSITION_CYCLES           0x72 WBOX
UMASK_TOTAL_TRANSITION_CYCLES           0x00

EVENT_VR_HOT_CYCLES                     0x42 WBOX
UMASK_VR_HOT_CYCLES                     0x00

EVENT_POWER_STATE_OCCUPANCY             0x80 WBOX
UMASK_POWER_STATE_OCCUPANCY_CORES_C0    0x40
UMASK_POWER_STATE_OCCUPANCY_CORES_C3    0x80
UMASK_POWER_STATE_OCCUPANCY_CORES_C6    0xC0

EVENT_CORES_IN_C3                       0x00 WBOX0FIX
UMASK_CORES_IN_C3                       0x00

EVENT_CORES_IN_C6                       0x00 WBOX1FIX
UMASK_CORES_IN_C6                       0x00

EVENT_CORES_IN_P3                       0x00 WBOX2FIX
UMASK_CORES_IN_P3                       0x00

EVENT_CORES_IN_P6                       0x00 WBOX3FIX
UMASK_CORES_IN_P6                       0x00

EVENT_IRP_CLOCKTICKS                    0x01 IBOX
UMASK_IRP_CLOCKTICKS                    0x00

EVENT_SNOOP_RESP                        0x12 IBOX
UMASK_SNOOP_RESP_MISS                   0x01
UMASK_SNOOP_RESP_HIT_I                  0x02
UMASK_SNOOP_RESP_HIT_ES                 0x04
UMASK_SNOOP_RESP_HIT_M                  0x08
UMASK_SNOOP_RESP_SNPCODE                0x10
UMASK_SNOOP_RESP_SNPDATA                0x20
UMASK_SNOOP_RESP_SNPINV                 0x40
UMASK_SNOOP_RESP_ALL_MISS               0x71
UMASK_SNOOP_RESP_ALL_HIT                0x7E
UMASK_SNOOP_RESP_ALL_HIT_ES             0x74
UMASK_SNOOP_RESP_ALL_HIT_I              0x72

EVENT_I_COHERENT_OPS                    0x10 IBOX
UMASK_I_COHERENT_OPS_RFO                0x08
UMASK_I_COHERENT_OPS_CLFLUSH            0x80

EVENT_CACHE_TOTAL_OCCUPANCY             0x0F IBOX
UMASK_CACHE_TOTAL_OCCUPANCY_ANY         0x01
UMASK_CACHE_TOTAL_OCCUPANCY_IV_Q        0x02

EVENT_IRP_ALL                           0x20 IBOX
UMASK_IRP_ALL_OUTBOUND_INSERTS          0x02
UMASK_IRP_ALL_EVICTS                    0x04

EVENT_MISC0                             0x1E IBOX
UMASK_MISC0_FAST_REQ                    0x01
UMASK_MISC0_FAST_REJ                    0x02
UMASK_MISC0_2ND_RD_INSERT               0x04
UMASK_MISC0_2ND_WR_INSERT               0x08
UMASK_MISC0_2ND_ATOMIC_INSERT           0x10
UMASK_MISC0_FAST_XFER                   0x20
UMASK_MISC0_PF_ACK_HINT                 0x40
UMASK_MISC0_SLOWPATH_FWPF_NO_PRF        0x80

EVENT_MISC1                             0x1F IBOX
UMASK_MISC1_SLOW_I                      0x01
UMASK_MISC1_SLOW_S                      0x02
UMASK_MISC1_SLOW_E                      0x04
UMASK_MISC1_SLOW_M                      0x08
UMASK_MISC1_SEC_RCVD_INVLD              0x20
UMASK_MISC1_SEC_RCVD_VLD                0x40

EVENT_P2P_TRANSACTIONS                      0x13 IBOX
UMASK_P2P_TRANSACTIONS_RD                   0x01
UMASK_P2P_TRANSACTIONS_WR                   0x02
UMASK_P2P_TRANSACTIONS_MSG                  0x04
UMASK_P2P_TRANSACTIONS_CMPL                 0x08
UMASK_P2P_TRANSACTIONS_REM                  0x10
UMASK_P2P_TRANSACTIONS_REM_AND_TGT_MATCH    0x20
UMASK_P2P_TRANSACTIONS_LOC                  0x40
UMASK_P2P_TRANSACTIONS_LOC_AND_TGT_MATCH    0x80

EVENT_TRANSACTIONS                      0x11 IBOX
UMASK_TRANSACTIONS_WRITES               0x02
UMASK_TRANSACTIONS_ATOMIC               0x10
UMASK_TRANSACTIONS_OTHER                0x20
UMASK_TRANSACTIONS_ORDERINGQ            0x40

EVENT_P2P_INSERTS                       0x14 IBOX
UMASK_P2P_INSERTS                       0x00

EVENT_P2P_OCCUPANCY                     0x15 IBOX
UMASK_P2P_OCCUPANCY                     0x00

EVENT_TxC_AK_INSERTS                    0x0B IBOX
UMASK_TxC_AK_INSERTS                    0x00

EVENT_TxC_BL_DRS_CYCLES_FULL            0x05 IBOX
UMASK_TxC_BL_DRS_CYCLES_FULL            0x00

EVENT_TxC_BL_DRS_INSERTS                0x02 IBOX
UMASK_TxC_BL_DRS_INSERTS                0x00

EVENT_TxC_BL_DRS_OCCUPANCY              0x08 IBOX
UMASK_TxC_BL_DRS_OCCUPANCY              0x00

EVENT_TxC_BL_NCB_CYCLES_FULL            0x06 IBOX
UMASK_TxC_BL_NCB_CYCLES_FULL            0x00

EVENT_TxC_BL_NCB_INSERTS                0x03 IBOX
UMASK_TxC_BL_NCB_INSERTS                0x00

EVENT_TxC_BL_NCB_OCCUPANCY              0x09 IBOX
UMASK_TxC_BL_NCB_OCCUPANCY              0x00

EVENT_TxC_BL_NCS_CYCLES_FULL            0x07 IBOX
UMASK_TxC_BL_NCS_CYCLES_FULL            0x00

EVENT_TxC_BL_NCS_INSERTS                0x04 IBOX
UMASK_TxC_BL_NCS_INSERTS                0x00

EVENT_TxC_BL_NCS_OCCUPANCY              0x0A IBOX
UMASK_TxC_BL_NCS_OCCUPANCY              0x00

EVENT_TxR2_AD01_STALL_CREDIT_CYCLES     0x1C IBOX
UMASK_TxR2_AD01_STALL_CREDIT_CYCLES     0x00

EVENT_TxR2_AD0_STALL_CREDIT_CYCLES      0x1A IBOX
UMASK_TxR2_AD0_STALL_CREDIT_CYCLES      0x00

EVENT_TxR2_AD1_STALL_CREDIT_CYCLES      0x1B IBOX
UMASK_TxR2_AD1_STALL_CREDIT_CYCLES      0x00

EVENT_TxR2_BL_STALL_CREDIT_CYCLES       0x1D IBOX
UMASK_TxR2_BL_STALL_CREDIT_CYCLES       0x00

EVENT_TxS_DATA_INSERTS_NCB              0x0D IBOX
UMASK_TxS_DATA_INSERTS_NCB              0x00

EVENT_TxS_DATA_INSERTS_NCS              0x0E IBOX
UMASK_TxS_DATA_INSERTS_NCS              0x00

EVENT_TxS_REQUEST_OCCUPANCY             0x0C IBOX
UMASK_TxS_REQUEST_OCCUPANCY             0x00

EVENT_IIO_BANDWIDTH_IN_PORT0            0x00 IBOX0PORT0|IBOX1PORT0|IBOX2PORT0|IBOX3PORT0|IBOX4PORT0|IBOX5PORT0
UMASK_IIO_BANDWIDTH_IN_PORT0            0x00

EVENT_IIO_BANDWIDTH_IN_PORT1            0x00 IBOX0PORT1|IBOX1PORT1|IBOX2PORT1|IBOX3PORT1|IBOX4PORT1|IBOX5PORT1
UMASK_IIO_BANDWIDTH_IN_PORT1            0x00

EVENT_IIO_BANDWIDTH_IN_PORT2            0x00 IBOX0PORT2|IBOX1PORT2|IBOX2PORT2|IBOX3PORT2|IBOX4PORT2|IBOX5PORT2
UMASK_IIO_BANDWIDTH_IN_PORT2            0x00

EVENT_IIO_BANDWIDTH_IN_PORT3            0x00 IBOX0PORT3|IBOX1PORT3|IBOX2PORT3|IBOX3PORT3|IBOX4PORT3|IBOX5PORT3
UMASK_IIO_BANDWIDTH_IN_PORT3            0x00

EVENT_IIO_BANDWIDTH_IN_PORT4            0x00 IBOX0PORT4|IBOX1PORT4|IBOX2PORT4|IBOX3PORT4|IBOX4PORT4|IBOX5PORT4
UMASK_IIO_BANDWIDTH_IN_PORT4            0x00

EVENT_IIO_BANDWIDTH_IN_PORT5            0x00 IBOX0PORT5|IBOX1PORT5|IBOX2PORT5|IBOX3PORT5|IBOX4PORT5|IBOX5PORT5
UMASK_IIO_BANDWIDTH_IN_PORT5            0x00

EVENT_IIO_BANDWIDTH_IN_PORT6            0x00 IBOX0PORT6|IBOX1PORT6|IBOX2PORT6|IBOX3PORT6|IBOX4PORT6|IBOX5PORT6
UMASK_IIO_BANDWIDTH_IN_PORT6            0x00

EVENT_IIO_BANDWIDTH_IN_PORT7            0x00 IBOX0PORT7|IBOX1PORT7|IBOX2PORT7|IBOX3PORT7|IBOX4PORT7|IBOX5PORT7
UMASK_IIO_BANDWIDTH_IN_PORT7            0x00

EVENT_IIO_CLOCKTICKS                    0x01 TCBOX0|TCBOX1|TCBOX2|TCBOX3|TCBOX4|TCBOX5|TCBOXFIX
UMASK_IIO_CLOCKTICKS                    0x00

EVENT_IOMMU0                            0x40 TCBOX
UMASK_IOMMU0_FIRST_LOOKUPS              0x01
UMASK_IOMMU0_ALL_LOOKUPS                0x02
UMASK_IOMMU0_4K_HITS                    0x04
UMASK_IOMMU0_2M_HITS                    0x08
UMASK_IOMMU0_1G_HITS                    0x10
UMASK_IOMMU0_MISSES                     0x20
UMASK_IOMMU0_CTXT_CACHE_LOOKUPS         0x40
UMASK_IOMMU0_CTXT_CACHE_HITS            0x80

EVENT_IOMMU1                            0x41 TCBOX
UMASK_IOMMU1_PWT_CACHE_LOOKUPS          0x01
UMASK_IOMMU1_PWC_4K_HITS                0x02
UMASK_IOMMU1_PWC_2M_HITS                0x04
UMASK_IOMMU1_PWC_1G_HITS                0x08
UMASK_IOMMU1_PWC_512G_HITS              0x10
UMASK_IOMMU1_PWC_CACHE_FILLS            0x20
UMASK_IOMMU1_NUM_MEM_ACCESSES           0x40
UMASK_IOMMU1_CYC_PWT_FULL               0x80

EVENT_IOMMU3                                0x43 TCBOX
UMASK_IOMMU3_NUM_INVAL_GBL                  0x01
UMASK_IOMMU3_NUM_INVAL_DOMAIN               0x02
UMASK_IOMMU3_NUM_INVAL_PAGE                 0x04
UMASK_IOMMU3_NUM_CTXT_CACHE_INVAL_GBL       0x08
UMASK_IOMMU3_NUM_CTXT_CACHE_INVAL_DOMAIN    0x10
UMASK_IOMMU3_NUM_CTXT_CACHE_INVAL_DEVICE    0x20
UMASK_IOMMU3_INT_CACHE_LOOKUPS              0x40
UMASK_IOMMU3_INT_CACHE_HITS                 0x80

EVENT_MASK_MATCH_AND                    0x02 TCBOX0C0|TCBOX0C1|TCBOX1C0|TCBOX1C1|TCBOX2C0|TCBOX2C1|TCBOX3C0|TCBOX3C1|TCBOX4C0|TCBOX4C1|TCBOX5C0|TCBOX5C1
UMASK_MASK_MATCH_AND_BUS0               0x01
UMASK_MASK_MATCH_AND_BUS1               0x02
UMASK_MASK_MATCH_AND_BUS0_NOT_BUS1      0x04
UMASK_MASK_MATCH_AND_BUS0_BUS1          0x08
UMASK_MASK_MATCH_AND_NOT_BUS0_BUS1      0x10
UMASK_MASK_MATCH_AND_NOT_BUS0_NOT_BUS1  0x20

EVENT_MASK_MATCH_OR                     0x03 TCBOX0C0|TCBOX0C1|TCBOX1C0|TCBOX1C1|TCBOX2C0|TCBOX2C1|TCBOX3C0|TCBOX3C1|TCBOX4C0|TCBOX4C1|TCBOX5C0|TCBOX5C1
UMASK_MASK_MATCH_OR_BUS0                0x01
UMASK_MASK_MATCH_OR_BUS1                0x02
UMASK_MASK_MATCH_OR_BUS0_NOT_BUS1       0x04
UMASK_MASK_MATCH_OR_BUS0_BUS1           0x08
UMASK_MASK_MATCH_OR_NOT_BUS0_BUS1       0x10
UMASK_MASK_MATCH_OR_NOT_BUS0_NOT_BUS1   0x20

EVENT_NUM_REQ_OF_CPU                    0x85 TCBOX
DEFAULT_OPTIONS_NUM_REQ_OF_CPU          EVENT_OPTION_MASK0=0xFF,EVENT_OPTION_MASK1=0x07
UMASK_NUM_REQ_OF_CPU_ALL_DROP           0x02

EVENT_NOTHING                           0x80 TCBOX
UMASK_NOTHING                           0x00

EVENT_PWT_OCCUPANCY                     0x42 TCBOX
UMASK_PWT_OCCUPANCY                     0x00

EVENT_SYMBOL_TIMES                      0x82 TCBOX
UMASK_SYMBOL_TIMES                      0x00

EVENT_NUM_REQ_OF_CPU_BY_TGT                 0x8E TCBOX
DEFAULT_OPTIONS_NUM_REQ_OF_CPU_BY_TGT       EVENT_OPTION_MASK0=0xFF,EVENT_OPTION_MASK1=0x07
UMASK_NUM_REQ_OF_CPU_BY_TGT_MSGB            0x01
UMASK_NUM_REQ_OF_CPU_BY_TGT_MCAST           0x02
UMASK_NUM_REQ_OF_CPU_BY_TGT_UBOX            0x04
UMASK_NUM_REQ_OF_CPU_BY_TGT_MEM             0x08
UMASK_NUM_REQ_OF_CPU_BY_TGT_REM_P2P         0x10
UMASK_NUM_REQ_OF_CPU_BY_TGT_LOC_P2P         0x20
UMASK_NUM_REQ_OF_CPU_BY_TGT_CONFINED_P2P    0x40
UMASK_NUM_REQ_OF_CPU_BY_TGT_ABORT           0x80

EVENT_NUM_TGT_MATCHED_REQ_OF_CPU        0x8F TCBOX
UMASK_NUM_TGT_MATCHED_REQ_OF_CPU        0x00

EVENT_NUM_OUTSTANDING_REQ_OF_CPU                0x88 TCBOX0C2|TCBOX0C2|TCBOX1C2|TCBOX1C3|TCBOX2C2|TCBOX2C3|TCBOX3C2|TCBOX3C3|TCBOX4C2|TCBOX4C3|TCBOX5C2|TCBOX5C3
DEFAULT_OPTIONS_NUM_OUSTANDING_REQ_OF_CPU       EVENT_OPTION_MASK0=0xFF,EVENT_OPTION_MASK1=0x07
UMASK_NUM_OUTSTANDING_REQ_OF_CPU_IOMMU_REQ      0x01
UMASK_NUM_OUTSTANDING_REQ_OF_CPU_IOMMU_HIT      0x02
UMASK_NUM_OUTSTANDING_REQ_OF_CPU_REQ_OWN        0x04
UMASK_NUM_OUTSTANDING_REQ_OF_CPU_FINAL_RD_WR    0x08
UMASK_NUM_OUTSTANDING_REQ_OF_CPU_WR             0x10
UMASK_NUM_OUTSTANDING_REQ_OF_CPU_DATA           0x20

EVENT_NUM_OUSTANDING_REQ_FROM_CPU               0xC5 TCBOX0C2|TCBOX0C2|TCBOX1C2|TCBOX1C3|TCBOX2C2|TCBOX2C3|TCBOX3C2|TCBOX3C3|TCBOX4C2|TCBOX4C3|TCBOX5C2|TCBOX5C3
DEFAULT_OPTIONS_NUM_OUSTANDING_REQ_FROM_CPU     EVENT_OPTION_MASK0=0xFF,EVENT_OPTION_MASK1=0x07
UMASK_NUM_OUSTANDING_REQ_FROM_CPU_TO_IO         0x08

EVENT_REQ_FROM_PCIE_CL_CMPL                     0x91 TCBOX
DEFAULT_OPTIONS_REQ_FROM_PCIE_CL_CMPL           EVENT_OPTION_MASK0=0xFF,EVENT_OPTION_MASK1=0x07
UMASK_REQ_FROM_PCIE_CL_CMPL_REQ_OWN             0x04
UMASK_REQ_FROM_PCIE_CL_CMPL_FINAL_RD_WR         0x08
UMASK_REQ_FROM_PCIE_CL_CMPL_WR                  0x10
UMASK_REQ_FROM_PCIE_CL_CMPL_DATA                0x20

EVENT_REQ_FROM_PCIE_CMPL                        0x92 TCBOX
DEFAULT_OPTIONS_REQ_FROM_PCIE_CMPL              EVENT_OPTION_MASK0=0xFF,EVENT_OPTION_MASK1=0x07
UMASK_REQ_FROM_PCIE_CMPL_IOMMU_REQ              0x01
UMASK_REQ_FROM_PCIE_CMPL_IOMMU_HIT              0x02
UMASK_REQ_FROM_PCIE_CMPL_REQ_OWN                0x04
UMASK_REQ_FROM_PCIE_CMPL_FINAL_RD_WR            0x08
UMASK_REQ_FROM_PCIE_CMPL_WR                     0x10
UMASK_REQ_FROM_PCIE_CMPL_DATA                   0x20

EVENT_REQ_FROM_PCIE_PASS_CMPL                   0x90 TCBOX
DEFAULT_OPTIONS_REQ_FROM_PCIE_PASS_CMPL         EVENT_OPTION_MASK0=0xFF,EVENT_OPTION_MASK1=0x07
UMASK_REQ_FROM_PCIE_PASS_CMPL_REQ_OWN           0x04
UMASK_REQ_FROM_PCIE_PASS_CMPL_FINAL_RD_WR       0x08
UMASK_REQ_FROM_PCIE_PASS_CMPL_WR                0x10
UMASK_REQ_FROM_PCIE_PASS_CMPL_DATA              0x20

EVENT_INBOUND_ARB_REQ                           0x86 TCBOX
DEFAULT_OPTIONS_INBOUND_ARB_REQ                 EVENT_OPTION_MASK0=0xFF,EVENT_OPTION_MASK1=0x07
UMASK_INBOUND_ARB_REQ_IOMMU_REQ                 0x01
UMASK_INBOUND_ARB_REQ_IOMMU_HIT                 0x02
UMASK_INBOUND_ARB_REQ_REQ_OWN                   0x04
UMASK_INBOUND_ARB_REQ_FINAL_RD_WR               0x08
UMASK_INBOUND_ARB_REQ_WR                        0x10
UMASK_INBOUND_ARB_REQ_DATA                      0x20

EVENT_INBOUND_ARB_WON                           0x87 TCBOX
DEFAULT_OPTIONS_INBOUND_ARB_WON                 EVENT_OPTION_MASK0=0xFF,EVENT_OPTION_MASK1=0x07
UMASK_INBOUND_ARB_WON_IOMMU_REQ                 0x01
UMASK_INBOUND_ARB_WON_IOMMU_HIT                 0x02
UMASK_INBOUND_ARB_WON_REQ_OWN                   0x04
UMASK_INBOUND_ARB_WON_FINAL_RD_WR               0x08
UMASK_INBOUND_ARB_WON_WR                        0x10
UMASK_INBOUND_ARB_WON_DATA                      0x20

EVENT_OUTBOUND_CL_REQS_ISSUED                   0xD0 TCBOX
DEFAULT_OPTIONS_CL_REQS_ISSUED_TO_IO            EVENT_OPTION_MASK0=0xFF,EVENT_OPTION_MASK1=0x07
UMASK_OUTBOUND_CL_REQS_ISSUED_TO_IO             0x08

EVENT_OUTBOUND_TLP_REQS_ISSUED                  0xD1 TCBOX
DEFAULT_OPTIONS_TLP_REQS_ISSUED_TO_IO           EVENT_OPTION_MASK0=0xFF,EVENT_OPTION_MASK1=0x07
UMASK_OUTBOUND_TLP_REQS_ISSUED_TO_IO            0x08

EVENT_NUM_REQ_FROM_CPU                  0xC2 TCBOX
DEFAULT_OPTIONS_NUM_REQ_FROM_CPU        EVENT_OPTION_MASK0=0xFF,EVENT_OPTION_MASK1=0x07
UMASK_NUM_REQ_FROM_CPU_IRP              0x01
UMASK_NUM_REQ_FROM_CPU_ITC              0x02
UMASK_NUM_REQ_FROM_CPU_PREALLOC         0x04

EVENT_COMP_BUF_INSERTS                          0xC2 TCBOX
DEFAULT_OPTIONS_COMP_BUF_INSERTS_CMPD_ALL       EVENT_OPTION_MASK0=0xFF,EVENT_OPTION_MASK1=0x04
UMASK_COMP_BUF_INSERTS_CMPD_ALL                 0x04


EVENT_TXN_REQ_BY_CPU                    0xC1 TCBOX
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_PEER_WRITE_PART0 EVENT_OPTION_MASK0=0x01,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_PEER_WRITE_PART0   0x02
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_PEER_WRITE_PART1 EVENT_OPTION_MASK0=0x02,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_PEER_WRITE_PART1   0x02
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_PEER_WRITE_PART2 EVENT_OPTION_MASK0=0x04,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_PEER_WRITE_PART2   0x02
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_PEER_WRITE_PART3 EVENT_OPTION_MASK0=0x08,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_PEER_WRITE_PART3   0x02
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_PEER_WRITE_PART4 EVENT_OPTION_MASK0=0x10,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_PEER_WRITE_PART4   0x02
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_PEER_WRITE_PART5 EVENT_OPTION_MASK0=0x20,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_PEER_WRITE_PART5   0x02
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_PEER_WRITE_PART6 EVENT_OPTION_MASK0=0x40,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_PEER_WRITE_PART6   0x02
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_PEER_WRITE_PART7 EVENT_OPTION_MASK0=0x80,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_PEER_WRITE_PART7   0x02
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_PEER_WRITE_IOMMU0 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_PEER_WRITE_IOMMU0  0x02 # strange
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_PEER_READ_PART0 EVENT_OPTION_MASK0=0x01,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_PEER_READ_PART0    0x08
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_PEER_READ_PART1 EVENT_OPTION_MASK0=0x02,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_PEER_READ_PART1    0x08
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_PEER_READ_PART2 EVENT_OPTION_MASK0=0x04,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_PEER_READ_PART2    0x08
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_PEER_READ_PART3 EVENT_OPTION_MASK0=0x08,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_PEER_READ_PART3    0x08
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_PEER_READ_PART4 EVENT_OPTION_MASK0=0x10,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_PEER_READ_PART4    0x08
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_PEER_READ_PART5 EVENT_OPTION_MASK0=0x20,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_PEER_READ_PART5    0x08
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_PEER_READ_PART6 EVENT_OPTION_MASK0=0x40,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_PEER_READ_PART6    0x08
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_PEER_READ_PART7 EVENT_OPTION_MASK0=0x80,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_PEER_READ_PART7    0x08
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_PEER_READ_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_PEER_READ_IOMMU0   0x08
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_PEER_READ_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_PEER_READ_IOMMU1   0x08
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_CFG_WRITE_PART0 EVENT_OPTION_MASK0=0x01,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_CFG_WRITE_PART0    0x10
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_CFG_WRITE_PART1 EVENT_OPTION_MASK0=0x02,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_CFG_WRITE_PART1    0x10
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_CFG_WRITE_PART2 EVENT_OPTION_MASK0=0x04,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_CFG_WRITE_PART2    0x10
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_CFG_WRITE_PART3 EVENT_OPTION_MASK0=0x08,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_CFG_WRITE_PART3    0x10
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_CFG_WRITE_PART4 EVENT_OPTION_MASK0=0x10,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_CFG_WRITE_PART4    0x10
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_CFG_WRITE_PART5 EVENT_OPTION_MASK0=0x20,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_CFG_WRITE_PART5    0x10
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_CFG_WRITE_PART6 EVENT_OPTION_MASK0=0x40,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_CFG_WRITE_PART6    0x10
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_CFG_WRITE_PART7 EVENT_OPTION_MASK0=0x80,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_CFG_WRITE_PART7    0x10
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_CFG_WRITE_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_CFG_WRITE_IOMMU0   0x10
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_CFG_WRITE_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_CFG_WRITE_IOMMU1   0x10
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_CFG_READ_PART0 EVENT_OPTION_MASK0=0x01,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_CFG_READ_PART0     0x40
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_CFG_READ_PART1 EVENT_OPTION_MASK0=0x02,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_CFG_READ_PART1     0x40
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_CFG_READ_PART2 EVENT_OPTION_MASK0=0x04,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_CFG_READ_PART2     0x40
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_CFG_READ_PART3 EVENT_OPTION_MASK0=0x08,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_CFG_READ_PART3     0x40
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_CFG_READ_PART4 EVENT_OPTION_MASK0=0x10,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_CFG_READ_PART4     0x40
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_CFG_READ_PART5 EVENT_OPTION_MASK0=0x20,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_CFG_READ_PART5     0x40
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_CFG_READ_PART6 EVENT_OPTION_MASK0=0x40,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_CFG_READ_PART6     0x40
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_CFG_READ_PART7 EVENT_OPTION_MASK0=0x80,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_CFG_READ_PART7     0x40
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_CFG_READ_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_CFG_READ_IOMMU0    0x40
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_CFG_READ_IOMMU0 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_CFG_READ_IOMMU1    0x40
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_IO_WRITE_PART0 EVENT_OPTION_MASK0=0x01,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_IO_WRITE_PART0     0x20
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_IO_WRITE_PART1 EVENT_OPTION_MASK0=0x02,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_IO_WRITE_PART1     0x20
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_IO_WRITE_PART2 EVENT_OPTION_MASK0=0x04,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_IO_WRITE_PART2     0x20
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_IO_WRITE_PART3 EVENT_OPTION_MASK0=0x08,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_IO_WRITE_PART3     0x20
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_IO_WRITE_PART4 EVENT_OPTION_MASK0=0x10,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_IO_WRITE_PART4     0x20
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_IO_WRITE_PART5 EVENT_OPTION_MASK0=0x20,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_IO_WRITE_PART5     0x20
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_IO_WRITE_PART6 EVENT_OPTION_MASK0=0x40,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_IO_WRITE_PART6     0x20
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_IO_WRITE_PART7 EVENT_OPTION_MASK0=0x80,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_IO_WRITE_PART7     0x20
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_IO_WRITE_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_IO_WRITE_IOMMU0    0x20
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_IO_WRITE_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_IO_WRITE_IOMMU1    0x20
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_IO_READ_PART0 EVENT_OPTION_MASK0=0x01,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_IO_READ_PART0      0x80
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_IO_READ_PART1 EVENT_OPTION_MASK0=0x02,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_IO_READ_PART1      0x80
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_IO_READ_PART2 EVENT_OPTION_MASK0=0x04,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_IO_READ_PART2      0x80
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_IO_READ_PART3 EVENT_OPTION_MASK0=0x08,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_IO_READ_PART3      0x80
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_IO_READ_PART4 EVENT_OPTION_MASK0=0x10,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_IO_READ_PART4      0x80
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_IO_READ_PART5 EVENT_OPTION_MASK0=0x20,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_IO_READ_PART5      0x80
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_IO_READ_PART6 EVENT_OPTION_MASK0=0x40,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_IO_READ_PART6      0x80
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_IO_READ_PART7 EVENT_OPTION_MASK0=0x80,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_IO_READ_PART7      0x80
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_IO_READ_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_IO_READ_IOMMU0     0x80
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_IO_READ_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_IO_READ_IOMMU1     0x80
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_MEM_WRITE_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_MEM_WRITE_IOMMU0   0x01
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_MEM_WRITE_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_MEM_WRITE_IOMMU1   0x01
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_MEM_READ_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_MEM_READ_IOMMU0    0x04
DEFAULT_OPTIONS_TXN_REQ_BY_CPU_MEM_READ_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_BY_CPU_MEM_READ_IOMMU1    0x04

EVENT_TXN_REQ_OF_CPU                    0x84 TCBOX
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_PEER_WRITE_PART0 EVENT_OPTION_MASK0=0x01,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_PEER_WRITE_PART0   0x02
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_PEER_WRITE_PART1 EVENT_OPTION_MASK0=0x02,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_PEER_WRITE_PART1   0x02
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_PEER_WRITE_PART2 EVENT_OPTION_MASK0=0x04,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_PEER_WRITE_PART2   0x02
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_PEER_WRITE_PART3 EVENT_OPTION_MASK0=0x08,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_PEER_WRITE_PART3   0x02
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_PEER_WRITE_PART4 EVENT_OPTION_MASK0=0x10,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_PEER_WRITE_PART4   0x02
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_PEER_WRITE_PART5 EVENT_OPTION_MASK0=0x20,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_PEER_WRITE_PART5   0x02
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_PEER_WRITE_PART6 EVENT_OPTION_MASK0=0x40,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_PEER_WRITE_PART6   0x02
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_PEER_WRITE_PART7 EVENT_OPTION_MASK0=0x80,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_PEER_WRITE_PART7   0x02
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_PEER_WRITE_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_PEER_WRITE_IOMMU0  0x02
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_PEER_WRITE_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_PEER_WRITE_IOMMU1  0x02
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_PEER_READ_PART0 EVENT_OPTION_MASK0=0x01,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_PEER_READ_PART0    0x08
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_PEER_READ_PART1 EVENT_OPTION_MASK0=0x02,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_PEER_READ_PART1    0x08
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_PEER_READ_PART2 EVENT_OPTION_MASK0=0x04,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_PEER_READ_PART2    0x08
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_PEER_READ_PART3 EVENT_OPTION_MASK0=0x08,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_PEER_READ_PART3    0x08
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_PEER_READ_PART4 EVENT_OPTION_MASK0=0x10,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_PEER_READ_PART4    0x08
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_PEER_READ_PART5 EVENT_OPTION_MASK0=0x20,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_PEER_READ_PART5    0x08
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_PEER_READ_PART6 EVENT_OPTION_MASK0=0x40,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_PEER_READ_PART6    0x08
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_PEER_READ_PART7 EVENT_OPTION_MASK0=0x80,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_PEER_READ_PART7    0x08
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_PEER_READ_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_PEER_READ_IOMMU0   0x08
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_PEER_READ_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_PEER_READ_IOMMU1   0x08
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_ATOMIC_PART0 EVENT_OPTION_MASK0=0x01,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_ATOMIC_PART0       0x10
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_ATOMIC_PART1 EVENT_OPTION_MASK0=0x02,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_ATOMIC_PART1       0x10
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_ATOMIC_PART2 EVENT_OPTION_MASK0=0x04,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_ATOMIC_PART2       0x10
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_ATOMIC_PART3 EVENT_OPTION_MASK0=0x08,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_ATOMIC_PART3       0x10
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_ATOMIC_PART4 EVENT_OPTION_MASK0=0x10,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_ATOMIC_PART4       0x10
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_ATOMIC_PART5 EVENT_OPTION_MASK0=0x20,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_ATOMIC_PART5       0x10
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_ATOMIC_PART6 EVENT_OPTION_MASK0=0x40,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_ATOMIC_PART6       0x10
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_ATOMIC_PART7 EVENT_OPTION_MASK0=0x80,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_ATOMIC_PART7       0x10
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_ATOMIC_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_ATOMIC_IOMMU0      0x1
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_ATOMIC_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_ATOMIC_IOMMU1      0x10
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_MSG_PART0 EVENT_OPTION_MASK0=0x01,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_MSG_PART0          0x40
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_MSG_PART1 EVENT_OPTION_MASK0=0x02,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_MSG_PART1          0x40
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_MSG_PART2 EVENT_OPTION_MASK0=0x04,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_MSG_PART2          0x40
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_MSG_PART3 EVENT_OPTION_MASK0=0x08,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_MSG_PART3          0x40
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_MSG_PART4 EVENT_OPTION_MASK0=0x10,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_MSG_PART4          0x40
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_MSG_PART5 EVENT_OPTION_MASK0=0x20,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_MSG_PART5          0x40
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_MSG_PART6 EVENT_OPTION_MASK0=0x40,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_MSG_PART6          0x40
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_MSG_PART7 EVENT_OPTION_MASK0=0x80,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_MSG_PART7          0x40
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_MSG_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_MSG_IOMMU0         0x40
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_MSG_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_MSG_IOMMU1         0x40
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_MEM_WRITE_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_MEM_WRITE_IOMMU0   0x01
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_MEM_WRITE_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_MEM_WRITE_IOMMU1   0x01
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_MEM_READ_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_MEM_READ_IOMMU0    0x04
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_MEM_READ_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_MEM_READ_IOMMU1    0x04
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_CPMD_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_CPMD_IOMMU0        0x80
DEFAULT_OPTIONS_TXN_REQ_OF_CPU_CPMD_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_TXN_REQ_OF_CPU_CPMD_IOMMU1        0x80

EVENT_DATA_REQ_OF_CPU                                   0x83 TCBOX0C0|TCBOX0C1|TCBOX1C0|TCBOX1C1|TCBOX2C0|TCBOX2C1|TCBOX3C0|TCBOX3C1|TCBOX4C0|TCBOX4C1|TCBOX5C0|TCBOX5C1
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_PEER_WRITE_PART0 EVENT_OPTION_MASK0=0x01,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_PEER_WRITE_PART0   0x02
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_PEER_WRITE_PART1 EVENT_OPTION_MASK0=0x02,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_PEER_WRITE_PART1   0x02
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_PEER_WRITE_PART2 EVENT_OPTION_MASK0=0x04,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_PEER_WRITE_PART2   0x02
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_PEER_WRITE_PART3 EVENT_OPTION_MASK0=0x08,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_PEER_WRITE_PART3   0x02
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_PEER_WRITE_PART4 EVENT_OPTION_MASK0=0x10,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_PEER_WRITE_PART4   0x02
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_PEER_WRITE_PART5 EVENT_OPTION_MASK0=0x20,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_PEER_WRITE_PART5   0x02
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_PEER_WRITE_PART6 EVENT_OPTION_MASK0=0x40,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_PEER_WRITE_PART6   0x02
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_PEER_WRITE_PART7 EVENT_OPTION_MASK0=0x80,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_PEER_WRITE_PART7   0x02
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_PEER_WRITE_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_PEER_WRITE_IOMMU0  0x02
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_PEER_WRITE_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_PEER_WRITE_IOMMU1  0x02
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_PEER_READ_PART0 EVENT_OPTION_MASK0=0x01,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_PEER_READ_PART0    0x08
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_PEER_READ_PART1 EVENT_OPTION_MASK0=0x02,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_PEER_READ_PART1    0x08
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_PEER_READ_PART2 EVENT_OPTION_MASK0=0x04,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_PEER_READ_PART2    0x08
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_PEER_READ_PART3 EVENT_OPTION_MASK0=0x08,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_PEER_READ_PART3    0x08
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_PEER_READ_PART4 EVENT_OPTION_MASK0=0x10,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_PEER_READ_PART4    0x08
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_PEER_READ_PART5 EVENT_OPTION_MASK0=0x20,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_PEER_READ_PART5    0x08
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_PEER_READ_PART6 EVENT_OPTION_MASK0=0x40,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_PEER_READ_PART6    0x08
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_PEER_READ_PART7 EVENT_OPTION_MASK0=0x80,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_PEER_READ_PART7    0x08
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_PEER_READ_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_PEER_READ_IOMMU0   0x08
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_PEER_READ_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_PEER_READ_IOMMU1   0x08
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_ATOMIC_PART0 EVENT_OPTION_MASK0=0x01,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_ATOMIC_PART0       0x10
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_ATOMIC_PART1 EVENT_OPTION_MASK0=0x02,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_ATOMIC_PART1       0x10
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_ATOMIC_PART2 EVENT_OPTION_MASK0=0x04,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_ATOMIC_PART2       0x10
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_ATOMIC_PART3 EVENT_OPTION_MASK0=0x08,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_ATOMIC_PART3       0x10
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_ATOMIC_PART4 EVENT_OPTION_MASK0=0x10,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_ATOMIC_PART4       0x10
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_ATOMIC_PART5 EVENT_OPTION_MASK0=0x20,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_ATOMIC_PART5       0x10
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_ATOMIC_PART6 EVENT_OPTION_MASK0=0x40,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_ATOMIC_PART6       0x10
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_ATOMIC_PART7 EVENT_OPTION_MASK0=0x80,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_ATOMIC_PART7       0x10
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_ATOMIC_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_ATOMIC_IOMMU0      0x1
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_ATOMIC_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_ATOMIC_IOMMU1      0x10
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_MSG_PART0 EVENT_OPTION_MASK0=0x01,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_MSG_PART0          0x40
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_MSG_PART1 EVENT_OPTION_MASK0=0x02,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_MSG_PART1          0x40
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_MSG_PART2 EVENT_OPTION_MASK0=0x04,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_MSG_PART2          0x40
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_MSG_PART3 EVENT_OPTION_MASK0=0x08,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_MSG_PART3          0x40
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_MSG_PART4 EVENT_OPTION_MASK0=0x10,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_MSG_PART4          0x40
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_MSG_PART5 EVENT_OPTION_MASK0=0x20,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_MSG_PART5          0x40
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_MSG_PART6 EVENT_OPTION_MASK0=0x40,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_MSG_PART6          0x40
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_MSG_PART7 EVENT_OPTION_MASK0=0x80,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_MSG_PART7          0x40
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_MSG_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_MSG_IOMMU0         0x40
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_MSG_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_MSG_IOMMU1         0x40
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_MEM_WRITE_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_MEM_WRITE_IOMMU0   0x01
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_MEM_WRITE_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_MEM_WRITE_IOMMU1   0x01
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_MEM_READ_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_MEM_READ_IOMMU0    0x04
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_MEM_READ_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_MEM_READ_IOMMU1    0x04
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_CPMD_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_CPMD_IOMMU0        0x80
DEFAULT_OPTIONS_DATA_REQ_OF_CPU_CPMD_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_OF_CPU_CPMD_IOMMU1        0x80


EVENT_DATA_REQ_BY_CPU                                   0xC0 TCBOX0C2|TCBOX0C2|TCBOX1C2|TCBOX1C3|TCBOX2C2|TCBOX2C3|TCBOX3C2|TCBOX3C3|TCBOX4C2|TCBOX4C3|TCBOX5C2|TCBOX5C3
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_PEER_WRITE_PART0 EVENT_OPTION_MASK0=0x01,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_PEER_WRITE_PART0   0x02
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_PEER_WRITE_PART1 EVENT_OPTION_MASK0=0x02,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_PEER_WRITE_PART1   0x02
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_PEER_WRITE_PART2 EVENT_OPTION_MASK0=0x04,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_PEER_WRITE_PART2   0x02
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_PEER_WRITE_PART3 EVENT_OPTION_MASK0=0x08,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_PEER_WRITE_PART3   0x02
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_PEER_WRITE_PART4 EVENT_OPTION_MASK0=0x10,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_PEER_WRITE_PART4   0x02
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_PEER_WRITE_PART5 EVENT_OPTION_MASK0=0x20,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_PEER_WRITE_PART5   0x02
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_PEER_WRITE_PART6 EVENT_OPTION_MASK0=0x40,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_PEER_WRITE_PART6   0x02
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_PEER_WRITE_PART7 EVENT_OPTION_MASK0=0x80,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_PEER_WRITE_PART7   0x02
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_PEER_WRITE_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_PEER_WRITE_IOMMU0  0x02
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_PEER_WRITE_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_PEER_WRITE_IOMMU1  0x02
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_PEER_READ_PART0 EVENT_OPTION_MASK0=0x01,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_PEER_READ_PART0    0x08
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_PEER_READ_PART1 EVENT_OPTION_MASK0=0x02,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_PEER_READ_PART1    0x08
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_PEER_READ_PART2 EVENT_OPTION_MASK0=0x04,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_PEER_READ_PART2    0x08
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_PEER_READ_PART3 EVENT_OPTION_MASK0=0x08,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_PEER_READ_PART3    0x08
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_PEER_READ_PART4 EVENT_OPTION_MASK0=0x10,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_PEER_READ_PART4    0x08
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_PEER_READ_PART5 EVENT_OPTION_MASK0=0x20,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_PEER_READ_PART5    0x08
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_PEER_READ_PART6 EVENT_OPTION_MASK0=0x40,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_PEER_READ_PART6    0x08
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_PEER_READ_PART7 EVENT_OPTION_MASK0=0x80,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_PEER_READ_PART7    0x08
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_PEER_READ_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_PEER_READ_IOMMU0   0x08
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_PEER_READ_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_PEER_READ_IOMMU1   0x08
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_CFG_WRITE_PART0 EVENT_OPTION_MASK0=0x01,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_CFG_WRITE_PART0    0x10
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_CFG_WRITE_PART1 EVENT_OPTION_MASK0=0x02,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_CFG_WRITE_PART1    0x10
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_CFG_WRITE_PART2 EVENT_OPTION_MASK0=0x04,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_CFG_WRITE_PART2    0x10
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_CFG_WRITE_PART3 EVENT_OPTION_MASK0=0x08,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_CFG_WRITE_PART3    0x10
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_CFG_WRITE_PART4 EVENT_OPTION_MASK0=0x10,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_CFG_WRITE_PART4    0x10
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_CFG_WRITE_PART5 EVENT_OPTION_MASK0=0x20,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_CFG_WRITE_PART5    0x10
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_CFG_WRITE_PART6 EVENT_OPTION_MASK0=0x40,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_CFG_WRITE_PART6    0x10
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_CFG_WRITE_PART7 EVENT_OPTION_MASK0=0x80,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_CFG_WRITE_PART7    0x10
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_CFG_WRITE_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_CFG_WRITE_IOMMU0   0x10
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_CFG_WRITE_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_CFG_WRITE_IOMMU1   0x10
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_CFG_READ_PART0 EVENT_OPTION_MASK0=0x01,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_CFG_READ_PART0     0x40
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_CFG_READ_PART1 EVENT_OPTION_MASK0=0x02,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_CFG_READ_PART1     0x40
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_CFG_READ_PART2 EVENT_OPTION_MASK0=0x04,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_CFG_READ_PART2     0x40
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_CFG_READ_PART3 EVENT_OPTION_MASK0=0x08,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_CFG_READ_PART3     0x40
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_CFG_READ_PART4 EVENT_OPTION_MASK0=0x10,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_CFG_READ_PART4     0x40
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_CFG_READ_PART5 EVENT_OPTION_MASK0=0x20,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_CFG_READ_PART5     0x40
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_CFG_READ_PART6 EVENT_OPTION_MASK0=0x40,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_CFG_READ_PART6     0x40
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_CFG_READ_PART7 EVENT_OPTION_MASK0=0x80,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_CFG_READ_PART7     0x40
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_CFG_READ_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_CFG_READ_IOMMU0    0x40
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_CFG_READ_IOMMU0 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_CFG_READ_IOMMU1    0x40
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_IO_WRITE_PART0 EVENT_OPTION_MASK0=0x01,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_IO_WRITE_PART0     0x20
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_IO_WRITE_PART1 EVENT_OPTION_MASK0=0x02,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_IO_WRITE_PART1     0x20
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_IO_WRITE_PART2 EVENT_OPTION_MASK0=0x04,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_IO_WRITE_PART2     0x20
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_IO_WRITE_PART3 EVENT_OPTION_MASK0=0x08,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_IO_WRITE_PART3     0x20
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_IO_WRITE_PART4 EVENT_OPTION_MASK0=0x10,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_IO_WRITE_PART4     0x20
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_IO_WRITE_PART5 EVENT_OPTION_MASK0=0x20,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_IO_WRITE_PART5     0x20
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_IO_WRITE_PART6 EVENT_OPTION_MASK0=0x40,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_IO_WRITE_PART6     0x20
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_IO_WRITE_PART7 EVENT_OPTION_MASK0=0x80,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_IO_WRITE_PART7     0x20
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_IO_WRITE_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_IO_WRITE_IOMMU0    0x20
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_IO_WRITE_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_IO_WRITE_IOMMU1    0x20
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_IO_READ_PART0 EVENT_OPTION_MASK0=0x01,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_IO_READ_PART0      0x80
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_IO_READ_PART1 EVENT_OPTION_MASK0=0x02,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_IO_READ_PART1      0x80
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_IO_READ_PART2 EVENT_OPTION_MASK0=0x04,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_IO_READ_PART2      0x80
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_IO_READ_PART3 EVENT_OPTION_MASK0=0x08,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_IO_READ_PART3      0x80
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_IO_READ_PART4 EVENT_OPTION_MASK0=0x10,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_IO_READ_PART4      0x80
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_IO_READ_PART5 EVENT_OPTION_MASK0=0x20,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_IO_READ_PART5      0x80
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_IO_READ_PART6 EVENT_OPTION_MASK0=0x40,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_IO_READ_PART6      0x80
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_IO_READ_PART7 EVENT_OPTION_MASK0=0x80,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_IO_READ_PART7      0x80
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_IO_READ_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_IO_READ_IOMMU0     0x80
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_IO_READ_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_IO_READ_IOMMU1     0x80
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_MEM_WRITE_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_MEM_WRITE_IOMMU0   0x01
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_MEM_WRITE_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_MEM_WRITE_IOMMU1   0x01
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_MEM_READ_IOMMU0 EVENT_OPTION_MASK0=0x100,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_MEM_READ_IOMMU0    0x04
DEFAULT_OPTIONS_DATA_REQ_BY_CPU_MEM_READ_IOMMU1 EVENT_OPTION_MASK0=0x200,EVENT_OPTION_MASK1=0x07
UMASK_DATA_REQ_BY_CPU_MEM_READ_IOMMU1    0x04
