SHORT L2 cache miss rate/ratio

EVENTSET
PMC0  INSTRUCTIONS_RETIRED
PMC1  L2_REQUESTS_ALL
PMC2  L2_MISSES_ALL
PMC3  L2_FILL_ALL

METRICS
Runtime (RDTSC) [s] time
L2 request rate   (PMC1+PMC3)/PMC0
L2 miss rate   PMC2/PMC0
L2 miss ratio   PMC2/(PMC1+PMC3)

LONG
Formulas:
L2 request rate = (L2_REQUESTS_ALL+L2_FILL_ALL)/INSTRUCTIONS_RETIRED
L2 miss rate  = L2_MISSES_ALL/INSTRUCTIONS_RETIRED
L2 miss ratio = L2_MISSES_ALL/(L2_REQUESTS_ALL+L2_FILL_ALL)
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This group measures the locality of your data accesses with regard to the
L2 cache. L2 request rate tells you how data intensive your code is
or how many data accesses you have on average per instruction.
The L2 miss rate gives a measure how often it was necessary to get
cache lines from memory. And finally L2 miss ratio tells you how many of your
memory references required a cache line to be loaded from a higher level.
While the data cache miss rate might be given by your algorithm you should
try to get data cache miss ratio as low as possible by increasing your cache reuse.
This group was taken from the whitepaper -Basic Performance Measurements for AMD Athlon 64,
AMD Opteron and AMD Phenom Processors- from Paul J. Drongowski.


