SHORT  L3 cache bandwidth in MBytes/s

EVENTSET
FIXC0 INSTR_RETIRED_ANY
FIXC1 CPU_CLK_UNHALTED_CORE
FIXC2 CPU_CLK_UNHALTED_REF
FIXC3 TOPDOWN_SLOTS
PMC0  L2_LINES_IN_ALL
PMC1  L2_TRANS_L2_WB
PMC2  L2_LINES_OUT_SILENT
PMC3  L2_LINES_OUT_NON_SILENT 

METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] FIXC1*inverseClock
Clock [MHz]  1.E-06*(FIXC1/FIXC2)/inverseClock
CPI  FIXC1/FIXC0
L3 load bandwidth [MBytes/s]  1.0E-06*PMC0*64.0/time
L3 load data volume [GBytes]  1.0E-09*PMC0*64.0
L3 evict bandwidth [MBytes/s]  1.0E-06*PMC3*64.0/time
L3 evict data volume [GBytes]  1.0E-09*PMC3*64.0
L3|MEM evict bandwidth [MBytes/s]  1.0E-06*PMC1*64.0/time
L3|MEM evict data volume [GBytes]  1.0E-09*PMC1*64.0
Dropped CLs bandwidth [MBytes/s] 1.0E-6*PMC2*64.0/time
Dropped CLs data volume [GBytes] 1.0E-9*PMC2*64.0
L3 bandwidth [MBytes/s] 1.0E-06*(PMC0+PMC1)*64.0/time
L3 data volume [GBytes] 1.0E-09*(PMC0+PMC1)*64.0

LONG
Formulas:
L3 load bandwidth [MBytes/s] = 1.0E-06*L2_LINES_IN_ALL*64.0/time
L3 load data volume [GBytes] = 1.0E-09*L2_LINES_IN_ALL*64.0
L3 evict bandwidth [MBytes/s] = 1.0E-06*L2_LINES_OUT_NON_SILENT*64.0/time
L3 evict data volume [GBytes] = 1.0E-09*L2_LINES_OUT_NON_SILENT*64.0
L3|MEM evict bandwidth [MBytes/s] = 1.0E-06*L2_TRANS_L2_WB*64.0/time
L3|MEM evict data volume [GBytes] = 1.0E-09*L2_TRANS_L2_WB*64.0
Dropped CLs bandwidth [MBytes/s] = 1.0E-6*L2_LINES_OUT_SILENT*64.0/time
Dropped CLs data volume [GBytes] = 1.0E-9*L2_LINES_OUT_SILENT*64.0
L3 bandwidth [MBytes/s] = 1.0E-06*(L2_LINES_IN_ALL+L2_TRANS_L2_WB)*64/time
L3 data volume [GBytes] = 1.0E-09*(L2_LINES_IN_ALL+L2_TRANS_L2_WB)*64
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Profiling group to measure L3 cache bandwidth. The bandwidth is computed by the
number of cache line allocated in the L2 and the number of modified cache lines
evicted from the L2. This group also output data volume transferred between the
L3 and measured cores L2 caches. Note that this bandwidth also includes data
transfers due to a write allocate load on a store miss in L2.

