\page kabini AMD® Kabini

# Available performance monitors for the AMD® Kabini microarchitecture

- \ref KAB_PMC "General-purpose counters"
- \ref KAB_CPMC "L2 cache general-purpose counters"
- \ref KAB_UPMC "Northbridge general-purpose counters"

\anchor KAB_PMC

## General-purpose counters

The AMD® Kabini microarchitecture provides 4 general-purpose counters consisting of a config and a counter register.

### Counter and events

Counter name | Event name
--- | ---
PMC0 | *
PMC1 | *
PMC2 | *
PMC3 | *

### Available Options

Option | Argument | Description | Comment
--- | --- | --- | ---
edgedetect | N | Set bit 18 in config register |
kernel | N | Set bit 17 in config register |
threshold | 8 bit hex value | Set bits 24-31 in config register | The value for threshold can range between 0x0 and 0x3
invert | N | Set bit 23 in config register |

# Counters available for one hardware thread per shared L2 cache

\anchor KAB_CPMC

## L2 general-purpose counters

The AMD® Kabini microarchitecture provides 4 general-purpose counters for measuring L2 cache events. They consist of a config and a counter register.

### Counter and events

Counter name | Event name
--- | ---
CPMC0 | *
CPMC1 | *
CPMC2 | *
CPMC3 | *

### Available Options

Option | Argument | Description | Comment
--- | --- | --- | ---
threshold | 8 bit hex value | Set bits 24-31 in config register | The value for threshold can range between 0x0 and 0x3
invert | N | Set bit 23 in config register |
tid | 4 bit hex value | Set bits 56-59 in config register | If bit equals 0, the events of the thread are counted. See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 16h Processors for details.
nid | 4 bit hex value | Set bits 48-51 in config register | If bit equals 0, the events of the thread are counted. See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 16h Processors for details.

# Counters available for one hardware thread per socket

\anchor KAB_UPMC

## Northbridge general-purpose counters

The AMD® Kabini microarchitecture provides 4 general-purpose counters for the Northbridge consisting of a config and a counter register.

### Counter and events

Counter name | Event name
--- | ---
UPMC0 | *
UPMC1 | *
UPMC2 | *
UPMC3 | *