SHORT Main memory bandwidth in MBytes/s (channels 0-3)

EVENTSET
FIXC1 ACTUAL_CPU_CLOCK
FIXC2 MAX_CPU_CLOCK
PMC0  RETIRED_INSTRUCTIONS
PMC1  CPU_CLOCKS_UNHALTED
DFC0  DRAM_CHANNEL_0
DFC1  DRAM_CHANNEL_1
DFC2  DRAM_CHANNEL_2
DFC3  DRAM_CHANNEL_3

METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] FIXC1*inverseClock
Clock [MHz]  1.E-06*(FIXC1/FIXC2)/inverseClock
CPI  PMC1/PMC0
Memory bandwidth (channels 0-3) [MBytes/s] 1.0E-06*(DFC0+DFC1+DFC2+DFC3)*64.0/time
Memory data volume (channels 0-3) [GBytes] 1.0E-09*(DFC0+DFC1+DFC2+DFC3)*64.0

LONG
Formulas:
Memory bandwidth (channels 0-3) [MBytes/s] = 1.0E-06*(SUM(DRAM_CHANNEL_*))*64.0/time
Memory data volume (channels 0-3) [GBytes] = 1.0E-09*(SUM(DRAM_CHANNEL_*))*64.0
-
Profiling group to measure memory bandwidth drawn by all cores of a socket.
Since this group is based on Uncore events it is only possible to measure on a
per socket base. Please note that the metric is "approximate" and only available in NPS1 mode.
AMD Zen3 systems provide 8 memory channels, each represented by a distinct event. Since there are
only 4 counter registers available, you have to measure the groups MEM1 and MEM2 for the whole
picture.
