\page zen4 AMD® Zen4 (Ryzen, Epyc)

# Available performance monitors for the AMD® Zen4 microarchitecture

- \ref ZEN4_FIXED "Fixed-purpose counters"
- \ref ZEN4_PMC "General-purpose counters"
- \ref ZEN4_POWER_CORE "CPU core energy counters"
- \ref ZEN4_CPMC "L3 cache general-purpose counters"
- \ref ZEN4_POWER_SOCKET "Socket energy counters"
- \ref ZEN4_DATA_FABRIC "Data Fabric counters"
- \ref ZEN4_UMC "Unified memory controller counters"

\anchor ZEN4_FIXED

## Fixed-purpose counters

The AMD® Zen4 microarchitecture provides three fixed-purpose counters for retired instructions, actual CPU core clock (MPerf: This register increments in proportion to the actual number of core clocks cycles while the core is in C0) and maximum CPU core clock (APerf: Incremented by hardware at the P0 frequency while the core is in C0).

### Counter and events

Counter name | Event name
--- | ---
FIXC0 | INST_RETIRED_ANY (removed due to bad counts)
FIXC1 | ACTUAL_CPU_CLOCK or APERF
FIXC2 | MAX_CPU_CLOCK or MPERF

\anchor ZEN4_PMC

## General-purpose counters

The AMD® Zen4 microarchitecture provides 6 general-purpose counters consisting of a config and a counter register.

### Counter and events

Counter name | Event name
--- | ---
PMC0 | *
PMC1 | *
PMC2 | *
PMC3 | *
PMC4 | *
PMC5 | *

### Available Options

Option | Argument | Description | Comment
--- | --- | --- | ---
edgedetect | N | Set bit 18 in config register |
kernel | N | Set bit 17 in config register |
threshold | 7 bit hex value | Set bits 24-31 in config register | The value for threshold can range between 0x0 and 0x7F
invert | N | Set bit 23 in config register |

# Counters available for one hardware thread per CPU core

\anchor ZEN4_POWER_CORE

## Power counters

The AMD® Zen4 microarchitecture provides measurements of the current power consumption through the RAPL interface.

### Counter and events

Counter name | Event name
--- | ---
PWR0 | RAPL_CORE_ENERGY

There are more energy counters but only one for each L3 segment (aka CCD) (\ref ZEN4_POWER_SOCKET)

# Counters available for one hardware thread per shared L3 cache

\anchor ZEN4_CPMC

## L3 general-purpose counters

The AMD® Zen4 microarchitecture provides 6 general-purpose counters for measuring L3 cache events. They consist of a config and a counter register.

### Counter and events

Counter name | Event name
--- | ---
CPMC0 | *
CPMC1 | *
CPMC2 | *
CPMC3 | *
CPMC4 | *
CPMC5 | *

### Available Options

Option | Argument | Description | Comment
--- | --- | --- | ---
tid | 8 bit hex value | Set bits 56-63 in config register | Define which CPU thread should be counted. Bits: 0 = Core0-Thread0, 1 = Core0-Thread1, 2 = Core1-Thread0, 3 = Core1-Thread1, ... Default are all threads
cid | 3 bit hex value | Set bits 42-45 in config register | Selects which core should be counted. If not specified, the all-cores flag (bit 47) is set
slice | 4 bit hex value | Set bits 48-51 in config register | Selects which L3 slice should be counted. If not specified, the all-slices flag (bit 46) is set

# Counters available for one hardware thread per socket

\anchor ZEN4_POWER_SOCKET

## Power counters

The AMD® Zen4 microarchitecture provides measurements of the current power consumption through the RAPL interface.

### Counter and events

Counter name | Event name
--- | ---
PWR1 | RAPL_DRAM_ENERGY

There are more energy counters for each CPU core (\ref ZEN4_POWER_CORE)

\anchor ZEN4_DATA_FABRIC

## Data Fabric counters

The AMD® Zen4 microarchitecture provides additional Uncore counters for the so-called Data Fabric.

### Counter and events

Counter name | Event name
--- | ---
DFC0 | *
DFC1 | *
DFC2 | *
DFC3 | *
DFC4 | *
DFC5 | *
DFC5 | *
DFC6 | *
DFC7 | *
DFC8 | *
DFC9 | *
DFC10 | *
DFC11 | *
DFC12 | *
DFC13 | *
DFC14 | *
DFC15 | *

\anchor ZEN4_UMC

## Unified memory controller counters

The AMD® Zen4 microarchitecture provides additional Uncore counters at the unified memory controllers (UMC). There are up to 12 memory controllers with up to 5 counters each as the system provides 64 registers in total for all. The exact configuration is system dependent and read at runtime.

### Counter and events

Counter name | Event name
--- | ---
UMC<0-11>C0 | *
UMC<0-11>C1 | *
UMC<0-11>C2 | *
UMC<0-11>C3 | *
UMC<0-11>C4 | *