// SPDX-License-Identifier: BSD-3-Clause
/* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */

#include <sys/mman.h>
#include <err.h>
#include <fcntl.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>

#include <debugcc.h>

static struct gcc_mux gcc = {
	.mux = {
		.phys =	0x100000,
		.size = 0x1f4200,

		.measure = measure_gcc,

		.enable_reg = 0x62004,
		.enable_mask = BIT(0),

		.mux_reg = 0x62024,
		.mux_mask = 0x3ff,

		.div_reg = 0x62000,
		.div_mask = 0xf,
		.div_val = 2,
	},

	.xo_div4_reg = 0x62008,
	.debug_ctl_reg = 0x62048,
	.debug_status_reg = 0x6204c,
};

static struct debug_mux av1e_cc = {
	.phys = 0x15220000,
	.size = 0x14000,
	.block_name = "av1e",

	.measure = measure_leaf,
	.parent = &gcc.mux,
	.parent_mux_val = 0xb4,

	.enable_reg = 0x600C,
	.enable_mask = BIT(0),

	.mux_reg = 0x6004,
	.mux_mask = 0x3f,

	.div_reg = 0x6008,
	.div_mask = 0xf,
	.div_val = 3,
};

static struct debug_mux cam_cc = {
	.phys = 0xade0000,
	.size = 0x20000,
	.block_name = "cam",

	.measure = measure_leaf,
	.parent = &gcc.mux,
	.parent_mux_val = 0xa2,

	.enable_reg = 0x14008,
	.enable_mask = BIT(0),

	.mux_reg = 0x16000,
	.mux_mask = 0xff,

	.div_reg = 0x14004,
	.div_mask = 0xf,
	.div_val = 4,
};

static struct debug_mux disp_cc = {
	.phys = 0xaf00000,
	.size = 0x20000,
	.block_name = "disp",

	.measure = measure_leaf,
	.parent = &gcc.mux,
	.parent_mux_val = 0xa7,

	.enable_reg = 0xd004,
	.enable_mask = BIT(0),

	.mux_reg = 0x11000,
	.mux_mask = 0x1ff,

	.div_reg = 0xd000,
	.div_mask = 0xf,
	.div_val = 4,
};

static struct debug_mux gpu_cc = {
	.phys = 0x3d90000,
	.size = 0xa000,
	.block_name = "gpu",

	.measure = measure_leaf,
	.parent = &gcc.mux,
	.parent_mux_val = 0x25b,

	.enable_reg = 0x9274,
	.enable_mask = BIT(0),

	.mux_reg = 0x9564,
	.mux_mask = 0xff,

	.div_reg = 0x9270,
	.div_mask = 0xf,
	.div_val = 2,
};

static struct debug_mux video_cc = {
	.phys = 0xaaf0000,
	.size = 0x10000,
	.block_name = "video",

	.measure = measure_leaf,
	.parent = &gcc.mux,
	.parent_mux_val = 0xb0,

	.enable_reg = 0x80fc,
	.enable_mask = BIT(0),

	.mux_reg = 0x9a4c,
	.mux_mask = 0x3f,

	.div_reg = 0x80f8,
	.div_mask = 0xf,
	.div_val = 3,
};

static struct measure_clk hamoa_clocks[] = {
	/* GCC entries */
	{ "gcc_aggre_noc_usb_north_axi_clk", &gcc.mux, 0x6b },
	{ "gcc_aggre_noc_usb_south_axi_clk", &gcc.mux, 0x6a },
	{ "gcc_aggre_ufs_phy_axi_clk", &gcc.mux, 0x63 },
	{ "gcc_aggre_usb2_prim_axi_clk", &gcc.mux, 0x62 },
	{ "gcc_aggre_usb3_mp_axi_clk", &gcc.mux, 0x61 },
	{ "gcc_aggre_usb3_prim_axi_clk", &gcc.mux, 0x5b },
	{ "gcc_aggre_usb3_sec_axi_clk", &gcc.mux, 0x5d },
	{ "gcc_aggre_usb3_tert_axi_clk", &gcc.mux, 0x5f },
	{ "gcc_aggre_usb4_0_axi_clk", &gcc.mux, 0x5c },
	{ "gcc_aggre_usb4_1_axi_clk", &gcc.mux, 0x5e },
	{ "gcc_aggre_usb4_2_axi_clk", &gcc.mux, 0x60 },
	{ "gcc_aggre_usb_noc_axi_clk", &gcc.mux, 0x69 },
	{ "gcc_av1e_ahb_clk", &gcc.mux, 0xb1 },
	{ "gcc_av1e_axi_clk", &gcc.mux, 0xb2 },
	{ "gcc_av1e_xo_clk", &gcc.mux, 0xb3 },
	{ "gcc_boot_rom_ahb_clk", &gcc.mux, 0x19b },
	{ "gcc_camera_ahb_clk", &gcc.mux, 0x9a },
	{ "gcc_camera_hf_axi_clk", &gcc.mux, 0x9d },
	{ "gcc_camera_sf_axi_clk", &gcc.mux, 0x9f },
	{ "gcc_camera_xo_clk", &gcc.mux, 0xa1 },
	{ "gcc_cfg_noc_pcie_anoc_ahb_clk", &gcc.mux, 0x3d },
	{ "gcc_cfg_noc_pcie_anoc_north_ahb_clk", &gcc.mux, 0x3f },
	{ "gcc_cfg_noc_pcie_anoc_south_ahb_clk", &gcc.mux, 0x41 },
	{ "gcc_cfg_noc_usb2_prim_axi_clk", &gcc.mux, 0x25 },
	{ "gcc_cfg_noc_usb3_mp_axi_clk", &gcc.mux, 0x24 },
	{ "gcc_cfg_noc_usb3_prim_axi_clk", &gcc.mux, 0x21 },
	{ "gcc_cfg_noc_usb3_sec_axi_clk", &gcc.mux, 0x22 },
	{ "gcc_cfg_noc_usb3_tert_axi_clk", &gcc.mux, 0x23 },
	{ "gcc_cfg_noc_usb_anoc_ahb_clk", &gcc.mux, 0x3e },
	{ "gcc_cfg_noc_usb_anoc_north_ahb_clk", &gcc.mux, 0x40 },
	{ "gcc_cfg_noc_usb_anoc_south_ahb_clk", &gcc.mux, 0x42 },
	{ "gcc_cnoc_pcie1_tunnel_clk", &gcc.mux, 0x39 },
	{ "gcc_cnoc_pcie2_tunnel_clk", &gcc.mux, 0x3a },
	{ "gcc_cnoc_pcie_north_sf_axi_clk", &gcc.mux, 0x19 },
	{ "gcc_cnoc_pcie_south_sf_axi_clk", &gcc.mux, 0x1a },
	{ "gcc_cnoc_pcie_tunnel_clk", &gcc.mux, 0x38 },
	{ "gcc_ddrss_gpu_axi_clk", &gcc.mux, 0x1b3 },
	{ "gcc_disp_ahb_clk", &gcc.mux, 0xa3 },
	{ "gcc_disp_hf_axi_clk", &gcc.mux, 0xa5 },
	{ "gcc_disp_xo_clk", &gcc.mux, 0xa6 },
	{ "gcc_gp1_clk", &gcc.mux, 0x1fe },
	{ "gcc_gp2_clk", &gcc.mux, 0x1ff },
	{ "gcc_gp3_clk", &gcc.mux, 0x200 },
	{ "gcc_gpu_cfg_ahb_clk", &gcc.mux, 0x258 },
	{ "gcc_gpu_gpll0_cph_clk_src", &gcc.mux, 0x25f },
	{ "gcc_gpu_gpll0_div_cph_clk_src", &gcc.mux, 0x260 },
	{ "gcc_gpu_memnoc_gfx_clk", &gcc.mux, 0x25c },
	{ "gcc_gpu_snoc_dvm_gfx_clk", &gcc.mux, 0x25e },
	{ "gcc_pcie0_phy_rchng_clk", &gcc.mux, 0xfa },
	{ "gcc_pcie1_phy_rchng_clk", &gcc.mux, 0x11f },
	{ "gcc_pcie2_phy_rchng_clk", &gcc.mux, 0x144 },
	{ "gcc_pcie_0_aux_clk", &gcc.mux, 0xf8 },
	{ "gcc_pcie_0_cfg_ahb_clk", &gcc.mux, 0xf7 },
	{ "gcc_pcie_0_mstr_axi_clk", &gcc.mux, 0xf6 },
	{ "gcc_pcie_0_pipe_clk", &gcc.mux, 0xf9 },
	{ "gcc_pcie_0_slv_axi_clk", &gcc.mux, 0xf5 },
	{ "gcc_pcie_0_slv_q2a_axi_clk", &gcc.mux, 0xf4 },
	{ "gcc_pcie_1_aux_clk", &gcc.mux, 0x11d },
	{ "gcc_pcie_1_cfg_ahb_clk", &gcc.mux, 0x11c },
	{ "gcc_pcie_1_mstr_axi_clk", &gcc.mux, 0x11b },
	{ "gcc_pcie_1_pipe_clk", &gcc.mux, 0x11e },
	{ "gcc_pcie_1_slv_axi_clk", &gcc.mux, 0x11a },
	{ "gcc_pcie_1_slv_q2a_axi_clk", &gcc.mux, 0x119 },
	{ "gcc_pcie_2_aux_clk", &gcc.mux, 0x142 },
	{ "gcc_pcie_2_cfg_ahb_clk", &gcc.mux, 0x141 },
	{ "gcc_pcie_2_mstr_axi_clk", &gcc.mux, 0x140 },
	{ "gcc_pcie_2_pipe_clk", &gcc.mux, 0x143 },
	{ "gcc_pcie_2_slv_axi_clk", &gcc.mux, 0x13f },
	{ "gcc_pcie_2_slv_q2a_axi_clk", &gcc.mux, 0x13e },
	{ "gcc_pcie_3_aux_clk", &gcc.mux, 0x205 },
	{ "gcc_pcie_3_cfg_ahb_clk", &gcc.mux, 0x204 },
	{ "gcc_pcie_3_mstr_axi_clk", &gcc.mux, 0x203 },
	{ "gcc_pcie_3_phy_aux_clk", &gcc.mux, 0x206 },
	{ "gcc_pcie_3_phy_rchng_clk", &gcc.mux, 0x208 },
	{ "gcc_pcie_3_pipe_clk", &gcc.mux, 0x207 },
	{ "gcc_pcie_3_pipediv2_clk", &gcc.mux, 0x209 },
	{ "gcc_pcie_3_slv_axi_clk", &gcc.mux, 0x202 },
	{ "gcc_pcie_3_slv_q2a_axi_clk", &gcc.mux, 0x201 },
	{ "gcc_pcie_4_aux_clk", &gcc.mux, 0x211 },
	{ "gcc_pcie_4_cfg_ahb_clk", &gcc.mux, 0x210 },
	{ "gcc_pcie_4_mstr_axi_clk", &gcc.mux, 0x20f },
	{ "gcc_pcie_4_phy_rchng_clk", &gcc.mux, 0x213 },
	{ "gcc_pcie_4_pipe_clk", &gcc.mux, 0x212 },
	{ "gcc_pcie_4_pipediv2_clk", &gcc.mux, 0x214 },
	{ "gcc_pcie_4_slv_axi_clk", &gcc.mux, 0x20e },
	{ "gcc_pcie_4_slv_q2a_axi_clk", &gcc.mux, 0x20d },
	{ "gcc_pcie_5_aux_clk", &gcc.mux, 0x21b },
	{ "gcc_pcie_5_cfg_ahb_clk", &gcc.mux, 0x21a },
	{ "gcc_pcie_5_mstr_axi_clk", &gcc.mux, 0x219 },
	{ "gcc_pcie_5_phy_rchng_clk", &gcc.mux, 0x21d },
	{ "gcc_pcie_5_pipe_clk", &gcc.mux, 0x21c },
	{ "gcc_pcie_5_pipediv2_clk", &gcc.mux, 0x21e },
	{ "gcc_pcie_5_slv_axi_clk", &gcc.mux, 0x218 },
	{ "gcc_pcie_5_slv_q2a_axi_clk", &gcc.mux, 0x217 },
	{ "gcc_pcie_6a_aux_clk", &gcc.mux, 0x231 },
	{ "gcc_pcie_6a_cfg_ahb_clk", &gcc.mux, 0x230 },
	{ "gcc_pcie_6a_mstr_axi_clk", &gcc.mux, 0x22f },
	{ "gcc_pcie_6a_phy_aux_clk", &gcc.mux, 0x232 },
	{ "gcc_pcie_6a_phy_rchng_clk", &gcc.mux, 0x234 },
	{ "gcc_pcie_6a_pipe_clk", &gcc.mux, 0x233 },
	{ "gcc_pcie_6a_pipediv2_clk", &gcc.mux, 0x235 },
	{ "gcc_pcie_6a_slv_axi_clk", &gcc.mux, 0x22e },
	{ "gcc_pcie_6a_slv_q2a_axi_clk", &gcc.mux, 0x22d },
	{ "gcc_pcie_6b_aux_clk", &gcc.mux, 0x225 },
	{ "gcc_pcie_6b_cfg_ahb_clk", &gcc.mux, 0x224 },
	{ "gcc_pcie_6b_mstr_axi_clk", &gcc.mux, 0x223 },
	{ "gcc_pcie_6b_phy_aux_clk", &gcc.mux, 0x226 },
	{ "gcc_pcie_6b_phy_rchng_clk", &gcc.mux, 0x228 },
	{ "gcc_pcie_6b_pipe_clk", &gcc.mux, 0x227 },
	{ "gcc_pcie_6b_pipediv2_clk", &gcc.mux, 0x229 },
	{ "gcc_pcie_6b_slv_axi_clk", &gcc.mux, 0x222 },
	{ "gcc_pcie_6b_slv_q2a_axi_clk", &gcc.mux, 0x221 },
	{ "gcc_pcie_rscc_ahb_clk", &gcc.mux, 0x84 },
	{ "gcc_pcie_rscc_xo_clk", &gcc.mux, 0x83 },
	{ "gcc_pdm2_clk", &gcc.mux, 0x18c },
	{ "gcc_pdm_ahb_clk", &gcc.mux, 0x18a },
	{ "gcc_pdm_xo4_clk", &gcc.mux, 0x18b },
	{ "gcc_qmip_av1e_ahb_clk", &gcc.mux, 0xb5 },
	{ "gcc_qmip_camera_nrt_ahb_clk", &gcc.mux, 0x9b },
	{ "gcc_qmip_camera_rt_ahb_clk", &gcc.mux, 0x9c },
	{ "gcc_qmip_disp_ahb_clk", &gcc.mux, 0xa4 },
	{ "gcc_qmip_gpu_ahb_clk", &gcc.mux, 0x259 },
	{ "gcc_qmip_video_cv_cpu_ahb_clk", &gcc.mux, 0xac },
	{ "gcc_qmip_video_cvp_ahb_clk", &gcc.mux, 0xa9 },
	{ "gcc_qmip_video_v_cpu_ahb_clk", &gcc.mux, 0xab },
	{ "gcc_qmip_video_vcodec_ahb_clk", &gcc.mux, 0xaa },
	{ "gcc_qupv3_wrap0_core_2x_clk", &gcc.mux, 0x163 },
	{ "gcc_qupv3_wrap0_core_clk", &gcc.mux, 0x162 },
	{ "gcc_qupv3_wrap0_qspi_s2_clk", &gcc.mux, 0x167 },
	{ "gcc_qupv3_wrap0_qspi_s3_clk", &gcc.mux, 0x169 },
	{ "gcc_qupv3_wrap0_s0_clk", &gcc.mux, 0x164 },
	{ "gcc_qupv3_wrap0_s1_clk", &gcc.mux, 0x165 },
	{ "gcc_qupv3_wrap0_s2_clk", &gcc.mux, 0x166 },
	{ "gcc_qupv3_wrap0_s3_clk", &gcc.mux, 0x168 },
	{ "gcc_qupv3_wrap0_s4_clk", &gcc.mux, 0x16a },
	{ "gcc_qupv3_wrap0_s5_clk", &gcc.mux, 0x16b },
	{ "gcc_qupv3_wrap0_s6_clk", &gcc.mux, 0x16c },
	{ "gcc_qupv3_wrap0_s7_clk", &gcc.mux, 0x16d },
	{ "gcc_qupv3_wrap1_core_2x_clk", &gcc.mux, 0x171 },
	{ "gcc_qupv3_wrap1_core_clk", &gcc.mux, 0x170 },
	{ "gcc_qupv3_wrap1_qspi_s2_clk", &gcc.mux, 0x175 },
	{ "gcc_qupv3_wrap1_qspi_s3_clk", &gcc.mux, 0x177 },
	{ "gcc_qupv3_wrap1_s0_clk", &gcc.mux, 0x172 },
	{ "gcc_qupv3_wrap1_s1_clk", &gcc.mux, 0x173 },
	{ "gcc_qupv3_wrap1_s2_clk", &gcc.mux, 0x174 },
	{ "gcc_qupv3_wrap1_s3_clk", &gcc.mux, 0x176 },
	{ "gcc_qupv3_wrap1_s4_clk", &gcc.mux, 0x178 },
	{ "gcc_qupv3_wrap1_s5_clk", &gcc.mux, 0x179 },
	{ "gcc_qupv3_wrap1_s6_clk", &gcc.mux, 0x17a },
	{ "gcc_qupv3_wrap1_s7_clk", &gcc.mux, 0x17b },
	{ "gcc_qupv3_wrap2_core_2x_clk", &gcc.mux, 0x17f },
	{ "gcc_qupv3_wrap2_core_clk", &gcc.mux, 0x17e },
	{ "gcc_qupv3_wrap2_qspi_s2_clk", &gcc.mux, 0x183 },
	{ "gcc_qupv3_wrap2_qspi_s3_clk", &gcc.mux, 0x185 },
	{ "gcc_qupv3_wrap2_s0_clk", &gcc.mux, 0x180 },
	{ "gcc_qupv3_wrap2_s1_clk", &gcc.mux, 0x181 },
	{ "gcc_qupv3_wrap2_s2_clk", &gcc.mux, 0x182 },
	{ "gcc_qupv3_wrap2_s3_clk", &gcc.mux, 0x184 },
	{ "gcc_qupv3_wrap2_s4_clk", &gcc.mux, 0x186 },
	{ "gcc_qupv3_wrap2_s5_clk", &gcc.mux, 0x187 },
	{ "gcc_qupv3_wrap2_s6_clk", &gcc.mux, 0x188 },
	{ "gcc_qupv3_wrap2_s7_clk", &gcc.mux, 0x189 },
	{ "gcc_qupv3_wrap_0_m_ahb_clk", &gcc.mux, 0x160 },
	{ "gcc_qupv3_wrap_0_s_ahb_clk", &gcc.mux, 0x161 },
	{ "gcc_qupv3_wrap_1_m_ahb_clk", &gcc.mux, 0x16e },
	{ "gcc_qupv3_wrap_1_s_ahb_clk", &gcc.mux, 0x16f },
	{ "gcc_qupv3_wrap_2_m_ahb_clk", &gcc.mux, 0x17c },
	{ "gcc_qupv3_wrap_2_s_ahb_clk", &gcc.mux, 0x17d },
	{ "gcc_sdcc2_ahb_clk", &gcc.mux, 0x15b },
	{ "gcc_sdcc2_apps_clk", &gcc.mux, 0x15a },
	{ "gcc_sdcc4_ahb_clk", &gcc.mux, 0x15e },
	{ "gcc_sdcc4_apps_clk", &gcc.mux, 0x15d },
	{ "gcc_sys_noc_usb_axi_clk", &gcc.mux, 0xf },
	{ "gcc_ufs_phy_ahb_clk", &gcc.mux, 0x23a },
	{ "gcc_ufs_phy_axi_clk", &gcc.mux, 0x239 },
	{ "gcc_ufs_phy_ice_core_clk", &gcc.mux, 0x240 },
	{ "gcc_ufs_phy_phy_aux_clk", &gcc.mux, 0x241 },
	{ "gcc_ufs_phy_rx_symbol_0_clk", &gcc.mux, 0x23c },
	{ "gcc_ufs_phy_rx_symbol_1_clk", &gcc.mux, 0x242 },
	{ "gcc_ufs_phy_tx_symbol_0_clk", &gcc.mux, 0x23b },
	{ "gcc_ufs_phy_unipro_core_clk", &gcc.mux, 0x23f },
	{ "gcc_usb20_master_clk", &gcc.mux, 0x155 },
	{ "gcc_usb20_mock_utmi_clk", &gcc.mux, 0x157 },
	{ "gcc_usb20_sleep_clk", &gcc.mux, 0x156 },
	{ "gcc_usb30_mp_master_clk", &gcc.mux, 0x14a },
	{ "gcc_usb30_mp_mock_utmi_clk", &gcc.mux, 0x14c },
	{ "gcc_usb30_mp_sleep_clk", &gcc.mux, 0x14b },
	{ "gcc_usb30_prim_master_clk", &gcc.mux, 0xd5 },
	{ "gcc_usb30_prim_mock_utmi_clk", &gcc.mux, 0xd7 },
	{ "gcc_usb30_prim_sleep_clk", &gcc.mux, 0xd6 },
	{ "gcc_usb30_sec_master_clk", &gcc.mux, 0xfd },
	{ "gcc_usb30_sec_mock_utmi_clk", &gcc.mux, 0xff },
	{ "gcc_usb30_sec_sleep_clk", &gcc.mux, 0xfe },
	{ "gcc_usb30_tert_master_clk", &gcc.mux, 0x122 },
	{ "gcc_usb30_tert_mock_utmi_clk", &gcc.mux, 0x124 },
	{ "gcc_usb30_tert_sleep_clk", &gcc.mux, 0x123 },
	{ "gcc_usb3_mp_phy_aux_clk", &gcc.mux, 0x14d },
	{ "gcc_usb3_mp_phy_com_aux_clk", &gcc.mux, 0x14e },
	{ "gcc_usb3_mp_phy_pipe_0_clk", &gcc.mux, 0x14f },
	{ "gcc_usb3_mp_phy_pipe_1_clk", &gcc.mux, 0x150 },
	{ "gcc_usb3_prim_phy_aux_clk", &gcc.mux, 0xd8 },
	{ "gcc_usb3_prim_phy_com_aux_clk", &gcc.mux, 0xd9 },
	{ "gcc_usb3_prim_phy_pipe_clk", &gcc.mux, 0xda },
	{ "gcc_usb3_sec_phy_aux_clk", &gcc.mux, 0x100 },
	{ "gcc_usb3_sec_phy_com_aux_clk", &gcc.mux, 0x101 },
	{ "gcc_usb3_sec_phy_pipe_clk", &gcc.mux, 0x102 },
	{ "gcc_usb3_tert_phy_aux_clk", &gcc.mux, 0x125 },
	{ "gcc_usb3_tert_phy_com_aux_clk", &gcc.mux, 0x126 },
	{ "gcc_usb3_tert_phy_pipe_clk", &gcc.mux, 0x127 },
	{ "gcc_usb4_0_cfg_ahb_clk", &gcc.mux, 0xed },
	{ "gcc_usb4_0_dp0_clk", &gcc.mux, 0xea },
	{ "gcc_usb4_0_dp1_clk", &gcc.mux, 0xf3 },
	{ "gcc_usb4_0_master_clk", &gcc.mux, 0xe6 },
	{ "gcc_usb4_0_phy_p2rr2p_pipe_clk", &gcc.mux, 0xf2 },
	{ "gcc_usb4_0_phy_pcie_pipe_clk", &gcc.mux, 0xe8 },
	{ "gcc_usb4_0_phy_rx0_clk", &gcc.mux, 0xee },
	{ "gcc_usb4_0_phy_rx1_clk", &gcc.mux, 0xef },
	{ "gcc_usb4_0_phy_usb_pipe_clk", &gcc.mux, 0xec },
	{ "gcc_usb4_0_sb_if_clk", &gcc.mux, 0xe7 },
	{ "gcc_usb4_0_sys_clk", &gcc.mux, 0xe9 },
	{ "gcc_usb4_0_tmu_clk", &gcc.mux, 0xeb },
	{ "gcc_usb4_1_cfg_ahb_clk", &gcc.mux, 0x112 },
	{ "gcc_usb4_1_dp0_clk", &gcc.mux, 0x10f },
	{ "gcc_usb4_1_dp1_clk", &gcc.mux, 0x118 },
	{ "gcc_usb4_1_master_clk", &gcc.mux, 0x10b },
	{ "gcc_usb4_1_phy_p2rr2p_pipe_clk", &gcc.mux, 0x117 },
	{ "gcc_usb4_1_phy_pcie_pipe_clk", &gcc.mux, 0x10d },
	{ "gcc_usb4_1_phy_rx0_clk", &gcc.mux, 0x113 },
	{ "gcc_usb4_1_phy_rx1_clk", &gcc.mux, 0x114 },
	{ "gcc_usb4_1_phy_usb_pipe_clk", &gcc.mux, 0x111 },
	{ "gcc_usb4_1_sb_if_clk", &gcc.mux, 0x10c },
	{ "gcc_usb4_1_sys_clk", &gcc.mux, 0x10e },
	{ "gcc_usb4_1_tmu_clk", &gcc.mux, 0x110 },
	{ "gcc_usb4_2_cfg_ahb_clk", &gcc.mux, 0x137 },
	{ "gcc_usb4_2_dp0_clk", &gcc.mux, 0x134 },
	{ "gcc_usb4_2_dp1_clk", &gcc.mux, 0x13d },
	{ "gcc_usb4_2_master_clk", &gcc.mux, 0x130 },
	{ "gcc_usb4_2_phy_p2rr2p_pipe_clk", &gcc.mux, 0x13c },
	{ "gcc_usb4_2_phy_pcie_pipe_clk", &gcc.mux, 0x132 },
	{ "gcc_usb4_2_phy_rx0_clk", &gcc.mux, 0x138 },
	{ "gcc_usb4_2_phy_rx1_clk", &gcc.mux, 0x139 },
	{ "gcc_usb4_2_phy_usb_pipe_clk", &gcc.mux, 0x136 },
	{ "gcc_usb4_2_sb_if_clk", &gcc.mux, 0x131 },
	{ "gcc_usb4_2_sys_clk", &gcc.mux, 0x133 },
	{ "gcc_usb4_2_tmu_clk", &gcc.mux, 0x135 },
	{ "gcc_video_ahb_clk", &gcc.mux, 0xa8 },
	{ "gcc_video_axi0_clk", &gcc.mux, 0xad },
	{ "gcc_video_axi1_clk", &gcc.mux, 0xae },
	{ "gcc_video_xo_clk", &gcc.mux, 0xaf },
	{ "measure_only_pcie_3_phy_aux_clk", &gcc.mux, 0x20b },
	{ "measure_only_pcie_3_pipe_clk", &gcc.mux, 0x20a },
	{ "measure_only_pcie_4_pipe_clk", &gcc.mux, 0x215 },
	{ "measure_only_pcie_5_pipe_clk", &gcc.mux, 0x21f },
	{ "measure_only_pcie_6a_phy_aux_clk", &gcc.mux, 0x237 },
	{ "measure_only_pcie_6a_pipe_clk", &gcc.mux, 0x236 },
	{ "measure_only_pcie_6b_phy_aux_clk", &gcc.mux, 0x22b },
	{ "measure_only_pcie_6b_pipe_clk", &gcc.mux, 0x22a },
	{ "measure_only_qusb4phy_0_gcc_usb4_rx0_clk", &gcc.mux, 0xe3 },
	{ "measure_only_qusb4phy_0_gcc_usb4_rx1_clk", &gcc.mux, 0xe4 },
	{ "measure_only_qusb4phy_1_gcc_usb4_rx0_clk", &gcc.mux, 0x108 },
	{ "measure_only_qusb4phy_1_gcc_usb4_rx1_clk", &gcc.mux, 0x109 },
	{ "measure_only_qusb4phy_2_gcc_usb4_rx0_clk", &gcc.mux, 0x12d },
	{ "measure_only_qusb4phy_2_gcc_usb4_rx1_clk", &gcc.mux, 0x12e },
	{ "measure_only_ufs_phy_rx_symbol_0_clk", &gcc.mux, 0x23e },
	{ "measure_only_ufs_phy_rx_symbol_1_clk", &gcc.mux, 0x244 },
	{ "measure_only_ufs_phy_tx_symbol_0_clk", &gcc.mux, 0x23d },
	{ "measure_only_usb3_phy_0_wrapper_gcc_usb30_pipe_clk", &gcc.mux, 0xde },
	{ "measure_only_usb3_phy_1_wrapper_gcc_usb30_pipe_clk", &gcc.mux, 0x103 },
	{ "measure_only_usb3_phy_2_wrapper_gcc_usb30_pipe_clk", &gcc.mux, 0x128 },
	{ "measure_only_usb3_uni_phy_mp_gcc_usb30_pipe_0_clk", &gcc.mux, 0x151 },
	{ "measure_only_usb3_uni_phy_mp_gcc_usb30_pipe_1_clk", &gcc.mux, 0x153 },
	{ "measure_only_usb4_0_phy_gcc_usb4_pcie_pipe_clk", &gcc.mux, 0xe2 },
	{ "measure_only_usb4_0_phy_gcc_usb4rtr_max_pipe_clk", &gcc.mux, 0xe1 },
	{ "measure_only_usb4_1_phy_gcc_usb4_pcie_pipe_clk", &gcc.mux, 0x107 },
	{ "measure_only_usb4_1_phy_gcc_usb4rtr_max_pipe_clk", &gcc.mux, 0x106 },
	{ "measure_only_usb4_2_phy_gcc_usb4_pcie_pipe_clk", &gcc.mux, 0x12c },
	{ "measure_only_usb4_2_phy_gcc_usb4rtr_max_pipe_clk", &gcc.mux, 0x12b },

	/* AV1E_CC entries */
	{ "av1e_cc_ahb_clk", &av1e_cc, 0x9 },
	{ "av1e_cc_av1e_core_axi_clk", &av1e_cc, 0x3 },
	{ "av1e_cc_av1e_core_clk", &av1e_cc, 0x1 },
	{ "av1e_cc_av1e_gdsc_noc_ahb_clk", &av1e_cc, 0x7 },
	{ "av1e_cc_av1e_noc_ahb_clk", &av1e_cc, 0x8 },
	{ "av1e_cc_av1e_noc_core_axi_clk", &av1e_cc, 0x5 },
	{ "av1e_cc_av1e_noc_xo_clk", &av1e_cc, 0xb },
	{ "measure_only_av1e_cc_av1e_cc_xo_clk", &av1e_cc, 0xa },
	{ "measure_only_av1e_cc_sleep_clk", &av1e_cc, 0xc },

	/* CAM_CC entries */
	{ "cam_cc_bps_ahb_clk", &cam_cc, 0x17 },
	{ "cam_cc_bps_clk", &cam_cc, 0x18 },
	{ "cam_cc_bps_fast_ahb_clk", &cam_cc, 0x16 },
	{ "cam_cc_camnoc_axi_nrt_clk", &cam_cc, 0x57 },
	{ "cam_cc_camnoc_axi_rt_clk", &cam_cc, 0x49 },
	{ "cam_cc_camnoc_dcd_xo_clk", &cam_cc, 0x4a },
	{ "cam_cc_camnoc_xo_clk", &cam_cc, 0x60 },
	{ "cam_cc_cci_0_clk", &cam_cc, 0x44 },
	{ "cam_cc_cci_1_clk", &cam_cc, 0x45 },
	{ "cam_cc_core_ahb_clk", &cam_cc, 0x4d },
	{ "cam_cc_cpas_ahb_clk", &cam_cc, 0x46 },
	{ "cam_cc_cpas_bps_clk", &cam_cc, 0x19 },
	{ "cam_cc_cpas_fast_ahb_clk", &cam_cc, 0x47 },
	{ "cam_cc_cpas_ife_0_clk", &cam_cc, 0x25 },
	{ "cam_cc_cpas_ife_1_clk", &cam_cc, 0x2a },
	{ "cam_cc_cpas_ife_lite_clk", &cam_cc, 0x34 },
	{ "cam_cc_cpas_ipe_nps_clk", &cam_cc, 0x1b },
	{ "cam_cc_cpas_sfe_0_clk", &cam_cc, 0x39 },
	{ "cam_cc_csi0phytimer_clk", &cam_cc, 0x9 },
	{ "cam_cc_csi1phytimer_clk", &cam_cc, 0xc },
	{ "cam_cc_csi2phytimer_clk", &cam_cc, 0xe },
	{ "cam_cc_csi3phytimer_clk", &cam_cc, 0x10 },
	{ "cam_cc_csi4phytimer_clk", &cam_cc, 0x12 },
	{ "cam_cc_csi5phytimer_clk", &cam_cc, 0x14 },
	{ "cam_cc_csid_clk", &cam_cc, 0x48 },
	{ "cam_cc_csid_csiphy_rx_clk", &cam_cc, 0xb },
	{ "cam_cc_csiphy0_clk", &cam_cc, 0xa },
	{ "cam_cc_csiphy1_clk", &cam_cc, 0xd },
	{ "cam_cc_csiphy2_clk", &cam_cc, 0xf },
	{ "cam_cc_csiphy3_clk", &cam_cc, 0x11 },
	{ "cam_cc_csiphy4_clk", &cam_cc, 0x13 },
	{ "cam_cc_csiphy5_clk", &cam_cc, 0x15 },
	{ "cam_cc_icp_ahb_clk", &cam_cc, 0x43 },
	{ "cam_cc_icp_clk", &cam_cc, 0x42 },
	{ "cam_cc_ife_0_clk", &cam_cc, 0x24 },
	{ "cam_cc_ife_0_dsp_clk", &cam_cc, 0x26 },
	{ "cam_cc_ife_0_fast_ahb_clk", &cam_cc, 0x28 },
	{ "cam_cc_ife_1_clk", &cam_cc, 0x29 },
	{ "cam_cc_ife_1_dsp_clk", &cam_cc, 0x2b },
	{ "cam_cc_ife_1_fast_ahb_clk", &cam_cc, 0x2d },
	{ "cam_cc_ife_lite_ahb_clk", &cam_cc, 0x37 },
	{ "cam_cc_ife_lite_clk", &cam_cc, 0x33 },
	{ "cam_cc_ife_lite_cphy_rx_clk", &cam_cc, 0x36 },
	{ "cam_cc_ife_lite_csid_clk", &cam_cc, 0x35 },
	{ "cam_cc_ipe_nps_ahb_clk", &cam_cc, 0x1e },
	{ "cam_cc_ipe_nps_clk", &cam_cc, 0x1a },
	{ "cam_cc_ipe_nps_fast_ahb_clk", &cam_cc, 0x1f },
	{ "cam_cc_ipe_pps_clk", &cam_cc, 0x1c },
	{ "cam_cc_ipe_pps_fast_ahb_clk", &cam_cc, 0x20 },
	{ "cam_cc_jpeg_clk", &cam_cc, 0x40 },
	{ "cam_cc_mclk0_clk", &cam_cc, 0x1 },
	{ "cam_cc_mclk1_clk", &cam_cc, 0x2 },
	{ "cam_cc_mclk2_clk", &cam_cc, 0x3 },
	{ "cam_cc_mclk3_clk", &cam_cc, 0x4 },
	{ "cam_cc_mclk4_clk", &cam_cc, 0x5 },
	{ "cam_cc_mclk5_clk", &cam_cc, 0x6 },
	{ "cam_cc_mclk6_clk", &cam_cc, 0x7 },
	{ "cam_cc_mclk7_clk", &cam_cc, 0x8 },
	{ "cam_cc_sfe_0_clk", &cam_cc, 0x38 },
	{ "cam_cc_sfe_0_fast_ahb_clk", &cam_cc, 0x3b },
	{ "measure_only_cam_cc_gdsc_clk", &cam_cc, 0x4e },
	{ "measure_only_cam_cc_sleep_clk", &cam_cc, 0x4f },

	/* DISP_CC entries */
	{ "disp_cc_mdss_accu_clk", &disp_cc, 0x47 },
	{ "disp_cc_mdss_ahb1_clk", &disp_cc, 0x38 },
	{ "disp_cc_mdss_ahb_clk", &disp_cc, 0x34 },
	{ "disp_cc_mdss_byte0_clk", &disp_cc, 0x14 },
	{ "disp_cc_mdss_byte0_intf_clk", &disp_cc, 0x15 },
	{ "disp_cc_mdss_byte1_clk", &disp_cc, 0x16 },
	{ "disp_cc_mdss_byte1_intf_clk", &disp_cc, 0x17 },
	{ "disp_cc_mdss_dptx0_aux_clk", &disp_cc, 0x20 },
	{ "disp_cc_mdss_dptx0_link_clk", &disp_cc, 0x1a },
	{ "disp_cc_mdss_dptx0_link_intf_clk", &disp_cc, 0x1c },
	{ "disp_cc_mdss_dptx0_pixel0_clk", &disp_cc, 0x1e },
	{ "disp_cc_mdss_dptx0_pixel1_clk", &disp_cc, 0x1f },
	{ "disp_cc_mdss_dptx0_usb_router_link_intf_clk", &disp_cc, 0x1b },
	{ "disp_cc_mdss_dptx1_aux_clk", &disp_cc, 0x27 },
	{ "disp_cc_mdss_dptx1_link_clk", &disp_cc, 0x23 },
	{ "disp_cc_mdss_dptx1_link_intf_clk", &disp_cc, 0x25 },
	{ "disp_cc_mdss_dptx1_pixel0_clk", &disp_cc, 0x21 },
	{ "disp_cc_mdss_dptx1_pixel1_clk", &disp_cc, 0x22 },
	{ "disp_cc_mdss_dptx1_usb_router_link_intf_clk", &disp_cc, 0x24 },
	{ "disp_cc_mdss_dptx2_aux_clk", &disp_cc, 0x2e },
	{ "disp_cc_mdss_dptx2_link_clk", &disp_cc, 0x2a },
	{ "disp_cc_mdss_dptx2_link_intf_clk", &disp_cc, 0x2b },
	{ "disp_cc_mdss_dptx2_pixel0_clk", &disp_cc, 0x28 },
	{ "disp_cc_mdss_dptx2_pixel1_clk", &disp_cc, 0x29 },
	{ "disp_cc_mdss_dptx2_usb_router_link_intf_clk", &disp_cc, 0x2c },
	{ "disp_cc_mdss_dptx3_aux_clk", &disp_cc, 0x32 },
	{ "disp_cc_mdss_dptx3_link_clk", &disp_cc, 0x30 },
	{ "disp_cc_mdss_dptx3_link_intf_clk", &disp_cc, 0x31 },
	{ "disp_cc_mdss_dptx3_pixel0_clk", &disp_cc, 0x2f },
	{ "disp_cc_mdss_esc0_clk", &disp_cc, 0x18 },
	{ "disp_cc_mdss_esc1_clk", &disp_cc, 0x19 },
	{ "disp_cc_mdss_mdp1_clk", &disp_cc, 0x35 },
	{ "disp_cc_mdss_mdp_clk", &disp_cc, 0x11 },
	{ "disp_cc_mdss_mdp_lut1_clk", &disp_cc, 0x36 },
	{ "disp_cc_mdss_mdp_lut_clk", &disp_cc, 0x12 },
	{ "disp_cc_mdss_non_gdsc_ahb_clk", &disp_cc, 0x39 },
	{ "disp_cc_mdss_pclk0_clk", &disp_cc, 0xf },
	{ "disp_cc_mdss_pclk1_clk", &disp_cc, 0x10 },
	{ "disp_cc_mdss_rscc_ahb_clk", &disp_cc, 0x3b },
	{ "disp_cc_mdss_rscc_vsync_clk", &disp_cc, 0x3a },
	{ "disp_cc_mdss_vsync1_clk", &disp_cc, 0x37 },
	{ "disp_cc_mdss_vsync_clk", &disp_cc, 0x13 },
	{ "deasure_only_disp_cc_sleep_clk", &disp_cc, 0x48 },
	{ "deasure_only_disp_cc_xo_clk", &disp_cc, 0x46 },

	/* GPU_CC entries */
	{ "gpu_cc_ahb_clk", &gpu_cc, 0x16 },
	{ "gpu_cc_crc_ahb_clk", &gpu_cc, 0x17 },
	{ "gpu_cc_cx_ff_clk", &gpu_cc, 0x20 },
	{ "gpu_cc_cx_gmu_clk", &gpu_cc, 0x1d },
	{ "gpu_cc_cxo_aon_clk", &gpu_cc, 0xb },
	{ "gpu_cc_cxo_clk", &gpu_cc, 0x1e },
	{ "gpu_cc_demet_clk", &gpu_cc, 0xd },
	{ "gpu_cc_freq_measure_clk", &gpu_cc, 0xc },
	{ "gpu_cc_gx_gmu_clk", &gpu_cc, 0x12 },
	{ "gpu_cc_gx_vsense_clk", &gpu_cc, 0xf },
	{ "gpu_cc_hub_aon_clk", &gpu_cc, 0x2d },
	{ "gpu_cc_hub_cx_int_clk", &gpu_cc, 0x1f },
	{ "gpu_cc_memnoc_gfx_clk", &gpu_cc, 0x21 },
	{ "gpu_cc_mnd1x_0_gfx3d_clk", &gpu_cc, 0x28 },
	{ "gpu_cc_mnd1x_1_gfx3d_clk", &gpu_cc, 0x29 },
	{ "gpu_cc_sleep_clk", &gpu_cc, 0x1b },
	{ "measure_only_gpu_cc_cb_clk", &gpu_cc, 0x2c },

	/* VIDEO_CC entries */
	{ "measure_only_video_cc_ahb_clk", &video_cc, 0x7 },
	{ "measure_only_video_cc_sleep_clk", &video_cc, 0xc },
	{ "measure_only_video_cc_xo_clk", &video_cc, 0xb },
	{ "video_cc_mvs0_clk", &video_cc, 0x3 },
	{ "video_cc_mvs0c_clk", &video_cc, 0x1 },
	{ "video_cc_mvs1_clk", &video_cc, 0x5 },
	{ "video_cc_mvs1c_clk", &video_cc, 0x9 },

	{}
};

struct debugcc_platform hamoa_debugcc = {
	"hamoa",
	hamoa_clocks,
};
