PIC18C601
Author: Molnár Károly

All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size ROM
size EEPROM
size Common
SFRs
Features Configuration Bits RAM map SFR map

PIC18C601
CONFIG1H (address:0x300001, mask:0x03, default:0x03)
OSC -- Oscillator Selection bits (bitmask:0x03)
OSC = LP | 0xFC | LP Oscillator.
OSC = EC | 0xFD | EC Oscillator.
OSC = HS | 0xFE | HS Oscillator.
OSC = RC | 0xFF | RC Oscillator.
CONFIG2L (address:0x300002, mask:0x41, default:0x41)
PWRT -- Power-up Timer Enable bit (bitmask:0x01)
PWRT = ON | 0xFE | PWRT enabled.
PWRT = OFF | 0xFF | PWRT disabled.
BW -- External Bus Data Width bit (bitmask:0x40)
BW = 8 | 0xBF | 8-bit External Bus mode.
BW = 16 | 0xFF | 16-bit External Bus mode.
CONFIG2H (address:0x300003, mask:0x0F, default:0x0F)
WDT -- Watchdog Timer Enable bit (bitmask:0x01)
WDT = OFF | 0xFE | WDT disabled (control is placed on the SWDTEN bit).
WDT = ON | 0xFF | WDT enabled.
WDTPS -- Watchdog Timer Postscale Select bits (bitmask:0x0E)
WDTPS = 1 | 0xF1 | 1:1.
WDTPS = 2 | 0xF3 | 1:2.
WDTPS = 4 | 0xF5 | 1:4.
WDTPS = 8 | 0xF7 | 1:8.
WDTPS = 16 | 0xF9 | 1:16.
WDTPS = 32 | 0xFB | 1:32.
WDTPS = 64 | 0xFD | 1:64.
WDTPS = 128 | 0xFF | 1:128.
CONFIG4L (address:0x300006, mask:0x01, default:0x01)
STVR -- Stack Full/Underflow RESET Enable bit (bitmask:0x01)
STVR = OFF | 0xFE | Stack Full/Underflow will not cause RESET.
STVR = ON | 0xFF | Stack Full/Underflow will cause RESET.

This page generated automatically by the device-help.pl program (2022-01-30 15:56:10 UTC) from the 8bit_device.info file (rev: 1.44) of mpasmx and from the gputils source package (rev: svn Unversioned directory). The mpasmx is included in the MPLAB X.