PIC16F727
Author: Molnár Károly

All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size ROM
size EEPROM
size Common
SFRs
Features Configuration Bits RAM map SFR map

PIC16F727
CONFIG1 (address:0x2007, mask:0x377F, default:0x377F)
FOSC -- Oscillator Selection bits (bitmask:0x0007)
FOSC = LP | 0x3FF8 | LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN.
FOSC = XT | 0x3FF9 | XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN.
FOSC = HS | 0x3FFA | HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN.
FOSC = EC | 0x3FFB | EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN.
FOSC = INTOSCIO | 0x3FFC | INTOSCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN.
FOSC = INTOSCCLK | 0x3FFD | INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN.
FOSC = EXTRCIO | 0x3FFE | RCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN.
FOSC = EXTRCCLK | 0x3FFF | RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN.
WDTE -- Watchdog Timer Enable bit (bitmask:0x0008)
WDTE = OFF | 0x3FF7 | WDT disabled and can be enabled by SWDTEN bit of the WDTCON register.
WDTE = ON | 0x3FFF | WDT enabled.
PWRTE -- Power-up Timer Enable bit (bitmask:0x0010)
PWRTE = ON | 0x3FEF | PWRT enabled.
PWRTE = OFF | 0x3FFF | PWRT disabled.
MCLRE -- RE3/MCLR pin function select bit (bitmask:0x0020)
MCLRE = OFF | 0x3FDF | RE3/MCLR pin function is digital input, MCLR internally tied to VDD.
MCLRE = ON | 0x3FFF | RE3/MCLR pin function is MCLR.
CP -- Code Protection bit (bitmask:0x0040)
CP = ON | 0x3FBF | Program memory code protection is enabled.
CP = OFF | 0x3FFF | Program memory code protection is disabled.
BOREN -- Brown-out Reset Selection bits (bitmask:0x0300)
BOREN = OFF | 0x3CFF | BOR disabled.
BOREN = NSLEEP | 0x3EFF | BOR enabled during operation and disabled in Sleep.
BOREN = ON | 0x3FFF | BOR enabled.
BORV -- Brown-out Reset Voltage selection bit (bitmask:0x0400)
BORV = 25 | 0x3BFF | Brown-out Reset Voltage (VBOR) set to 2.5 V nominal.
BORV = 19 | 0x3FFF | Brown-out Reset Voltage (VBOR) set to 1.9 V nominal.
PLLEN -- INTOSC PLLEN Enable Bit (bitmask:0x1000)
PLLEN = OFF | 0x2FFF | INTOSC Frequency is 500 kHz.
PLLEN = ON | 0x3FFF | INTOSC Frequency is 16MHz (32x).
DEBUG -- In-Circuit Debugger Mode bit (bitmask:0x2000)
DEBUG = ON | 0x1FFF | In-Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger.
DEBUG = OFF | 0x3FFF | In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins.
CONFIG2 (address:0x2008, mask:0x0030, default:0x0030)
VCAPEN -- Voltage Regulator Capacitor Enable bits (bitmask:0x0030)
VCAPEN = RA0 | 0x3FCF | VCAP functionality is enabled on RA0.
VCAPEN = RA5 | 0x3FDF | VCAP functionality is enabled on RA5.
VCAPEN = RA6 | 0x3FEF | VCAP functionality is enabled on RA6.
VCAPEN = DIS | 0x3FFF | All VCAP pin functions are disabled.

This page generated automatically by the device-help.pl program (2022-01-30 15:56:09 UTC) from the 8bit_device.info file (rev: 1.44) of mpasmx and from the gputils source package (rev: svn Unversioned directory). The mpasmx is included in the MPLAB X.