PIC12F752
Author: Molnár Károly

All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size ROM
size EEPROM
size Common
SFRs
Features Configuration Bits RAM map SFR map

PIC12F752
CONFIG (address:0x2007, mask:0x1F79, default:0x1F79)
FOSC0 -- FOSC: Oscillator Selection bit (bitmask:0x0001)
FOSC0 = INT | 0x3FFE | Internal oscillator mode. I/O function on RA5/CLKIN.
FOSC0 = EC | 0x3FFF | EC oscillator mode. CLKIN function on RA5/CLKIN.
WDTE -- Watchdog Timer Enable bit (bitmask:0x0008)
WDTE = OFF | 0x3FF7 | Watchdog Timer disabled.
WDTE = ON | 0x3FFF | Watchdog Timer enabled.
PWRTE -- Power-up Timer Enable bit (bitmask:0x0010)
PWRTE = ON | 0x3FEF | Power-up Timer enabled.
PWRTE = OFF | 0x3FFF | Power-up Timer disabled.
MCLRE -- MCLR/VPP Pin Function Select bit (bitmask:0x0020)
MCLRE = OFF | 0x3FDF | MCLR pin is alternate function.
MCLRE = ON | 0x3FFF | MCLR pin is MCLR function with internal weak pullup.
CP -- Code Protection bit (bitmask:0x0040)
CP = ON | 0x3FBF | Program memory code protection is enabled.
CP = OFF | 0x3FFF | Program memory code protection is disabled.
BOREN -- Brown-out Reset Enable bits (bitmask:0x0300)
BOREN = DIS | 0x3CFF | BOR disabled.
BOREN = SLEEP_DIS | 0x3EFF | BOR enabled during operation and disabled in Sleep.
BOREN = EN | 0x3FFF | BOR enabled.
WRT -- Flash Program Memory Self Write Enable bit (bitmask:0x0C00)
WRT = ALL | 0x33FF | 000h to 3FFh self-write protected.
WRT = HALF | 0x37FF | 000h to 1FFh self-write protected.
WRT = FOURTH | 0x3BFF | 000h to 0FFh self-write protected.
WRT = OFF | 0x3FFF | Flash self-write protection off.
CLKOUTEN -- Clock Out Enable bit (bitmask:0x1000)
CLKOUTEN = ON | 0x2FFF | CLKOUT function enabled. CLKOUT pin is CLKOUT.
CLKOUTEN = OFF | 0x3FFF | CLKOUT function disabled. CLKOUT pin acts as I/O.

This page generated automatically by the device-help.pl program (2022-01-30 15:56:09 UTC) from the 8bit_device.info file (rev: 1.44) of mpasmx and from the gputils source package (rev: svn Unversioned directory). The mpasmx is included in the MPLAB X.