The Logical Effort tool examines a digital schematic and determines the optimal transistor size to use in order to get maximum speed. The tool is based on the book Logical Effort, by Ivan Sutherland, Bob Sproull, and David Harris (Morgan Kaufmann, San Francisco, 1999). It is highly recommended that the user be familiar with the concept of this book before using the Logical Effort Tool.




To control Logical Effort, use the "Logical Effort" preferences (in menu File / Preferences..., "Tools" section, "Logical Effort" tab) . Besides setting the maximum stage gain for whole-cell analysis, the dialog allows other settings.


Figure 9.14

Two commands may be given to the Logical Effort tool (in menu Tool / Logical Effort):


Optimize for Equal Gate Delays

Optimizes all Logical Effort gates (cells) to have the same delay. The delay is specified by the Global fan-out (step-up) option. This is NOT a path optimization algorithm.

A Logical Effort gate is simply a schematic or layout cell that conforms to the following specifications:

Figure 9.25

On the input and output exports of the cell, we can define an attribute named "le" (double-click on the export text to get the Export Properties dialog, then click the Attributes button to define the attribute). The value of this attribute is the logical effort of that port. For example, a NAND gate typically has a logical effort on each input of 4/3, and an output logical effort of 2. An inverter is defined to have an input logical effort of 1, and an output logical effort of 1.

The size assigned to the logical effort gate is retrieved via the "LE.getdrive()" call. This value can then be used to size transistors within the gate. The size retrieved is scaled with respect to a minimum sized inverter (as are all other logical effort parameters). So a size of "1" denotes a minimum sized inverter.

While these attributes are defined on the layout or schematic cell definition, they must also be present on the instantiated icon or instance of that definition. By default this will be so.

Finally, this command should be performed on a cell containing instances of Logical Effort gates. There must be at least one load that is driven by the gates in order for them to be sized. A load is either a transistor or a capacitor. Gates that do not drive loads, or that do not drive gates that drive loads, will not be assigned sizes.

Advanced Features

There are several advanced features that may be added to the cell definition:


Caching Versus Non-Caching Sizing

It is intended that both the caching and non-caching algorithms obtain exactly the same result, however due to the difficulty in obtaining and maintaining correctness when it comes to caching, the non-caching algorithm is also available.

Back Annotate Wire Loads for the Current Cell

The Back Annotate Wire Lengths for Current Cell command runs NCC on the current cell against it's matching layout or schematic cell. Assuming they match, for each LEWIRE in the schematic cell, it finds the half-perimeter of the matching wire in the layout cell (as if the layout was flattened), and then changes the "L" parameter on the LEWIRE to the value. Note, back-annotation is only performed on top level LEWIREs, and it takes into account the wire's length throughout the layout hierarhcy.

Clear LE Sizes

LE sizes are stored as parameters on the LEGATE. Sometimes the sheer number of sizes can overwhelm the allocated process memory, and can also bloat file sizes when they are no longer needed. The Clear Sizes on Selected Node(s) and Clear Sizes in all Libraries commands provide ways to delete saved sizes on a per-node basis, or globally.

Print Info for Selected Node

After running sizing, information about a specific logical effort gate can be found by selecting the gate instance and running this command.